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Pentium® Processor Low-Power Module
Mobile Pentium® processor On-die, primary 16-Kbyte Instruction cache 16-Kbyte Write Back Data cache On-die, 256-Kbyte cache Eight-way associative Runs speed processor core Fully compatible with previous Intel mobile microprocessors Binary compatible with applications Support MMXtechnology Supports streaming SIMD Power management features that provide low-power dissipation Quick Start mode Deep Sleep mode Integrated math co-processor Integrated active thermal feedback (ATF) system Programmable trip point interrupt poll mode temperature reading
Intel 82443BX Host Bridge/Controller DRAM controller supports 3.3-V SDRAM Supports CLKRUN# protocol SDRAM clock enable support selfrefresh SDRAM during Suspend mode control only, Specification Revision compliant Supports single 66-MHz, 3.3-V device Thermal transfer plate (TTP) heat dissipation Above peak efficiency Integrated solution
Order Number: 273299-001 January 2000
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Pentium® Processor Low-Power Module
Contents
Introduction
References
Architecture Overview Signal Information
Signal Definitions.10 3.1.1 Signal List 3.1.2 Memory Signal Description 3.1.3 Signals 3.1.4 Signals. 3.1.5 Processor PIIX4E Sideband Signals 3.1.6 Power Management Signals 3.1.7 Clock Signals.16 3.1.8 Voltage Signals 3.1.9 JTAG Pins. 3.1.10 Miscellaneous Pins. Connector Assignments Assignments Pentium® Processor Low-Power Module Cache 82443BX Host Bridge/Controller 4.3.1 Memory Organization 4.3.2 Reset Strap Options 4.3.3 Interface 4.3.4 Interface Power Management 4.4.1 Clock Control Architecture. 4.4.1.1 Normal State 4.4.1.2 Auto Halt State 4.4.1.3 Stop Grant State. 4.4.1.4 Quick Start State 4.4.1.5 HALT/Grant Snoop State1234 4.4.1.6 Sleep State 4.4.1.7 Deep Sleep State
Functional Description.
Electrical Specifications
Requirements. Requirements Processor Core Voltage Regulation 5.3.1 Voltage Regulator Efficiency 5.3.2 Voltage Regulator Control 5.3.3 Power Planes: Bulk Capacitance Requirements 5.3.3.1 V_DC Decoupling 5.3.4 Surge Current Guidelines
Pentium® Processor Low-Power Module
Power System Protection. 5.0-V Power Supply Overcurrent Protection Slew-rate Control. Undervoltage Lockout: Circuit Description, V_DC_UVlock(out) 5.3.4.6 Overvoltage Lockout: Circuit Description Active Thermal Feedback Thermal Sensor Configuration Register
5.3.4.1 5.3.4.2 5.3.4.3 5.3.4.4 5.3.4.5
Mechanical Specification
Module Dimensions. 6.1.1 Location Connector 6.1.2 Printed Circuit Board 6.1.3 Height Restrictions Thermal Transfer Plate Physical Support 6.3.1 Mounting Requirements 6.3.2 Weight
Thermal Specification
Thermal Design Power.
Labeling Information. Environmental Standards
Figures
Pentium® Processor Low-Power Module Block Diagram. 400-Pin Connector Footprint. Clock Control States BCLK Waveform Processor Core Pins V_CORE Efficiency Chart Power Sequence Timing V_DC Decoupling Circuit Example V_DC Power System Protection Block Diagram Overcurrent Protection Circuit Example Undervoltage Lockout Circuit Example Undervoltage Lockout Model Overvoltage Lockout Circuit Example Overvoltage Lockout Model Recommended Power Supply Protection Circuit System Electronics Simulation V_DC Voltage Skew Board Dimensions Board Dimensions Connector Orientation. Power Module Printed Circuit Board Thickness Keep-out Zone 82443BX Thermal Transfer Plate.
Pentium® Processor Low-Power Module
Thermal Transfer Plate Standoff Holes, Board Edge Clearance, Containment Ring Product Tracking Code.
Tables
Related Documents. Connector Signal Summary Memory Signal Descriptions. Signal Descriptions Signal Descriptions. Processor PIIX4E Sideband Signal Descriptions Power Management Signal Descriptions Clock Signal Descriptions. Voltage Descriptions JTAG Descriptions. Miscellaneous Descriptions. Connector Assignment Rows A-E. Connector Assignment Rows Connector Specifications.22 Configuration Straps 82443BX Host Bridge/Controller Clock State Characteristics Requirements. Specifications Processor Core Pins BCLK Signal Quality Specifications Processor Core.32 V_CORE Power Conversion Efficiency. Voltage Signal Definitions VR_ON In-Rush Current Capacitance Requirement Power Plane Thermal Sensor SMBus Address Thermal Sensor Configuration Register Thermal Design Power Specification Environmental Standards
Pentium® Processor Low-Power Module
Revision History
Date January 2000 Revision Initial Release Updates
Pentium® Processor Low-Power Module
Introduction
This document provides technical specifications integrating Pentium® Processor Low-Power Module into latest applied computing systems today's embedded market. Building around this design gives system manufacturer these advantages:
Avoids complexities associated with designing high-speed processor core logic boards. Provides upgrade path from previous Intel Low-Power Modules using standard interface.
References
Refer following documents additional information relating Pentium Processor Low-Power Module.
Table
Related Documents
Document Title Mobile Pentium® Processor BGA2 Micro-PGA2 Packages MHz, MHz, datasheet Mobile Pentium® Processor Specification Update Intel 440BX AGPSet: 82443BX Host Bridge/Controller datasheet Intel 440BX AGPset 82443BX Host Bridge/Controller Specification Update 82371AB PCI-to-ISA/IDE Xcelerator (PIIX4) datasheet 82371EB PCI-to-ISA/IDE Xcelerator (PIIX4E) Specification Update CK97 Clock Synthesizer Design Guidelines Intel Pentium Processor Low-Power Module Design Guide Low-Power Module Memory Simulation Methodology PLow-Power Module SDRAM DIMM Routing Guidelines Mobile Pentium Processor Pentium Processor Mobile Module Thermal Sensor Interface Specifications 66/100 SDRAM Unbuffered SO-DIMM Specification
Order Number 245302 245306 290633 290639 290562 290635 243867 273319 273316 273317 243724 http://www.intel.com/design/ chipsets/memory/sdram.htm
Pentium® Processor Low-Power Module
Architecture Overview
module contains mobile Pentium processor core that runs with 100-MHz processor system (PSB) speed. Intel® 440BX AGPset provides immediate system-level support includes PIIX4E PCI/ISA bridge Intel 82443BX Host Bridge/Controller. PIIX4E provides extensive power management capabilities supports 82443BX Host Bridge/Controller. system electronics should include PIIX4E device connect Low-Power Module. features Intel 82443BX Host Bridge/Controller include: DRAM controller supporting SDRAM with burst read x-1-1-1; CLKRUN# signal request PIIX4E regulate clock bus; 82443BX clock enables Self-Refresh mode SDRAM during Suspend mode compatible with SMRAM (C_SMRAM) Extended SMRAM (E_SMRAM) modes power management; E_SMRAM mode supports write-back cacheable SMRAM Mbyte. thermal transfer plate mobile Pentium processor 82443BX Host Bridge/Controller provides heat dissipation thermal attach points manufacturer's thermal solution. on-board voltage regulator converts system voltage processor's core voltage. Isolating processor voltage requirements allows system manufacturer incorporate different processor variants into single applied computing system that supports input voltage integrated module voltage regulator enables above peak efficiency de-couples processor voltage requirements from system. Also incorporated active thermal feedback (ATF) sensing, compliant ACPI Specification 1.0. integrated system management (SMBus) compliant thermal sensor supports internal external temperature sensing with programmable trip points. Figure illustrates block diagram Pentium Processor Low-Power Module.
Pentium® Processor Low-Power Module
Figure Pentium® Processor Low-Power Module Block Diagram
Processor Core Voltage
Mobile Pentium® Processor Core
Voltage
Sense
Sideband Pullup (V_CPUPU)
Clock Driver (V_CLK)
V_DC (5.0V)
Memory
GCLKO
400-Pin Board-to-Board Connector
GCLKI
PCLK
PIIX4E/M Sidebands
HCLK0
82443BX "Northbridge"
DCLKWR SMBUS
DCLKO
Pentium® Processor Low-Power Module
Signal Information
This section provides information signal groups Pentium Processor Low-Power Module.
Signal Definitions
Table provides list signals category corresponding number signals each category. proper signal termination, Low-Power Module Design Guide (order number 273319).
Table
Connector Signal Summary
Signal Group Memory Processor/PIIX4E Sideband Power Management Clocks Voltage: V_DC Voltage: V_3S Voltage: Voltage: Voltage: VCCAGP Voltage: V_CPUPU Voltage: V_CLK ITP/JTAG Module Ground Reserved Total Number Pins
Pentium® Processor Low-Power Module
3.1.1
Signal List
following notations used denote signal type: Input Output Open-drain output requiring pullup resistor Open-drain input requiring pullup resistor Input/Open-drain output requiring pullup resistor Bi-directional input/output
signal description also includes type buffer used particular signal: GTL+ CMOS Open-drain GTL+ interface signal interface signals interface signals CMOS signals depending their functional group.
3.1.2
Memory Signal Description
Table provides descriptions memory interface signals.
Table
Memory Signal Descriptions
Name Type CMOS CMOS CMOS Voltage Description Memory Data: These signals carry Memory data during access DRAM. implemented tested Pentium Processor LowPower Module. supported Low-Power Modules. Chip Select (SDRAM): These pins activate SDRAMs. SDRAM accepts command when active low. Input/Output Data Mask (SDRAM): These pins synchronized output enables during read cycle byte mask during write cycle. Memory Address (SDRAM): This column address DRAM. 82443BX Host Bridge/Controller identical sets address lines (MAA MAB#). Low-Power Module supports only address lines. additional addressing features, please refer Intel 440BX AGPSet: 82443BX Host Bridge/Controller Datasheet (Order number: 290633). Memory Write Enable (SDRAM): MWEA# should used write enable memory data bus. SDRAM Address Strobe (SDRAM): When active low, this signal latches Address positive edge clock. This signal also allows access pre-charge. SDRAM Column Address Strobe (SDRAM): When active low, this signal latches Column Address positive edge clock also allows Column access. SDRAM Clock Enable (SDRAM): SDRAM clock enable pin. When these signals deasserted, SDRAM enters power-down mode. Each individually controlled clock enable. Memory Data: These signals connected DRAM data bus. They terminated Low-Power Module.
MECC[7:0]
CSA[5:0]# DQMA[7:0] MAB[9:0]# MAB[10] MAB[12:11]# MAB[13] MWEA#
CMOS
CMOS CMOS CMOS CMOS CMOS
SRASA#
SCASA#
CKE[5:0]
MD[63:0]
Pentium® Processor Low-Power Module
3.1.3
Signals
Table provides descriptions interface signals.
Table
Signal Descriptions (Sheet
Name Type Voltage Description Address/Data: These signals standard address data lines. This functions same AD[31:0] bus. address driven with FRAME# assertion, data driven received following clocks. Command/Byte Enable: This carries command information during cycles when PIPE# used. During write, this contains byte enable information. command driven with FRAME# assertion, byte enables corresponding supplied requested data driven subsequent clocks. Frame: This signal used during transactions. GFRAME# remains deasserted internal pullup resistor. Assertion this signal indicates address phase transfer negation indicates that cycle initiator desires more data transfer. Device Select: This signal provides same function DEVSEL#. GDEVSEL# used during transactions. 82443BX Host Bridge/Controller drives this signal when initiator attempting access DRAM. DEVSEL# asserted medium decode time. Initiator Ready: This signal indicates that compliant target ready provide write data current transaction. signal asserted when initiator ready data transfer. Target Ready: This signal indicates that compliant master ready provide write data current transaction. signal asserted when target ready data transfer. Stop: This signal same function STOP#. This signal used during transactions. Asserted target request master stop current transaction. Request: master requests AGP. Grant: same function PCI. Additional information provided ST[2:0] bus. example: Grant: Permission given master PCI. Parity: single parity provided over GAD[31:0] GC/BE[3:0]. This signal used during transactions. Pipelined Request: current master asserts this signal indicate that full width address will queued target. master queues request each rising clock edge while PIPE# asserted. Sideband Address: This provides additional conduit pass address commands 82443BX Host Bridge/Controller from master. Read Buffer Full: This signal indicates when master ready accept previously requested, low-priority read data.
GAD[31:0]
GC/BE[3:0]#
GFRAME#
GDEVSEL#
GIRDY#
GTRDY#
GSTOP#
GREQ#
GGNT#
GPAR
PIPE#
SBA[7:0]
RBF#
Pentium® Processor Low-Power Module
Table
Signal Descriptions (Sheet
Name ST[2:0] Type Voltage Description Status Bus: This provides information from arbiter Master what These bits only have meaning when GGNT asserted. Strobes: These signals provide timing double-clocked data bus. agent providing data drives these signals. These signals identical copies each other. Sideband Strobe: This signal provides timing sideband bus. SBA[7:0] (AGP master) drives sideband strobe.
ADSTB[B:A]
SBSTB
3.1.4
Signals
Table provides descriptions signals.
Table
Signal Descriptions (Sheet
Name AD[31:0] Type Voltage Description Address/Data: These standard address data lines. address driven with FRAME# assertion, data driven received following clocks. Command/Byte Enable: command driven with FRAME# assertion, byte enables corresponding supplied requested data driven following clocks. Frame: Assertion this signal indicates address phase transfer. Negation this signal indicates that cycle initiator desires more data transfer. Device Select: 82443BX Host Bridge/Controller drives this signal when initiator attempting access DRAM. DEVSEL# asserted medium decode time. Initiator Ready: This signal asserted when initiator ready data transfer. Target Ready: This signal asserted when target ready data transfer. Stop: This signal asserted target request master stop current transaction. Lock: This signal indicates exclusive operation require multiple transactions complete. When LOCK# asserted, nonexclusive transactions proceed. 82443BX supports lock initiated cycles only. initiated locked cycles supported. Request: master requests bus. Grant: Permission given master PCI.
C/BE[3:0]
FRAME#
DEVSEL#
IRDY# TRDY# STOP#
PLOCK#
REQ[4:0]# GNT[4:0]#
Pentium® Processor Low-Power Module
Table
Signal Descriptions (Sheet
Name Type Voltage Description Hold: This signal comes from expansion bridge bridge request PCI. 82443BX Host Bridge/Controller drains DRAM write buffers, drains processor-to-PCI posting buffers, acquires host before granting request PHLDA#. This ensures that timing masters. PHOLD# protocol been modified include support passive release. Hold Acknowledge: This signal driven 82443BX Host Bridge/Controller grant expansion bridge. PHLDA# protocol been modified include support passive release. Parity: single parity provided over AD[31:0] C/BE[3:0]#. System Error: 82443BX asserts this signal indicate error condition. further information, refer Intel 440BX AGPSet: 82443BX Host Bridge/Controller datasheet (Order Number: 290633). Clock Run: This open-drain output input. 82443BX Host Bridge/Controller requests central resource, PIIX4E, start maintain clock asserting CLKRUN#. 82443BX Host Bridge/Controller three-states CLKRUN# upon deassertion Reset (since running upon deassertion Reset). Reset: When asserted, this signal asynchronously resets 82443BX Host Bridge/Controller. signals also three-state, compliant with Revision Specifications.
PHOLD#
PHLDA#
SERR#
CLKRUN#
PCI_RST#
CMOS
3.1.5
Processor PIIX4E Sideband Signals
Table provides descriptions processor PIIX4E sideband signals.
Table
Processor PIIX4E Sideband Signal Descriptions (Sheet
Name Type CMOS CMOS CMOS CMOS Voltage Description Numeric Coprocessor Error: This functions FERR# signal supporting coprocessor errors. This signal tied coprocessor error signal processor pulled active processor PIIX4E. Ignore Error: This open-drain signal connected Ignore Error processor driven PIIX4E. Initialization: INIT# asserted PIIX4E processor system initialization. This signal open-drain. Processor Interrupt: INTR driven PIIX4E signal processor that interrupt request pending needs serviced. This signal open-drain. Non-Maskable Interrupt: used force non-maskable interrupt processor. PIIX4E bridge generates when either SERR# IOCHK# asserted, depending Status Control Register programmed. This signal opendrain.
FERR#
V_CPUPU
IGNNE# INIT#
V_CPUPU V_CPUPU
INTR
V_CPUPU
CMOS
V_CPUPU
NOTE: Table V_CPUPU definition.
Pentium® Processor Low-Power Module
Table
Processor PIIX4E Sideband Signal Descriptions (Sheet
Name A20M# Type CMOS Voltage V_CPUPU Description Address Mask: When enabled, this open-drain signal causes processor emulate address wraparound Mbyte, which occurs Intel® 8086 processor. System Management Interrupt: SMI# active-low synchronous output from PIIX4E that asserted response many enabled hardware software events. SMI# open-drain signal asynchronous input processor. However, this chipset, SMI# synchronous PCLK. Stop Clock: STPCLK# active-low, synchronous open-drain output from PIIX4E that asserted response many hardware software events. STPCLK# connects directly processor synchronous PCICLK. When processor samples STPCLK# asserted, responds entering low-power state (Quick Start). processor exits this mode only when this signal deasserted.
SMI#
CMOS
V_CPUPU
STPCLK#
CMOS
V_CPUPU
NOTE: Table V_CPUPU definition.
3.1.6
Power Management Signals
Table provides descriptions power management signals. SM_CLK SM_DATA signals refer two-wire serial SMBus interface. Although this interface currently used solely digital thermal sensor, SMBus contains reserved serial addresses future use.
Table
Power Management Signal Descriptions
Name SUS_STAT1# Type CMOS Voltage V_3ALWAYS Description Suspend Status: This signal connects SUS_STAT1# output PIIX4E. SUS_STAT1# provides information host clock status asserted during suspend states. VR_ON: Voltage regulator This 3.3-V (5.0-V tolerant) signal controls operation voltage regulator. VR_ON should generated function PIIX4E SUSB# signal, which used controlling "Suspend State voltage planes. This signal should driven digital signal with rise/fall time less than equal (VIL, =0.4 VIH, =3.0 VR_PWRGD: This signal driven high Low-Power Module indicate that voltage regulator stable. signal pulled using 100-K resistor when inactive. used some combination generate system PWRGOOD signal. Power This signal must active least after power rail stable prior deassertion PCIRST#. Serial Clock: This clock signal used SMBus interface digital thermal sensor. Serial Data: Open-drain data signal SMBus interface digital thermal sensor. Interrupt: This signal open-drain output signal digital thermal sensor.
VR_ON
CMOS
VR_PWRGD
BXPWROK
CMOS CMOS CMOS CMOS
SM_CLK SM_DATA ATF_INT#
V_3ALWAYS 3.3-V supply generated whenever V_DC available supplied PIIX4E resume well.
Pentium® Processor Low-Power Module
3.1.7
Clock Signals
Table provides descriptions clock signals.
Table
Clock Signal Descriptions
Name Type Voltage Description Clock PCLK, input Low-Power Module, system's clocks. This clock used 82443BX Host Bridge/Controller logic clock domain. This clock stopped when PIIX4E PCI_STP# signal asserted and/or during suspend states. Host Clock This clock input Low-Power Module from CK100-M/CK100-SM clock source. processor 82443BX Host Bridge/Controller HCLK0. This clock stopped when PIIX4E CPU_STP# signal asserted and/or during suspend states. Host Clock This clock input Low-Power Module from CK100-M/CK100-SM clock source. This signal implemented Low-Power Modules. SDRAM Clock Out: 100-MHz SDRAM clock reference generated internally 82443BX Host Bridge/Controller onboard PLL. feeds external buffer that produces multiple copies SODIMMs. SDRAM Read Clock: feedback reference from SDRAM clock buffer. 82443BX Host Bridge/Controller uses this clock when reading data from SDRAM array. This signal implemented Low-Power Modules. DCLKWR CMOS CMOS SDRAM Write Clock: feedback reference from SDRAM clock buffer. 82443BX Host Bridge/Controller uses this clock when writing data SDRAM array. Clock GCLKIN input feedback reference from GCLKO signal. Clock Out: This signal generated 82443BX Host Bridge/Controller onboard from HCLK0 host clock reference. frequency GCLKO MHz. GCLKO output used feed both reference input pins 82443BX Host Bridge/Controller device. board layout must maintain complete symmetry loading trace geometry minimize clock skew. Frequency Select: This output indicates desired host clock frequency Low-Power Module.
PCLK
HCLK0
CMOS
V_CLK
HCLK1
CMOS CMOS
V_CLK
DCLK0
DCLKRD
CMOS
GCLKIN
GCLKO
CMOS
CMOS
V_3S
Pentium® Processor Low-Power Module
3.1.8
Voltage Signals
Table provides descriptions voltage signals.
Table
Voltage Descriptions
Name V_DC V_3S Type Number pins Description Input: note below. SUSB# Controlled power managed 3.3-V supply, output voltage regulator system electronics. This rail during STR, STD, Soff. SUSC# Controlled power managed 5.0-V supply. output voltage regulator system electronics. This rail during Soff.1,2 SUSC# Controlled power managed 3.3-V supply. output voltage regulator system electronics. This rail during Soff.1 Voltage: This voltage rail implemented LowPower Module defined upgrade purposes only. Intel recommends that this voltage rail connected system electronics. Processor Ring: Low-Power Module drives this signal power processor interface signals, such PIIX4E opendrain pullups processor PIIX4E sideband signals. V_CPUPU tied Processor Clock Rail: Low-Power Module drives V_CLK power CK100-M VDDCPU rail.
VCCAGP
V_CPUPU
V_CLK
NOTES: Refer 82371AB PCI-to-ISA/IDE Xcelerator (PIIX4) datasheet (Order Number 290562) additional information suspend modes. connecting V_DC system electronics, "V_DC Decoupling" page
Pentium® Processor Low-Power Module
3.1.9
JTAG Pins
Table provides descriptions JTAG signals, which system manufacturer implement JTAG chain port desired.
Table JTAG Descriptions
Name TCLK TRST# FS_PREQ# FS_PRDY# FS_RESET# Type Voltage V_CPUPU Description JTAG Test Data Out: serial output port. instructions data shifted processor from this port. JTAG Test Data serial input port. instructions data shifted into processor from this port. JTAG Test Mode Select: Controls controller change sequence. JTAG Test Clock: testability clock clocking JTAG boundary scan sequence. JTAG Test Reset: TRST# asynchronously resets controller processor. Debug Mode Request: This signal driven makes request enter debug mode. Debug Mode Ready: FS_PRDY# driven processor informs that processor debug mode. Processor Reset: processor reset status ITP. GTL+ Termination Voltage: Used POWERON debug port determine when target system POWERON pulled using resistor VTT. Other signals this power rail pullup.
NOTE: FS_RESET# FS_PRDY# pulled inside mobile Pentium® processor core.
3.1.10
Miscellaneous Pins
Table provides descriptions miscellaneous signal pins.
Table Miscellaneous Descriptions
Name Type CMOS RSVD Number Description Module Revision These pins track revision level LowPower Module. 100-K pullup resistor V_3S must placed system electronics these signals. "Labeling Information" page more detail. Ground Unallocated Reserved pins. Reserved pins must connected.
Module ID[3:0]
Ground Reserved
Pentium® Processor Low-Power Module
Connector Assignments
Table lists signals each connector system electronics. Refer "Pin Assignments" page assignments.
Table Connector Assignment Rows (Sheet
Number SBA5 GAD25 GAD30 RBF# BXPWROK MD36 MD41 MD43 MD14 MECC4 SCASA# CSA1# SRASA# RESERVED RESERVED RESERVED MAB8# RESERVED MAB13 CKE1 CKE5 RESERVED FS_RESET# FS_PRDY# RESERVED# RESERVED ADSTBB GAD24 GAD29 VCCAGP GAD1 RESERVED MD33 MD38 MD42 MD11 MD45 MECC0 MWEA# MID1 DQMA4 CSA2# CSA5# RESERVED MAB4# RESERVED RESERVED MAB11# MID2 CKE2 RESERVED# SMCLK SMDAT SBA6 GAD26 GAD4 GAD3 GAD2 MD37 MD40 MD44 ND15 MECC5 DQMA0 MID0 CSA4# MAB0# MAB2# MAB5# RESERVED MAB12# CKE3 MID3 DQMA2 RESERVED MD26 MD58 GAD31 SBA4 GAD27 GAD6 GAD5 ADSTBA CLKRUN# MD32 MD35 MD39 MD10 MD13 ND47 RESERVED DQMA1 DQMA5 CSA3# MAB1# RESERVED RESERVED RESERVED MSB9# RESERVED CKE0 RESERVED# DCLKWR FS_PREQ# MD57 TCLK SBA7 SBA0 GDA8 GC/BE0# GAD7 MD34 MD34 MD12 ND46 RESERVED CSA# RESERVED MAB3# MAB6# MAB7# MAB10 DCLK0 DCLKRD RESERVED# DQMA3 MD25 MD60 FERR# IGNNE#
Pentium® Processor Low-Power Module
Table Connector Assignment Rows (Sheet
Number RESERVED RESERVED V_CPUPU V_CLK RESERVED V_DC V_DC RESERVED V_DC V_DC RESERVED V_3S V_3S V_3S RESERVED V_DC V_DC TRST# V_3S V_3S V_3S RESERVED V_DC V_DC ATF_INT# V_3S V_3S V_3S RESERVED V_DC V_DC
Table Connector Assignment Rows (Sheet
Number GREQ# GGNT# GAD13 GAD12 GAD10 GAD11 GAD9 VCCAGP MECC1 SERR# AD16 AD19 AD23 AD27 PCI_RST# RESERVED IRDY# GNT1# DQMA6 MECC2 GSTOP# GPAR GAD15 GC/BE1# GAD14 VCCAGP C/BE0# AD10 AD13 TRDY# AD30 AD22 PHOLD# FRAME# GNT2# GNT4# PHLDA# MECC7 MD48 PIP# SBA1 SBA2 GAD16 GAD18 GFRAME# GTRDY# GDEVESEL# AD15 STOP# AD17 AD24 C/BE3# AD20 AD31 REQ2# GNT0# MD50 MD18 SBA3 SBSTB GAD20 GAD17 GC/BE2# GIRDY# VCCAGP AD12 C/BE1# DEVSEL# C/BE2# AD26 AD28 AD29 REQ1# REQ3# REQ4# MD51 MD52 GCLKI CGLK0 GAD23 GC/BE3# GAD22 GAD21 GAD19 GAD28 AD11 AD14 PLOCK# AD18 AD21 PCLK AD25 REQ0# GNT3# MD59 MD54 MD24
Pentium® Processor Low-Power Module
Table Connector Assignment Rows (Sheet
DQMA7 MECC6 MECC3 MD27 DMI# A20M# RESERVED V_DC V_DC MD16 MD17 MD49 MD28 MD29 INTR SUS_STAT1# STPCLK# RESERVED V_DC V_DC MD19 MD21 MD20 MD61 VR_ON VR_PWRGD INIT# RESERVED V_DC V_DC MD53 MD22 MD62 MD30 RESERVED V_DC V_DC MD23 MD55 MD56 MD63 MD31 HCLK0 HCLK1 RESERVED V_DC V_DC
Pentium® Processor Low-Power Module
Assignments
400-pin connector 1.27-mm pitch BGA-style surface mount. Refer "Height Restrictions" page size information. Figure shows 400-pin connector assignments.
Figure 400-Pin Connector Footprint
400-Pin Connector Footprint Assignments
Table summarizes some connector specifications. Table Connector Specifications
Parameter Contact Material Housing Current Voltage Electrical Insulation Resistance Termination Resistance Capacitance Mating Cycles Mechanical Connector Mating Force Contact Unmating Force Thermo-Plastic Molded Compound: 20-m maximum 20-mV open circuit with maximum contact Cycles (22.7 maximum (13.6 maximum Condition Copper Alloy Specification
Pentium® Processor Low-Power Module
Functional Description
Pentium® Processor Low-Power Module
Pentium Processor Low-Power Module runs with 100-MHz processor system (PSB).
Cache
on-die cache Kbyte, eight-way associative, runs speed processor core.
82443BX Host Bridge/Controller
Intel's 82443BX Host Bridge/Controller highly integrated device that combines controller, DRAM controller, controller into component. 82443BX Host Bridge/Controller multiple power management features designed applied computing systems such
CLKRUN#, feature that enables controlling clock 82443BX Host Bridge/Controller suspend modes, which include Suspend-To-RAM
(STR), Suspend-To-Disk (STD), Power-On-Suspend (POS)
System Management (SMRAM) power management modes, which include Compatible
SMRAM (C_SMRAM) Extended SMRAM (E_SMRAM). C_SMRAM traditional SMRAM feature implemented Intel chipsets. E_SMRAM feature that supports write-back cacheable SMRAM space Mbyte. minimize power consumption while system idle, internal 82443BX Host Bridge/Controller clock turned (gated off) when there processor activity. This accomplished setting G_CLK enable 82443BX power management register through system BIOS.
4.3.1
Memory Organization
memory interface 82443BX Host Bridge/Controller available connector. This allows following:
memory control signals, sufficient support three SO-DIMM sockets
banks SDRAM
signal each bank
Memory features supported 82443BX Host Bridge/Controller this product are:
Eight banks memory 256-Mbit memory devices Second memory address lines (MAA[13:0]) Extended Data (EDO) DRAM 66-MHz memory
Pentium® Processor Low-Power Module
clocking architecture supports SDRAM. tight timing requirements 100-MHz SDRAM clocks, clocking mode SDRAM memory configurations allows host SDRAM clocks generated from same clocking architecture system electronics. complete details about memory device support, organization, size, addressing when using SDRAM memory trace length guidelines, refer Low-Power Module SDRAM DIMM Routing Guidelines (order number 273317).
4.3.2
Reset Strap Options
Several strap options memory address define behavior Low-Power Module after reset. Other straps allowed override default settings. Table shows various straps their implementation.
Table Configuration Straps 82443BX Host Bridge/Controller
Signal MAB[12]# MAB[11]# MAB[10]# MAB[9]# MAB[7]# MAB[6]# Function Host Frequency Select Order Queue Depth Quick Start Select Disable Configuration Host Buffer Mode Select Module Default Setting Strapped high module strap, maximum queue depth Strapped high module Quick Start mode strap (AGP enabled) strap (Standard mode) Strapped high module mobile buffers Optional Override System Electronics None None None Strap high disable None None
4.3.3
Interface
interface 82443BX Host Bridge/Controller available connector. 82443BX Host Bridge/Controller supports Clockrun protocol power management. this protocol, devices assert CLKRUN# open-drain signal when they require interface. 82443BX Host Bridge/Controller responsible arbitrating bus. 82443BX Host Bridge/Controller support five masters. There five Request/Grant pairs (REQ[4:0]# GNT[4:0]#) available connector system electronics. interface connector only. devices that supported. 82443BX Host Bridge/Controller compliant with Specification, which improves worst case access latency from earlier specifications. 82443BX Host Bridge/Controller supports only Mechanism accessing configuration space. This implies that signals AD[31:11] available IDSEL signals. However, since 82443BX Host Bridge/Controller always device AD11 never asserted during configuration cycles IDSEL. 82443BX reserves AD12 AGPbus. AD13 first available address line usable IDSEL. Intel recommends that AD18 used PIIX4E.
Pentium® Processor Low-Power Module
4.3.4
Interface
82443BX Host Bridge/Controller compliant with Interface Specification Revision 1.0, which supports asynchronous interface coupling 82443BX core frequency. interface achieve real data throughput excess Mbytes second using graphics device. Actual bandwidth vary depending specific hardware software implementations.
4.4.1
Power Management
Clock Control Architecture
Low-Power Module's clock control architecture optimal applied computing designs. clock control architecture consists seven different clock states: Normal, Stop Grant, Auto Halt, Quick Start, HALT/Grant Snoop, Sleep, Deep Sleep. Auto Halt state provides low-power clock state that controlled through software execution instruction. Quick Start state provides very low-power, low-exit latency clock state that used hardware controlled "idle" states. Deep Sleep state provides extremely low-power state that used Power-On-Suspend states, which alternative shutting processor's power. exit latency Deep Sleep state been reduced Stop Grant Sleep states available Low-Power Module these states intended desktop server systems. Stop Grant state Quick Start clock state mutually exclusive. example, strapping option signal A15# chooses which state entered when STPCLK# signal asserted. Strapping A15# signal ground Reset enables Quick Start state. Otherwise, asserting STPCLK# signal puts processor into Stop Grant state. Table provides information clock control states Figure illustrates clock control architecture. Performing state transitions shown Figure neither recommended supported.
Table Clock State Characteristics
Clock State Normal Auto Halt Stop Grant Approximately clocks clocks Through Snoop, HALT/Grant Snoop state: immediate Through STPCLK#, Normal state: clocks HALT/Grant Snoop Sleep Deep Sleep clocks after snoop activity Stop Grant state clocks specified Exit Latency Processor Power Varies Snooping System Uses Normal program execution Software controlled entry-idle mode Hardware controlled entry/exit mobile throttling
Quick Start
Hardware controlled entry/exit mobile throttling
Supports snooping lowpower states Hardware controlled entry/exit mobile throttling Hardware controlled entry/exit mobile throttling
Intel Low-Power Modules support this clock control state.
Pentium® Processor Low-Power Module
Figure Clock Control States
Normal State
HS=false
STPCLK#
(!STPCLK# !HS) RESET# halt cycle halt break STPCLK# !STPCLK#
Quick Start
BCLK stopped BCLK
STPCLK# !QSE (!STPCLK# !HS) stop break !STPCLK# STPCLK# !QSE
Auto Halt
HS=true
Snoop serviced
Snoop occurs
Deep Sleep
Snoop occurs Snoop serviced Snoop occurs Snoop serviced
Stop Grant
HALT/Grant Snoop
SLP# !SLP# RESET# BCLK stopped
BCLK !QSE
Sleep
NOTES: Halt break A20M#, BINIT#, FLUSH#, INIT#, INTR, NMI, PREQ#, RESET#, SMI# instruction executed Processor Halt State Quick Start State Enabled Stop Grant Acknowledge cycle issued Stop break BINIT#, FLUSH#, RESET# low-power module does support shaded clock control states
Pentium® Processor Low-Power Module
4.4.1.1
Normal State
Normal state normal operating mode where processor's core clock running, processor actively executing instructions.
4.4.1.2
Auto Halt State
This low-power mode entered processor through execution instruction. power level this mode similar Stop Grant state. transition Normal state made halt break event (one following signals going active: NMI, INTR, BINIT#, INIT#, RESET#, FLUSH#, SMI#). Asserting STPCLK# signal while Auto Halt state causes processor transition Stop Grant state Quick Start state, where Stop Grant Acknowledge cycle issued. Deasserting STPCLK# causes processor return Auto Halt state without issuing Halt cycle. SMI# (System Management Interrupt) recognized Auto Halt state. return from handler either Normal state Auto Halt state. Intel® Architecture Software Developer's Manual, Volume III: System Programming Guide (order number 243192) more information. Halt cycle issued when returning Auto Halt state from System Management mode (SMM). FLUSH# signal serviced Auto Halt state. After flushing on-chip caches, processor returns Auto Halt state without issuing Halt cycle. Transitions A20M# PREQ# signals recognized while Auto Halt state.
4.4.1.3
Stop Grant State
Low-Power Module does support Stop Grant state. desktop systems, processor enters Stop Grant mode with assertion STPCLK# signal when configured Stop Grant state (via A15# strapping option). processor still respond snoop requests latch interrupts. Latched interrupts serviced when processor returns Normal state. Only occurrence each interrupt event latched. transition back Normal state made deassertion STPCLK# signal occurrence stop break event BINIT#, FLUSH#, RESET# assertion). processor returns Stop Grant state after completion BINIT# initialization unless STPCLK# been deasserted. RESET# assertion causes processor immediately initialize itself. However, processor stays Stop Grant state after initialization until STPCLK# deasserted. FLUSH# signal asserted, processor flushes on-chip caches returns Stop Grant state. transition Sleep state made assertion SLP# signal. While Stop Grant state, assertions SMI#, INIT#, INTR, LINT[1:0]) latched processor. These latched events serviced until processor returns Normal state. Only each event recognized upon return Normal state.
Pentium® Processor Low-Power Module
4.4.1.4
Quick Start State
processor enters this mode with assertion STPCLK# signal when processor configured Quick Start state (via A15# strapping option). Quick Start state, processor only capable acting snoop transactions generated priority device. Because snooping behavior, Quick Start only used single processor configurations. transition Deep Sleep state made stopping clock input processor. transition back Normal state (from Quick Start state) made only STPCLK# signal deasserted. While this state, processor limited ability respond input. incapable latching interrupts, servicing snoop transactions from symmetric masters, responding FLUSH# BINIT# assertions. Quick Start state, processor does respond properly input signal other than STPCLK#, RESET#, BPRI#. other input signal changes, then behavior processor will unpredictable. serial interrupt messages begin progress while processor Quick Start state. RESET# assertion causes processor immediately initialize itself, processor stays Quick Start state after initialization until STPCLK# deasserted.
4.4.1.5
HALT/Grant Snoop State1234
processor responds snoop transactions while Auto Halt, Stop Grant, Quick Start state. When snoop transaction presented system bus, processor enters HALT/Grant Snoop state. processor remains this state until snoop been serviced quiet. After snoop been serviced, processor returns previous state. HALT/Grant Snoop state entered from Quick Start state, then input signal restrictions Quick Start state still apply HALT/Grant Snoop state (except those signal transitions that required perform snoop).
4.4.1.6
Sleep State
Low-Power Module does support Sleep state. desktop systems, Sleep state very low-power state which processor maintains context phase locked loop (PLL) maintains phase lock. Sleep state only entered from Stop Grant state. After entering Stop Grant state, SLP# signal asserted, causing processor enter Sleep state. SLP# signal recognized Normal state Auto Halt state. processor reset RESET# signal while Sleep state. RESET# driven active while processor Sleep state, then SLP# STPCLK# must immediately driven inactive ensure that processor correctly initializes itself. Input signals (other than RESET#) change while processor transitioning into Sleep state. Input signal changes these times cause unpredictable behavior. Thus, processor incapable snooping latching events Sleep state. While Sleep state processor enter lowest power state, Deep Sleep state. Removing processor's input clock puts processor Deep Sleep state. PICCLK removed Sleep state.
Pentium® Processor Low-Power Module
4.4.1.7
Deep Sleep State
Deep Sleep state lowest power mode that processor enter while maintaining context. processor enters Deep Sleep state stopping BCLK input processor while processor Sleep state Quick Start state. proper operation, BCLK input should stopped state. processor returns Sleep state Quick Start state from Deep Sleep state when BCLK input restarted. lock latency, there 30-µs delay after clocks have started before this state transition happens. PICCLK removed Deep Sleep state. PICCLK should designed turn when BCLK turns while transitioning Deep Sleep state. input signal restrictions Deep Sleep state same Sleep state, except that RESET# assertion results unpredictable behavior.
Pentium® Processor Low-Power Module
Electrical Specifications
following section provides electrical requirements Pentium Processor Low-Power Module.
Requirements
Table provides power supply design criteria.
Table Requirements
Symbol V_DC Signal Parameters IDC_RMS IDC_Surge Input Voltage Input Current Ripple Current Maximum Surge Current V_DC 4.75 5.25 20.0 Parameter Unit Notes
Signal Parameters I5_Surge Power Managed 5.0-V Supply Power Managed 5.0-V Current, Operating Maximum Surge Current 4.75 20.0 50.0 5.25 100.0
Signal Parameters I3_Surge Power Managed 3.3-V Supply Power Managed 3.3-V Current Maximum Surge Current 3.135 3.465
V_CPUPU Signal Parameters VCPUPU ICPUPU Processor Ring Voltage Processor Ring Current 1.375 10.0 1.625 20.0
V_CLK Signal Parameters VCLK ICLK Processor Clock Rail Voltage Processor Clock Rail Current 2.375 24.0 35.0 2.625 80.0
NOTES: 20-µS duration. These values system dependent.
Pentium® Processor Low-Power Module
Requirements
Table shows BCLK requirements.
Table Specifications Processor Core Pins
Parameter2,3 System Frequency BCLK Period BCLK Period Stability BCLK High Time BCLK Time BCLK Rise Time BCLK Fall Time 2.85 2.55 0.175 0.175 0.875 0.875 ±250 Unit Note Note Notes Note Note Note Note Note
NOTES: Figure page illustrates these intervals. timings GTL+ signals referenced BCLK rising edge 1.25 processor core pin. GTL+ signal timings (address bus, data bus, etc.) referenced 1.00 processor core pins. timings CMOS signals referenced BCLK rising edge 1.25 processor core pin. CMOS signal timings (compatibility signals, etc.) referenced 1.25 processor core pins. internal core clock frequency derived from clock. clock core clock ratio determined during initialization predetermined Low-Power Module. BCLK period allows +0.5-ns tolerance clock driver variation. Measured rising edge adjacent BCLKs 1.25 jitter present must accounted component BCLK skew between devices. clock driver's closed loop jitter bandwidth must allow PLL-based device track jitter created clock driver. attenuation point, measured into 10-pF 2-pF load, should less than kHz. This specification ensured design characterization and/or measured with spectrum analyzer. CK97 Clock Synthesizer Design Guidelines further details. 100% tested. Specified design characterization clock driver requirement.
Table describes signal quality specifications processor core clock (BCLK) signal. Figure describes signal quality waveforms clock processor core pins.
Pentium® Processor Low-Power Module
Table BCLK Signal Quality Specifications Processor Core
VIL_BCLK VIH_BCLK Absolute Voltage Range Rising Edge Ringback Falling Edge Ringback BCLK rising/falling slew rate -0.7 Parameter V/ns Unit Note Note Undershoot, Overshoot, Note Absolute Value, Note Absolute Value, Note Note Notes
NOTES: rising edge BCLK, there must minimum overshoot clock must rise monotonically between IL_BCLK fall monotonically between IH_BCLK VIL_BCLK. BCLK must rise/fall monotonically between VIL_BCLK VIH_BCLK. specifications this table apply only when BCLK running. BCLK above IH_BCLK,max below VIL_BCLK,MIN more than clock cycle. rising falling edge ringback voltage specified minimum (rising) maximum (falling) absolute voltage that BCLK signal back after passing VIH_BCLK (rising) IL_BCLK (falling) voltage limits.
Figure BCLK Waveform Processor Core Pins
A7743-01
Pentium® Processor Low-Power Module
Processor Core Voltage Regulation
voltage regulator (DC/DC converter) designed support core voltage ring voltage current future Intel mobile processors. voltage regulator provides appropriate mobile Pentium processor core voltage, GTL+ termination voltage, processor sideband signal pull-up voltage, clock driver buffer voltage. these voltages, only processor sideband pullup voltage (V_CPUPU) clock driver buffer voltage (V_CLK) delivered system electronics. Low-Power Module supports input voltage from system battery power supply.
5.3.1
Voltage Regulator Efficiency
There three voltage regulators (VR) Low-Power Module. These voltage regulators generate processor core voltage processor ring voltage. core voltage regulator provides required current from V_DC supply, relative efficiencies shown Table Figure V_CLK voltage regulators plane.
Table V_CORE Power Conversion Efficiency
V_CORE ICORE Efficiency V_DC 82.15% 88.04% 88.55% 88.14% 87.67% 86.59% 85.47% 79.67% 77.87% 75.71% 73.55%
Pentium® Processor Low-Power Module
Figure V_CORE Efficiency Chart
Efficiency 100.00% 95.00% 90.00% 85.00% 80.00% 75.00% 70.00% 65.00% 60.00% Current
5.3.2 Voltage Regulator Control
VR_ON 400-pin connector allows 3.3-V signal control voltage regulator. system manufacturer this signal turn voltage regulator off. VR_ON should controlled function same signal (SUSB#) used control system's switched 5.0-V 3.3-V power planes. PIIX4E defines Suspend Power Management state which power physically removed from processor voltage regulator. this state, SUSB# PIIX4E controls these power planes. Low-Power Module provides VR_PWRGD signal, which indicates that voltage regulator power operating stable voltage level. system manufacturer should this signal system electronics control power inputs gate PWROK PIIX4E South Bridge. Table provides detailed definitions sequences voltage signals. Table Voltage Signal Definitions (Sheet
Signal Source Definitions V_DC required driven system electronics' power supply. V_DC powers Low-Power Module DC-to-DC converter processor core voltages. Low-Power Module cannot inserted removed while V_DC powered supplied system electronics voltage regulator. supplied system electronics 82443BX powers Low-Power Module's linear regulators generating V_CLK V_CPUPU voltage rails. stays during suspend. V_3S supplied system electronics shut during suspend.
V_DC
System Electronics
System Electronics System Electronics System Electronics
V_3S
Pentium® Processor Low-Power Module
Table Voltage Signal Definitions (Sheet
Signal Source System Electronics Definitions VR_ON 3.3-V signal that enables voltage regulator circuit. When driven active high voltage regulator circuit activated. signal driving VR_ON should digital signal with rise/fall time less than equal (VIL, =0.4 =3.0 result VR_ON being asserted, V_CORE output DC-DC regulator Low-Power Module driven core voltage processor. Upon sampling voltage level V_CORE (minus tolerances ripple), VR_PWRGD driven active high. When asserting VR_ON, VR_PWRGD guaranteed stable after VR_PWRGD sampled active within second assertion VR_ON, then system electronics should deassert VR_ON. After V_CORE stabilized, VR_PWRGD asserts logic high. This signal must pulled system electronics. VR_PWRGD should "logically ANDed" with V_3S generate PIIX4E input signal, PWROK. system electronics should monitor VR_PWRGD verify that asserted high prior active high assertion PIIX4E PWROK. V_CPUPU system electronics uses this voltage power PIIX4E-to-processor interface circuitry. V_CLK system electronics uses this voltage power HCLK[1:0] drivers processor clock.
VR_ON
V_CORE
Low-Power Module
VR_PWRGD
Low-Power Module
V_CPUPU V_CLK
Low-Power Module Low-Power Module
following list includes additional specifications clarifications power sequence timing Figure provides illustration.
VR_ON signal only asserted logical high digital signal after
V_DC 4.75
Rise Time Fall Time VR_ON must less than equal VR_ON (max) +0.4 (min) +3.0 VR_PWRGD asserted logic high (3.3 after V_CORE stabilized V_DC
reaches This signal should cannot pulled system electronics.
power-on process, Intel recommends raising higher voltage power plane first
(V_DC), followed lower power planes (V_5, V_3), finally assert VR_ON after above voltage levels rails. power-off process should reverse process; example, VR_ON gets deasserted, followed lower power planes, finally higher power planes.
VR_ON must monotonically rise through fall through points.
sign slope cannot change between rising falling. following values listed Table Table VR_ON In-Rush Current
Instantaneous Maximum Typical 41.0 Operating
VR_ON must provide instantaneous in-rush current Low-Power Module with
VR_ON Valid-Low Time: This specifies long VR_ON must valid before
VR_ON turned again. going from valid then back
Pentium® Processor Low-Power Module
following conditions must prevent damage customer system Low-Power Module: VR_ON must original voltage level requirements turn-on must before assertion VR_ON (i.e., V_DC 4.75 Figure Power Sequence Timing
V_DC
Note
V_3S
G_LO/HI#
Note
VR_ON
Note
VR_PWRGD V_CPUPU
Note
Note
V_CLK
Note
A7759-01
NOTES: PWROK board should active when VR_PWRGD active V_3S good. CPU_RST from board should active minimum after PWROK active PLL_STP# CPU_STP# inactive. Note that PLL_STP# condition RSMRST# SUSB# PIIX4E. This power supplied Power Module. This should first 5.0-V plane power Stays during suspend. G_LO/HI# must high rising edge VR_ON. not, BIOS must assert this signal very early core execution. V_DC 4.75 V_3S When asserting VR_ON, VR_PWRGD guaranteed stable after V_CPUPU V_CLK generated module.
Pentium® Processor Low-Power Module
5.3.3
Power Planes: Bulk Capacitance Requirements
placement sufficient bulk capacitance system electronics board critical operation Pentium Processor Low-Power Module. Intel provided maximum possible bulk capacitance module. However, order achieve proper filtering in-rush current protection, imperative that additional filtering provided system electronics board. Table details bulk capacitance requirements system electronics. Note: Observe voltage rating requirement capacitors each respective voltage rail.
Table Capacitance Requirement Power Plane
Bulk Capacitance Requirements Power Plane V_DC V_3S VCC_AGP V_CPUPU V_CLK Total Capacitance4
Ripple Current 3A~5A
High Frequency Capacitance Requirements 0.01 0.01 0.01 0.01
0.01 8200 8200
NOTES: These capacitances should located near connector. V_CLK filtering should located next system clock synthesizer. order reduce ESR, Intel recommends multiple bulk capacitors rather than single large capacitor. Intel strongly recommends that customers close attention capacitor design considerations. Specifically, "Capacitance Temperature De-rating Curve," "Capacitance Applied Voltage De-rating Curve," "Capacitance Frequency De-rating Curve." Some capacitor dielectrics particularly susceptible these conditions; example ceramic capacitors.
Pentium® Processor Low-Power Module
5.3.3.1
V_DC Decoupling
V_DC tied together, ensure that decoupling guidelines strictly followed avoid noise from V_DC rail coupling rail. Noise could trigger undervoltage lockout circuits module. example circuit shown Figure adheres decoupling guidelines.
Figure V_DC Decoupling Circuit Example
V5_0
200nH
0.1µF 0.1µF 0.1µF
Inductor
220µF
220µF
220µF
A7703-01
Exact component values system dependant. Intel recommends that specific component values determined through full simulation parasitic modeling.
5.3.4
5.3.4.1
Surge Current Guidelines
Power System Protection
recommended Power System Protection consists elements:
power supply that capable delivering Low-Power Module overcurrent protection circuit that provides means limit maximum current available
system
slew-rate control circuit that provides controlled voltage slew rate turn-on providing
protection components sensitive fast voltage rise times
undervoltage lockout circuit that protects against potentially damaging high currents that
encountered when power supply voltage
overvoltage lockout circuit that provides protection from potentially damaging high
power supply voltages
Bulk decoupling capacitors that provide filtering reservoir energy that provide
faster transient response than power supply
Pentium® Processor Low-Power Module
Figure V_DC Power System Protection Block Diagram
5.0-VDC Power Supply Current Limit Circuit Slew Rate Control Bulk Decoupling Capacitors Undervoltage Lockout Processor Module
Overvoltage Lockout
5.3.4.2
5.0-V Power Supply
5.0-V power supply must able deliver Low-Power Module, measured Low-Power Module.
5.3.4.3
Overcurrent Protection
overcurrent protection circuit provides limit current drawn module. Under normal operating conditions, I_DC should expected exceed allow component variations margining issues, reasonable I_DC current limit Figure shows example overcurrent protection circuit.
Figure Overcurrent Protection Circuit Example
Slew DC_A LM404 2N22 N7000 V_DC
rren Protec tion
Power Supp
Pentium® Processor Low-Power Module
following provided example only. Customers should determine their specific requirements calculate component values accordingly.
I_DC(limit)= (Q1)= 0.005 V(R14) I(R20)
When power initially applied circuit, charges through R20. This slowly rising voltage applied base current source, voltage approximately minus base-emitter drop about V(R14) 2N2222A with moderate about 100. Therefore, current through approximately equal current through R14. charging provides small increment delay since does allow pull gate until pulled non-inverting input down slightly. voltage developed across function load. Equation V(R1) I_DC maximum I_DC expected reasonable I_DC current limit current sense resistor, selected (0.005 maximum voltage developed across this resistor would Equation I_DC(limit) Rsense offset voltage applied inverting input comparator, should then selected current then calculated: Equation Ioffset Note: successful design, system designer should also take into consideration input offset comparator. general rule suggests that design offset should least times greater than device offsets. value calculated: Equation 1.8V (The nearest standard value 6.04 reference R20, LM4040-2.5 very wide operating current range from order provide current source base drive, following needed: Equation Ibase selected I(R20), this would adequate reference current source base drive. Since both these currents must satisfied low-power supply margin, V_DC 4.75 assumed.
Pentium® Processor Low-Power Module
Equation (V_DC Vref) I(R20) (4.75 2.50) 22.5 allow component tolerances, might good choice.)
5.3.4.4
Slew-rate Control
slew-rate control regulates rate that power supply voltage applied system:
threshold voltage -1.0 VGS(sat) -2.4 also denoted Vsat t_delay Ctotal Bulk Caps. Module Caps. 119.4
RDS(on) p-channel MOSFET such Siliconix Si4435DY*. When power supply voltage applied increased value that exceeds Lockout value, (4.75 used this example), undervoltage lockout circuit allows pull gate start turn-on sequence. pulls drain toward ground, forcing current flow through does start source current until after t_delay, with t_delay defined following: Equation t_delay (V_DC VG)] Equation [R16 (R16 R2)] V_DC published minimum threshold Si4435DY -1.0V; i.e. must charge before starts turn delay, t_delay, time required charge Assuming negligible voltage drop across when voltage Gate with respect ground, voltage developed across (R2). minimum steadystate bias desired -4.5 this will voltage dropped across R16. V_DC margin, 4.75 Equation V_DC 4.75 4.65 (with respect ground) Equation (V_DC 5.556 (The nearest standard value 5.62 example continues with 5.62 Rearranging Equation solve yields: Equation -t_delay ln(1 (V_DC G))] value calculated. Equation 0.354 close standard value 0.33 yields t_delay µs.) ramp-up time, t_ramp, defined Equation t_ramp ln(1 VSAT/VGS) t_delay VGS(sat) -2.4
Pentium® Processor Low-Power Module
Equation t_ramp 948.8 maximum current during power-up ramp Equation Imax Ctotal (d/dt Ctotal V_DC/t_ramp total Capacitance, Ctotal V_DC bus, 119.4 then equation below. Equation Imax Summary: From values assumed calculated, t_delay t_ramp Imax
5.3.4.5
Undervoltage Lockout: Circuit Description, V_DC_UVlock(out)
circuit Figure shows undervoltage lockout portion V_DC Supply circuit. This circuit protects locks applied voltage module prevent accidental turn-on V_DC supply voltages. voltage applied module could result destructive current levels.
Figure Undervoltage Lockout Circuit Example
V_DC_A V_DC_UVlock=4.75V R17=10K
R25=1M VCEsat= 0.3V Vref=2.5V
V_DC Vref 2.5V
V_DC
LM339
output LM339 comparator open-collector. when applied voltage V_DC less than 4.75 volts. This holds gate low, which does allow slew-rate controller turn-on. 2.5-V reference, Vref, voltage derived from Figure When noninverting input comparator exceeds Vref, comparator trips allows output High-Z state. Gate then pulled starting controlled power-up slew. following model used calculate undervoltage lockout trip point.
Pentium® Processor Low-Power Module
Figure Undervoltage Lockout Model
V_DC
VCEsat
A7744-01
VCEsat saturation voltage comparator output transistor. comparator trip-point voltage calculated with following equation: Equation V_DC_UVlock Vref [Vref (Vref VCEsat) R25] power module held until V_DC exceeds 4.75 Equation rearranged solve R18. Equation Vref [R25 (V_DC_UVlock Vref) (R17 (Vref VCEsat)] value determined plugging these values into Equation standard resistor value.)
5.3.4.6
Overvoltage Lockout: Circuit Description
Low-Power Module operates with maximum input voltage 5.25 This circuit lock input voltage exceeds desired input.
Pentium® Processor Low-Power Module
Figure Overvoltage Lockout Circuit Example
V_DC R4=100K R24=100K R26=1M R27=1K
Gate
Vref 2.5V
V_DC V_DC LM339
LM339 comparator open-collector output pulled when applied voltage V_DC high, thus disabling slew-rate circuit. model below used component calculations. Figure Overvoltage Lockout Model
V_DC
V_DC
Vinv Vnoninv Vref
Assume that desired V_DC overvoltage lockout Using Equation input non-inverting input lockout comparator calculated. lockout trip voltage calculated with following equations:
Pentium® Processor Low-Power Module
Equation noninv Vref [R27 (V_DC_OVlock Vref) R27)] Equation noninv 2.503 Equation Vinv V_DC_OVlock (R23 R24) output lockout comparator becomes active pulls down when inverting input becomes greater than 2.503 input non-inverting input. Equation rearranged solve R23. Equation Vinv (V_DC_OVlock Vinv) lockout comparator trip point defined Vinv Vnoninv 2.503 Equation provides solution R23. Equation 71.576 (The nearest standard value 71.5 V_DC exceeds voltage lockout comparator inverting input will exceed 2.503 This will cause comparator trip, pulling output disabling power skew control circuit which, turn, will disconnect V_DC from Low-Power Module. Figure Recommended Power Supply Protection Circuit System Electronics
V_DC Over Current Protection 5.0VDC 22uF 2.5V LM4040 V_DC LM339 Under Voltage Lockout V_DC V_DC 2.5V V_DC LM339 2N2222A V_DC Slew Rate Control Si4435DY 22uF 22uF 22uF 4.7uF 4.7uF Input Bulk Decoupling Capacitors Low-Power Module
Power Supply
22uF
2N7000
Components Values Assumed Calculated
5.62 100, 100, 6.04 71.5
LM339
0.33
Over Voltage Lockout
Pentium® Processor Low-Power Module
Figure Simulation V_DC Voltage Skew
0.8ms 1.0ms 1.2ms 1.4ms 1.6ms 1.8ms 1.9ms
A7758-01
Active Thermal Feedback
Table identifies address allocated SMBus thermal sensor used Low-Power Module.
Table Thermal Sensor SMBus Address
Function Thermal Sensor Reserved Reserved Fixed Address Bits (6:4) Selectable Address Bits (3:0) 1110 1010 1011
NOTE: thermal sensor used compliant with SMBus addressing.
Pentium® Processor Low-Power Module
Thermal Sensor Configuration Register
configuration register thermal sensor controls operating mode (Auto Conversion Standby) device. Since processor temperature varies dynamically during normal operation, Auto Conversion mode should used exclusively monitor processor temperature. Table shows format configuration register. RUN/STOP low, then thermal sensor enters Auto-Conversion mode. RUN/STOP high, then thermal sensor immediately stops converting enters Standby mode. thermal sensor still performs temperature conversions Standby mode when receives one-shot command. However, result one-shot command during Auto Conversion mode guaranteed. Intel does recommend using one-shot command monitor temperature when processor active; only Auto Conversion mode should used. Contact your Intel representative further information.
Table Thermal Sensor Configuration Register
Name MASK Reset State Function Masks SMBALERT# when high Standby mode control bit. low, then device enters Auto Convert mode. high, then device immediately stops converting enters Standby mode where one-shot command performed. Reserved future
RUN/STOP
Reserved
NOTE: reserved bits should written read "don't care" programming purposes.
Pentium® Processor Low-Power Module
Mechanical Specification
This section provides physical dimensions Pentium Processor Low-Power Module.
Module Dimensions
Figure shows board dimensions connector orientation.
Figure Board Dimensions
Module Mechanical X-Y-Z Dimensions Thermal Attach Points Unless otherwise specified: Tolerances Angles 0.5° 0.15 .XXX 0.075
Units=mm
Pentium® Processor Low-Power Module
6.1.1
Location Connector
Figure shows location 400-pin connector.
Figure Board Dimensions Connector Orientation
Units=mm
Pentium® Processor Low-Power Module
6.1.2
Printed Circuit Board
Figure shows minimum maximum thickness Power Module printed circuit board (PCB). range thickness allows different technologies used with Intel Low-Power Modules.
Figure Power Module Printed Circuit Board Thickness
Min: 0.90 Max: 1.10
Printed Circuit Board
6.1.3
Height Restrictions
Figure shows height restrictions Low-Power Module. keep-out zone also illustrated. Three mating connectors available heights approximately three sizes provide flexibility choosing system electronics components between boards.
Figure Keep-out Zone
Note
Note
NOTES: values nominal unless otherwise specified. These dimensions have changed from previous modules.
KEEP ZONES
Units=mm
Pentium® Processor Low-Power Module
Thermal Transfer Plate
thermal transfer plate (TTP) provides heat dissipation mobile Pentium processor 82443BX. vary previous generations Intel Low-Power Modules. provides thermal attach point, where system manufacturer transfer heat through system using heat pipe, heat spreader plate, other thermal solutions. Attachment dimensions thermal interface block provided Figure Figure system manufacturer should exact dimensions maximum contact area while ensuring that warpage occurs. warpage occurs, thermal resistance module could adversely affected. When attaching mating block TTP, thermal elastomer thermal grease should used interface material. This material reduces thermal resistance. customer thermal interface block should secured with screws using maximum torque Kg*cm Kg*cm (equivalent 0.147 0.197 N*m). thread length 2.00-mm screws should 2.25-mm gaugeable thread (2.25-mm minimum 2.80-mm maximum). thermal resistance between processor core center does exceed watt.
Figure 82443BX Thermal Transfer Plate
Rivets Mounting
Units=mm
Pentium® Processor Low-Power Module
Figure Thermal Transfer Plate
Units=mm
Pentium® Processor Low-Power Module
6.3.1
Physical Support
Mounting Requirements
Three mounting holes available securing Low-Power Module system base system electronics. Figure mounting hole locations. These hole locations board edge clearances remain fixed Intel Low-Power Modules. three mounting holes should used ensure long term mechanical reliability integrity system. board edge clearance includes 0.762-mm (0.030 inches) wide containment ring around perimeter module. This ring each layer module grounded. surface module, metal exposed shielding purposes. hole patterns also have plated surrounding ring metal standoff shielding purposes. Standoffs should used provide support installed module. However, warpage baseboard vary should calculated into final dimensions standoffs used. Figure shows standoff support hole patterns, board edge clearance, dimensions containment ring. components placed board keep-out area.
Figure Standoff Holes, Board Edge Clearance, Containment Ring
Hole detail, places
3.81+/-0.19
2.413
0.050 0.025 hole diameter
4.45 diameter grounded ring
1.27+/- 0.19 board edge ring
0.762 width containment ring
2.54+/-0.19 keep-out area
3.81+/-0.19 board edge hole centerline
6.3.2
Weight
Pentium Processor Low-Power Module weight approximately grams.
Pentium® Processor Low-Power Module
Thermal Specification
Thermal Design Power
Table provides typical thermal design power (TDP) specification. typical typical power dissipation under normal operating conditions nominal V_CORE (CPU power supply) while executing worst case power instruction mix. This includes power dissipated relevant components. During operating environments, processor junction temperature (Tj) must within specified range 100° power handling capability system thermal solution reduced less than recommended typical shown Table with implementation firmware/software control "throttling" that reduces power consumption dissipation. more information, Pentium® Processor Low-Power Module Thermal Design Guide (order number 273300).
Table Thermal Design Power Specification
Symbol Module Parameter Module Thermal Design Power Typical 15.0 Notes Module core 82443BX voltage regulator, Notes
NOTES: processor temperature, must within specified range 100° TDPModule thermal solution design reference point customer thermal solution readiness total module power.
Pentium® Processor Low-Power Module
Labeling Information
Intel Low-Power Modules tracked ways. first product tracking code (PTC). Intel uses label determine assembly level Low-Power Module. Figure shows where found Low-Power Module. contains characters provides following information. Example: EM500L00102ES Definition: Note: Embedded Module Speed identity Low-Power Module Initial release 256-Kbyte cache size Engineering sample
last letters depend design revision. example, used qualification sample, used production sample.
Figure Product Tracking Code
Intel Assembly Identification Intel Serial Number
ISYWW6666
XXXXXX-XXX XXXXXXXXXXXXX
Product Tracking Code Secondary Side Module
second tracking method uses customer-generated software utility. Four strapping resistors located module determine production level. connected terminated properly, module revision levels determined. customer-generated software utility then read these bits with stepping provide complete module manufacturing revision level. more information, contact your Intel representative.
Pentium® Processor Low-Power Module
Environmental Standards
environmental standards defined Table
Table Environmental Standards
Parameter Temperature Cycle Humidity Voltage Condition Non-operating Operating Unbiased Non-operating Shock Unpackaged Packaged Packaged Unpackaged Vibration Packaged Packaged Damage Human Body Model -40° relative humidity Half Sine, msec Trapezoidal, msec Inclined impact ft/s Half Sine, inches simulated free fall 2.2-gRMS random gRMS 11,800 impacts (low frequency) Non-powered test module only non-catastrophic failure. Low-Power Module tested then inserted system functional test. Specification
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