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Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
Order Number: 273296-005
Information this document provided connection with Intel® products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Intel® 440BX AGPset, Intel Celeronprocessor, Intel Pentium® processor contain design defects errors known errata which cause products deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com.
Copyright Intel Corporation, 2000 *Third-party brands names property their respective owners.
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
Contents
Introduction
Notation Terminology Reference Documents Resources Design Features 1.3.1 PGA370-Based Processors 1.3.2 Intel® 440BX AGPset General Considerations.10 1.4.1 Voltage Definitions 1.4.2 General Design Recommendations Transitioning from Intel® Pentium® Processor 440BX AGPset Design 1.5.1 AGTL+ Termination 1.5.2 VREF Inputs 1.5.3 System Clock 1.5.4 CMOS Compatibility with Future Processors 1.5.5 Processor Core Voltage Decoupling 1.5.6 VID[4] 1.5.7 Phase Lock Loop (PLL) Power.12 1.5.7.1 Topology 1.5.7.2 Filter Specification.13 1.5.7.3 Filter Recommendation 1.5.8 Frequency Selection 1.5.9 Definitions 1.5.10 VCOREDET Quadrant Assignment PGA370-Based Processor Signal Quadrants Board Description.20 Routing Guidelines 2.4.1 AGTL+ Description AGTL+ Layout Recommendations 2.5.1 Network Topology Conditions 2.5.2 Recommended Trace Lengths 2.5.2.1 Board Layout Rules 2.5.3 Additional Guidelines.23 Pre-Layout Simulation (Sensitivity Analysis) 2.6.1 Simulation Parameter Values.23 2.6.2 Simulation Methodology 2.6.2.1 Flight Time Simulation 2.6.2.2 Signal Quality Measurement Post-Layout Simulation 2.7.1 Crosstalk Multi-Bit Adjustment Factor Timing Analysis Host Clock Routing Spacing.27 2.9.1 System Clock Layout.28 Other Buses
Layout Routing Guidelines.16
2.10
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
Scalable Performance Board Guidelines
Processor Guidelines 3.1.1 Scalable Performance System Design Guidelines. 3.1.2 System Guidelines 3.1.3 Thermal Guidelines PGA370 Socket Design Guidelines 3.2.1 VCCCORE Power Plane Split 3.2.2 BSEL[1:0] Implementation 3.2.3 CLKREF Circuit Implementation 3.2.4 AGTL+ Reset Implementation. 3.2.4.1 AGTL+ Reset Layout Topology. 3.2.5 CMOS Voltage Conversion Logic. Overview Pull-up Pull-down Resistor Values Processor Checklist 4.3.1 PGA370-Based Processors 4.3.2 Power Definition 4.3.3 Processor Clocks 4.3.4 Processor Signals 4.3.5 Processor Decoupling Capacitors 4.3.5.1 Core Voltage High-Frequency Decoupling. 4.3.5.2 Decoupling. 4.3.5.3 VREF Decoupling. Board Component Keep-Out. Thermals/Cooling Solutions 4.5.1 Thermal Solution Design Considerations Mechanical Design Considerations. Electrical Design Considerations Voltage Regulator Control Silicon Clock Drivers. PGA370 Socket.
Design Checklist
Third-Party Vendor Information
Index
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
Figures
Filter Topology Filter Specification.13 Using Discrete Discrete Major Signal Sections 82443BX (Top View) PGA370-Based Processor Quadrants Example Placement Intel® 440BX AGPset PGA370-Based Processor Designs Example Placement Intel® 440BX AGPset PGA370-Based Processor Design Four-Layer Board Stack-up Example Recommended Topology Test Load Actual System Load.24 Clock Trace Spacing Guidelines Host Clock Topology BCLK Waveform.33 Processor System Valid Delay Timings Waveform.34 Processor System Setup Hold Timings.34 Power-On Reset Configuration Timings.35 BSEL[1:0] Circuit Implementation PGA370 Designs.36 CLKREF Circuit Implementation PGA370 Designs.37 AGTL+ Reset Implementation AGTL+ Reset Layout Topology CMOS Conversion Logic.40 Pull-up Resistor Example Example Capacitor Placement Within PGA370 Socket Board Component Keep-Out.48
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
Tables
Reference Documents Resources Recommended Inductor Filter Recommended Capacitor Filter. Recommended Resistor Filter Recommended Trace Lengths. Parameter Values Interconnect AGTL+ Simulations PGA370-Based Processor Intel® 440BX AGPset System Timing Equations PGA370-Based Processor Intel® 440BX AGPset System Timing Terms Recommended 66/100 System Timing Parameters Host Clock Trace Lengths. Voltage Current Specifications1, PGA370-Based Processors Scalable Performance Board Processor System Guidelines (Clock)1,2,3 Processor Pins Processor System Guidelines (AGTL+ Signal Group)1, Processor Pins Intel® CeleronProcessor PPGA Thermal Design Power Intel® Pentium® Processor PGA370 Socket Thermal Design Power. Resistor Values CLKREF Divider (3.3 Source) AGTL+ Connectivity CMOS Connectivity. Connectivity (optional). Clock Connectivity. Miscellaneous Connectivity. Power Connectivity Connects
Revision History
Revision Date 10/01 5/00 5/00 Updated note page Removed VCCCORE Voltage Sequencing section (3.2.2 -003 version). Renamed document remove references "motherboard" "flexible platform." corrected term "scalable performance board." Clarified "CMOS Compatibility with Future Processors" page Clarified "BSEL[1:0] Implementation" page Updated Figure with component keep-out restrictions. Corrected power dissipation specification 26.7 Added VCCCORE Power Plane Split section VCCCORE Voltage Sequencing section. Clarified core voltage high frequency decoupling recommendations. Updated Figure Figure First publication this document. Description
2/00 11/99
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
Introduction
Intel® Celeronand Intel Pentium® processor families include processors that installed PGA370 socket. This document provides design recommendations considerations developing systems based Celeron processor PPGA package Pentium processor FC-PGA package, together with Intel 440BX AGPset. Likely design considerations included alleviate problems during design debug phases. information contained this document should used conjunction with Intel® 440BX AGPset Design Guide, which covers Intel 440BX AGPset designs with Intel Pentium processor. Refer that document topics covered this design guide. Exceptions Intel® 440BX AGPset Design Guide listed this document.
Notation Terminology
this document, symbol after signal name identifies signal active low; that signal that active state, based name signal, when driven level. example, when FLUSH# low, flush been requested. When high, nonmaskable interrupt occurred. When signal name does imply active state, symbol indicates that signal inverted. example, D[3:0] `HLHL' refers `A', D[3:0]# `LHLH' also refers High logic level, logic level). term "PGA370-based processor(s)" refers Celeron processor PPGA FC-PGA package Pentium processor FC-PGA package.
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
Table
Reference Documents Resources
Reference Documents Resources
Document Name Information Source Order Number 245264 244453 245301 243658 243748 290633 273218 290634 290641 Contact your Intel Field Sales Representative 290639 243502 243331 290562 290548 290635 244410 245025 243867 244001
Pentium® Processor PGA370 Socket 500E 550E datasheet Intel® Pentium® Processor Specification Update Intel® Pentium® Processor Thermal Metrology CPUID 068xh Family Processors Intel® CeleronProcessor datasheet Intel® Intel® CeleronProcessor Specification Update 440BX AGPset: 82443BX Host Bridge/Controller datasheet
82443BX Host Bridge/Controller Electrical Thermal Timing Specification Datasheet Addendum Intel® 440BX AGPset Design Guide Intel® 440BX AGPset Design Guide Update
82443BX Application Notes
Intel® 440BX AGPset: 82443BX Host Bridge/Controller Specification Update Pentium®
Processor Developer's Manual
Pentium® Processor Thermal Design Guidelines 82371AB PCI-TO-ISA/IDE Xcelerator (PIIX4) datasheet 82371AB PCI-TO-ISA/IDE Xcelerator (PIIX4) Timing Specifications Datasheet Addendum Intel® 82371EB (PIIX4E) Specification Update 370-pin Socket (PGA370) Design Guidelines PGA370 Heat Sink Cooling MicroATX Chassis CK97 CLock Synthesizer Design Guidelines Family Processors Hardware Developer's Manual
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
1.3.1
Design Features
PGA370-Based Processors
PGA370-based processors implement dynamic execution microarchitecture execute Intel MMXtechnology instructions enhanced media communication performance. Additionally, Pentium processors feature streaming single instruction, multiple data (SIMD) extensions enhanced floating-point application performance. PGA370-based processors also same multi-transaction system used Intel Pentium processor. PGA370-based processors support multiple low-power states such AutoHALT, Stop-Grant, Sleep, Deep Sleep conserve power during idle times. PGA370-based processors based processor core. Celeron processor provided Plastic Grid Array (PPGA) package Flip-Chip Grid Array (FC-PGA) package, Pentium processor optionally provided FC-PGA package cost systems value embedded computing market segment. PGA370-based processors utilize AGTL+ system used Pentium processor with support limited single processor-based systems. Celeron processor (PPGA) includes integrated 128-Kbyte leveltwo cache with separate 16-Kbyte instruction 16-Kbyte data level-one caches. Pentium processor (FC-PGA) includes integrated 256-Kbyte level-two cache with separate 16-Kbyte instruction 16-Kbyte data level-one caches. level-two cache capable caching Gbyte system memory address space.
1.3.2
Intel® 440BX AGPset
Intel 440BX AGPset two-component chipset that includes 82443BX Host Bridge Controller 82371AB PCI-TO-ISA/IDE Xcelerator (PIIX4). chipset following features:
Support single Celeron Pentium processor configuration 64-bit AGTL+ based host interface 32-bit AGTL+ based host address interface 64-bit main memory interface with optimized support SDRAM 32-bit primary interface (PCI) with integrated arbiter interface (AGP) with data transfer capability configurable secondary
Extensive data buffering between interfaces high throughput concurrent operations Mobile "Deep Green" desktop power management support
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
1.4.1
General Considerations
Voltage Definitions
purposes this document, following nominal voltage definitions used:
VCC3.3 VCCCORE VCC2.5 VCC1.5 VCCCMOS VREF AGPVREF Voltage dependent four setting depending processor 1.32
Note:
VCC1.5 must sourced same voltage regulator.
1.4.2
General Design Recommendations Intel recommends using widely available, programmable Voltage Regulator Module (VRM)
installed header on-board programmable voltage regulator. Please DC-DC Converter Design Guidelines.
Board designs targeted system integrators should designed according boxed
processor electrical, mechanical, thermal specifications provided boxed processor section Intel® CeleronProcessor datasheet Pentium® Processor PGA370 Socket datasheet. most notable items required power header fan/ heatsink physical clearance board.
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
Transitioning from Intel® Pentium® Processor 440BX AGPset Design
following sections detail considerations transitioning from Intel 440BX AGPset SC-242 connector design PGA370 socket design.
1.5.1
AGTL+ Termination
Intel recommends resistors AGTL+ termination board. addition, high frequency decoupling also required system board. Intel recommends more capacitors 0603 package with capacitor every resistor packs (assumes four resistors pack).
1.5.2
VREF Inputs
VREF (2/3 VTT) must supplied processor through each eight VREF inputs. Intel recommends using resistor divider supply generate VREF. Intel also recommends placing four capacitors 0603 package within mils processor's VREF pins.
1.5.3
System Clock
change system trace lengths FC-PGA PPGA packages, chipset processor clocks must tied together minimize pin-to-pin clock skew. Implementation details provided Section 2.5, "AGTL+ Layout Recommendations" page also recommended that capacitor site placed near processor BCLK input allow clock skew minimized through tuning. This done changing value capacitor site compensate actual board trace lengths.
1.5.4
CMOS Compatibility with Future Processors
PGA370-based processor CMOS outputs open drain require pull-up drive external logic. 0.18 micron process technology utilizes V-compatible CMOS signals 0.25 micron process technology utilizes V-compatible CMOS signals. Intel recommends following CMOS design guidelines. Intel defined three pins PGA370-based processors:
VCC2.5: This should connected system's supply. VCC1.5: This should connected system's supply. VCCCMOS: This should used system CMOS pull-up voltage. decoupling
capacitor recommended. VCC1.5 recommended sourced same voltage regulator. VCCCMOS provides CMOS voltage pull-up resistors required system board. source must provided VCC2.5 source must provided VCC1.5 pin. source VCC1.5 must same supplying VTT. processor routes compatible CMOS voltage source (1.5 through package
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
VCCCMOS output pin. Processors based 0.25 micron process technology (such Intel Celeron processor) CMOS buffers. Processors based 0.18 micron process technology (such Pentium processor PGA370 socket) CMOS buffers. These pins have been defined permit maximum current
1.5.5
Processor Core Voltage Decoupling
system board must implement high frequency decoupling processor core voltage. Intel recommends that more capacitors 1206 package (ceramic better material) placed within socket cavity. Placement capacitors should minimize overall inductance between VCC/VSS power pins. Implementation details provided Section 4.3.5.1, "Core Voltage High-Frequency Decoupling" page
1.5.6
VID[4]
Voltage VID[4] available processor. Therefore, according DC-DC Converter Guidelines, VID[4] must connected ground voltage regulator order provide correct VID[3:0] 1.30 2.05 voltage encoding.
1.5.7
Phase Lock Loop (PLL) Power
PGA370-based processors have internal clock generators that analog require quiet power supplies minimize jitter.
1.5.7.1
Topology
general desired topology shown Figure shown parasitic routing local decoupling capacitors. Excluded from external circuitry parasitics associated with each component. Section 1.5.7.3, "PLL Filter Recommendation" page values. Figure Filter Topology
VCCCORE PLL1
PLL2
370-Pin Socket
v004
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
1.5.7.2
Filter Specification
function filter protect from external noise through low-pass attenuation. general, low-pass description forms adequate description filter. low-pass specification, with input VCCCORE output measured across capacitor, follows: gain pass band attenuation pass band (see drop notes that follow Figure attenuation from attenuation from core frequency filter specification graphically shown Figure Figure Filter Specification
0.2dB
-28dB
-34dB
passband
fpeak
fcore
high frequency band
filt
20.log[(Vcc-60mV)/Vcc]
NOTES: Diagram scale. specification frequencies beyond fcore. fpeak, exists, should less than 0.05 MHz.
Other requirements filter are:
filter should support current shielded type inductor required minimize magnetic pickup. voltage drop from PLL1 should which practice implies series
this also means that pass band attenuation (from 0.35
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
1.5.7.3
Filter Recommendation
following tables examples components that meet Intel's recommendations, when configured topology shown Figure Table Recommended Inductor Filter
Part Number MLF2012A4R7KT Murata LQG21N4R7K00T1 Murata LQG21C4R7N00 Value Tolerance Rated 0.56 0.70 0.30
Table
Recommended Capacitor Filter
Part Number Kemet T495D336M016AS TPSD336M020S0200 Value Tolerance 0.225 0.200
Table
Recommended Resistor Filter
Value Tolerance Power
Note Resistor implemented with trace resistance, which discrete needed.
satisfy damping requirements, total series resistance filter (from VCCCORE plate capacitor) must least 0.35 This resistor form discrete component, routing, both. example, selected inductor minimum 0.25 then routing resistance least 0.10 required. careful exceed maximum resistance rule example, using discrete maximum should less than which precludes using some inductors. Other routing requirements:
should close PLL1 PLL2 pins, route. These routes count
towards minimum damping requirement.
PLL2 route should parallel next PLL1 route minimize loop area). should close routing resistance should inserted between VCCCORE discrete should inserted between VCCCORE
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
Figure Using Discrete
VCCCORE Discrete Resistor PLL2 370-Pin Socket <0.1 route PLL1
<0.1 route
v005
Figure Discrete
VCCCORE Trace Resistance PLL2 370-Pin Socket <0.1 route PLL1
<0.1 route
v006
1.5.8
Frequency Selection
PGA370-based processors utilize BSEL[0] pins select from CK100 clock synthesizer. Implementation details provided Section 3.0, "Scalable Performance Board Guidelines" page
1.5.9
Definitions
following pins required correct operation processor. Implementation details provided Section 3.0, "Scalable Performance Board Guidelines" page
CLKREF EDGCTRL RESET2# RTTCTRL SLEWCTRL Requires 1.25 source Requires pull-up VCCCORE Additional reset processor Requires pull-down Requires pull-down
1.5.10
VCOREDET
VCOREDET used Intel 440BX AGPset PGA370 scalable performance board design.
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
Layout Routing Guidelines
This section describes layout routing recommendations ensuring robust design. Follow these guidelines closely possible. deviations from guidelines listed here should simulated ensure that adequate margin maintained design.
Quadrant Assignment
Intel assigned pins 82443BX simplify routing keep board costs down permitting board routed four layers. Figure shows four signal quadrants 82443BX. component placement board should done with this general flow mind. This simplifies routing minimizes number signals that must cross. individual signals within respective groups have also been optimized order routed using only layers. complete list signals ball assignments, Intel® 440BX AGPset: 82443BX Host Bridge/Controller datasheet.
Figure Major Signal Sections 82443BX (Top View)
Quadrant Corner
AGTL+ Quadrant
Quadrant
DRAM Quadrant
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
PGA370-Based Processor Signal Quadrants
Figure indicates signal quadrants PGA370-based processors. These quadrants defined facilitate layout placement illustrate proposed component placement PGA370-based processor both form factor designs.
Figure PGA370-Based Processor Quadrants
CMOS
Side View
VCCCMOS PLL1, PLL2
AGTL+ Signals
Interrupts
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
Form Factor:
placement layout shown Figure recommended PGA370-based
processor Intel 440BX AGPset system design.
example placement shown Figure shows slots, slots, DIMM sockets,
connector.
form factor design, AGP-compliant graphics device reside either
board (device down option) connector option).
trace length limitation between critical connections addressed Section 2.5.2,
"Recommended Trace Lengths" page
Figure reference only. trade-off between number slots, number
DIMM sockets, other board peripherals must evaluated each design. Figure Example Placement Intel® 440BX AGPset PGA370-Based Processor Designs
Ports
PC10
AGP/PCI1 Plug
370-pin Socket
Host Interface Interface Interface 82443BX CKBF
SDRAM Interface
CK100
SDRAM DIMMs PIIX4E
A7175-01
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
Form Factor:
placement layout shown Figure recommended PGA370-based
processor Intel 440BX AGPset system design.
example placement below shows DIMM sockets compliant device down
board. form factor design, compliant graphics device readily integrated board (device down option). trace length limitation between critical connections addressed Section 2.5.2, "Recommended Trace Lengths" page
Figure reference only; trade-off between number DIMM sockets other
board peripherals must evaluated each design. Figure Example Placement Intel® 440BX AGPset PGA370-Based Processor Design
SDRAM DIMMs CK100
SDRAM Interface Interface CKBF 82443BX Interface
Host Interface
370-pin Socket PIIX4
PC10/ISA Riser
A7176-01
Ports
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
Board Description
4-layer stack-up arrangement recommended system board. example 4-layer stack-up shown Figure impedance signal layers should between lower trace impedance reduces signal edge rates, overshoot, undershoot, less crosstalk than higher trace impedance. higher trace impedance increases edge rates slightly decrease signal flight times.
Figure Four-Layer Board Stack-up Example
ohms
Primary Signal Layer (1/2 cu.) mils mils mils
PREPREG CORE PREPREG
Ground Plane cu.) Power Plane Secondary Signal Layer (1/2
ohms
Total board thickness 62.6 mils
Note that bottom routing layers specify However, after board plated, traces will about Check with your vendor exact value ensure that signal simulation accounts this variation. Note: thicker core help reduce board warpage issues. Additional guidelines board stack-up, placement, layout include following.
board impedance should between recommended). FR-4 material should used board fabrication. dielectric process variation fabrication should minimized. ground plane should split ground plane layer. signal must routed short distance power ground plane, then should routed plane, ground plane.
Keep vias decoupling capacitors close capacitor pads possible.
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
Routing Guidelines
This section lists guidelines followed when routing signal traces during board design. order which signals routed first last will vary different designs. Some designers prefer routing clock signals first, while others prefer routing high-speed signals first. Either order used, long guidelines listed here followed. guidelines listed here followed, important that your design simulated, especially AGTL+ signals. Even when guidelines followed, recommended that simulate many signals possible proper signal integrity, flight time, crosstalk.
2.4.1
AGTL+ Description
AGTL+ electrical technology used family processors host architecture. AGTL+ low-output swing, incident wave switching, open-drain with external pull-up resistors that provide both high logic level termination bus. AGTL+ specification contained Intel® Family Processor Developer's Manual.
AGTL+ Layout Recommendations
This section contains layout recommendations AGTL+ signals. layout recommendations derived from pre-layout simulations that Intel performed.
2.5.1
Network Topology Conditions
Figure shows recommended topology 66/100 single processor systems. termination resistor placed system board. recommended value termination resistor (RTT)
Figure Recommended Topology
Intel® 440BX AGPset
PGA370
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
2.5.2
Recommended Trace Lengths
Table summarizes trace length recommendations. recommended lengths derived from parametric sweeps Monte Carlo analysis.
Table
Recommended Trace Lengths
Trace Minimum Length 1.8" 0.5" Maximum Length 4.3" 2.0"
recommended topology AGTL+ single-ended termination topology. resistor near processor acts pull-up bus. this case, recommended that board trace length actual AGTL+ trace width standard mil, with minimum edge-to-edge trace spacing mils. This helps minimize possible crosstalk effects. voltage must held (transient condition). required that held while processor system idle (static condition). This measured PGA370 socket pins bottom side baseboard. Intel recommends running analog simulations using available buffer models together with layout information extracted from your specific design. Simulation will confirm that design adheres guidelines.
2.5.2.1
Board Layout Rules
AGTL+ Signals
AGTL+ signals should routed with lengths between trace from processor
chipset.
AGTL+ signals trace length between processor resistor pack should
within
Traces routed with minimum edge-to-edge spacing, ratio this
spacing dielectric thickness layer should least 2:1.
trace width recommended mils greater than mils. minimum spacing decreased mils escaping FC-PGA/PPGA
areas, length less than 0.25".
Intel recommends breaking signals from connector same layer.
routing tight, break from connector opposite routing layer over ground reference cross over main signal layer near connector.
strongly recommended that AGTL+ signals routed signal layer next
ground layer (referenced ground).
strongly recommended that splits avoided reference plane. Splits disrupt signal
return paths increase overshoot/undershoot significantly increased inductance.
Eliminate parallel traces between layers separated power ground plane. strongly recommended that AGTL+ signals traverse multiple signal layers.
Note: Following above layout rules critical AGTL+ signal integrity, particularly processors based 0.18 micron process technology.
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
2.5.3
Additional Guidelines
General rules minimizing impact crosstalk other practical considerations design high speed AGTL+ bus, provided Intel® 440BX AGPset Design Guide.
2.6.1
Pre-Layout Simulation (Sensitivity Analysis)
Simulation Parameter Values
Parametric Sweeps interconnect parameter values that were used parametric sweeps summarized Table
Table
Parameter Values Interconnect AGTL+ Simulations
Parameter FC-PGA On-die Termination Board Impedance Board Velocity Board Termination Reference Voltage Connector Impedance Connector Velocity Symbol [ns/ft] VREF[V] [ns/ft] 74.75 1.455 0.95 Typical 65.00 55.25 1.545 1.05 Tolerance 10-20%
Note:
simulation purposes, socket connector modeled transmission line. length line propagation speed must selected such that they give total delay slow case fast case.
2.6.2
Simulation Methodology
Analog simulations recommended high-speed system designs. Start simulations prior layout. Pre-layout simulations provide detailed picture working "solution space" that meets flight time signal quality requirements. layout recommendations Section 2.5.2 based pre-layout simulations conducted Intel. basing board layout guidelines solution space, iterations between layout post-layout simulations reduced. Intel recommends running simulations device pads signal quality device pins timing analysis. However, simulation results device pins used later correlate simulation performance against actual system measurements. Pre-layout analysis includes timing analysis Section sensitivity analysis using parametric sweeps. Parametric sweep analysis involves varying system parameters while others, such driver strength, package, held constant. This way,
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
sensitivity proposed topology varying parameters analyzed systematically. sensitivity minimum flight time, maximum flight time, signal quality should analyzed follows:
Minimum flight time typically analyzed using fast buffers, fast package, fast
PGA370 socket, fast interconnects.
Maximum flight time typically analyzed using slow buffers, slow package, slow
PGA370 socket, slow interconnects.
Signal quality typically analyzed using fast buffers, slow package, slow PGA370
socket, fast interconnects. recommended sweep parameter values shown Table should used simulation. values Table replaced your supplier's specific capabilities known. corner values should comprehend full range manufacturing variation. PGA370-based processor models include buffer models, core package socket connector parasitics, package socket connector trace length, impedance, velocity. Intel 440BX AGPset models available include buffers package traces. Termination resistors should controlled within Outputs from each sweep should analyzed determine which regions meet timing signal quality specifications. establish working solution space, find common space across sweeps that result passing timing signal quality. solution space should allow enough design flexibility feasible, cost-effective layout.
2.6.2.1
Flight Time Simulation
Flight time time difference between signal crossing VREF input receiver output driver crossing VREF where drives test load. timings tables topology discussed this guideline assume actual system load PPGA FC-PGA equal test load. test load found Processor System Specifications (GTL+ Signal Group) section Intel® CeleronProcessor datasheet Pentium® Processor PGA370 Socket datasheet. Figure Test Load Actual System Load
Buffer
Driver
RTEST Test Load
Driver
TREF
Buffer
Driver
Actual System Load
Receiver
TFLIGHT SYSTEM
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
Figure shows different configurations testing flight time simulation. flipflop represents logic input driver stage typical AGTL+ buffer. timings specified driver output. TFLIGHT-SYSTEM usually reported simulation tool time from driver starting transition time when receiver's input sees valid data input. Since both timing numbers (TCO TFLIGHT-SYSTEM) will include propagation time from pin, necessary subtract this time (TREF) from reported flight time avoid double counting. TREF defined time that takes driver output reach measurement voltage, VREF, starting from beginning driver transition pad. TREF must generated using same test load TCO. Intel provides this timing value AGTL+ buffer models. this manner, following valid delay equation satisfied: Valid Delay TFLIGHT-SYS TREF TCO-MEASURED TFLIGHT-MEASURED valid delay equation total time from when driver sees valid clock pulse time when receiver sees valid data input.
2.6.2.2
Signal Quality Measurement
addition flight time simulations, waveforms AGTL+ must conform signal quality specifications ensure that system performance limited interconnect noise. signal quality specifications PGA370-based processors found Intel® CeleronProcessor datasheet Pentium® Processor PGA370 Socket datasheet.
Post-Layout Simulation
Following layout, extract traces simulations verify that layout meets timing noise requirements. small amount trace "tuning" required, experience Intel shown that sensitivity analysis significantly reduces amount tuning required. post layout simulations should take into account expected variation interconnect parameters. Intel recommends running simulations device pads signal quality device pins timing analysis. However, simulation results device pins used later correlate simulation performance against actual system measurements. timing simulations, VREF both processor Intel 440BX AGPset components. Flight times measured from processor pins other system components normal flight time method.
2.7.1
Crosstalk Multi-Bit Adjustment Factor
Coupled lines should included post-layout simulations. flight times listed Table apply single simulations only. They include allowance crosstalk. Crosstalk effects accounted separately, part multi-bit timing adjustment factor (Tadj), which defined Table recommended timing budget includes adjustment factor. caution applying Tadj coupled simulations. This adjustment factor encompasses effects other than board coupling, such processor package crosstalk ground return inductances.
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
Timing Analysis
determine available flight time window, perform initial timing analysis. Analysis setup hold conditions will determine minimum maximum flight time bounds system bus. following equations establish system flight time limits.
Table
PGA370-Based Processor Intel® 440BX AGPset System Timing Equations
Driver Receiver 440BX Equation
Tflight, Thold Tco,min Tskew, (CPU leads Tflight, Tcycle Tco,max Tskew, leads CPU) Tjit Tadj Tflight, Thold Tco,min Tskew, leads CPU) Tflight, Tcycle Tco,max Tskew, (CPU leads Tjit Tadj
440BX
terms used equations described Table Table PGA370-Based Processor Intel® 440BX AGPset System Timing Terms
Term Tcycle Tflight,min Tflight,max Tco,max Tco,min Description System cycle time, defined reciprocal frequency. Minimum system flight time. Maximum system flight time. Maximum driver delay from input clock output data. Minimum driver delay from input clock output data. Minimum setup time. Defined time which input data must valid prior input clock. Minimum hold time. Defined time which input data must remain valid after input clock. Clock generator skew. Defined maximum delay variation between output clock signals from system clock generator, maximum delay variation between clock signals system board variation Intel 440BX AGPset loading variation, skew delay PGA370 socket. Clock jitter. Defined maximum edge edge variation given clock signal. Multi-bit timing adjustment factor. This term accounts additional delay that occurs network when multiple data bits switch same cycle. adjustment factor includes such mechanisms package crosstalk, high inductance current return paths, simultaneous switching noise.
Tskew,CLK Tjit Tadj
Component timings PGA370-based processors available Intel® CeleronProcessor datasheet Pentium® Processor PGA370 Socket datasheet, respectively. Recommended values system timings contained Table Skew jitter values clock generator device come from clock driver vendor's datasheet. skew specification based results extensive simulations Intel. Tadj value based Intel's experience with systems that Pentium Pentium processors.
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
Table
Recommended 66/100 System Timing Parameters
Timing Term PGA370-based processors Tskew,CLK (CPU leads [ns] Tskew,CLK leads CPU) [ns] Tjit [ns] Tadj [ns] Value PPGA FC-PGA 0.600 0.250 -0.250 0.100 0.25 0.40
flight time requirements that result from using component timing specifications recommended system timings summarized Table component values should verified against latest specifications before proceeding with analysis.
Host Clock Routing Spacing
PGA370-based processor Intel 440BX AGPset scalable performance board requires clock synthesizer supplying 66/100 system clocks, clocks, APIC clocks, SDRAM clocks, clocks. minimize impact crosstalk, minimum 0.025" spacing should maintained between clock traces other traces. minimum spacing 0.025" also recommended serpentines.
Figure Clock Trace Spacing Guidelines
0.025" 0.025" Clock
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
2.9.1
System Clock Layout
Intel recommends approximately series termination system clocks; this requirement design-specific vary depending system clocks' signal integrity clock skew requirements. pin-to-pin skew clock generator reduced tying clock driver pins together clock chip. connection should maximum distance 0.250" from each driver most 0.100" long. Also, maximum trace length should exceed 9.0". recommended topology trace lengths defined Table Figure followings additional recommended layout rules system clocks:
recommended that system clocks routed signal layer next ground layer
(referenced ground).
strongly recommended that system clocks traverse multiple signal layers. System clock routing over power plane splits should minimized.
items that must considered when determining clock lengths additional delay socket loading differences between 82443BX processor. recommended that total clock skew Tskew, CLK, including Tskew,CLK (CPU leads Tskew,CLK leads CPU) kept values specified Table order avoid affecting timing budget. Tuning capacitors recommended each clock signal. This requires placing 0603 package capacitor sites within 0.5" both socket connector 82443BX ball. Each capacitor site should have placed clock trace itself, avoiding creation stub that affect signal integrity clock line. capacitor site allows system designer flexibility adjusting skew rate each clock (adjusting load), thereby minimizing skew between them. Table Host Clock Trace Lengths
Clock Chip PGA370 socket Clock Chip 440BX Trace Length 0.75" 1.25" 2.00" 8.25" 9.0"
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
Figure Host Clock Topology
0.250"
82443BX tuning capacitor
0.5"
Clock
0.1"
0.250"
0.75" tuning capacitor
0.5"
PGA370based processors 370-Pin Socket Connector
2.10
Other Buses
Buses mentioned previous sections should adhere recommendations forth Intel® 440BX AGPset Design Guide.
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
3.1.1
Scalable Performance Board Guidelines
Processor Guidelines
Scalable Performance System Design Guidelines
processor guidelines scalable system designs provided this section defined processor pins. Table lists guidelines PGA370-based processors. Specifications valid only specifications case temperature, clock frequency, input voltages met. sure read notes associated with each parameter.
Table Voltage Current Specifications1, PGA370-Based Processors (Sheet
Symbol VCCCORE VTT, VCC1.5 VTT, VCC1.5 VREF VCLKREF Baseboard VCCCORE Tolerance, Static Baseboard VCCCORE Tolerance, Transient ICCCORE ICCCMOS ICLKREF IVTT ISGnt ISLP Parameter processor core Static AGTL+ termination voltage Transient AGTL+ termination voltage AGTL+ input reference voltage CLKREF input reference voltage Processor core voltage static tolerance level PGA370 socket pins Processor core voltage transient tolerance level PGA370 socket pins processor core VCCCMOS CLKREF voltage supply current Termination voltage supply current Stop-Grant processor core Sleep processor core 1.455 1.365 1.169 Core Freq 1.65 1.50 1.50 1.25 1.545 1.635 1.331 Unit Notes ±2%, ±6.5%,
-0.080
0.040
-0.130
0.080
16.2
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
Table Voltage Current Specifications1, PGA370-Based Processors (Sheet
Symbol IDSLP dICCCORE/dt dIVTT/dt Parameter Deep Sleep processor core Power supply current slew rate Termination current slew rate Core Freq Unit A/µs A/µs Notes
NOTES: Unless otherwise noted, specifications this table apply processor frequencies. specifications this table apply only PGA370-based processors. VCCCORE ICCCORE supply processor core on-die cache. "typical voltage" specification with "tolerance specifications" provide correct voltage regulation processor. VCC1.5 must held while AGTL+ active. required that VCC1.5 held while processor system static (idle condition). required design target ±3%; transient noise will ±9%. This measured PGA370 socket pins bottom side baseboard. These tolerance requirements, across frequency bandwidth, measured processor socket soldered-side board. VCCCORE must return within static voltage specification within after transient event; DC-DC Converter Design Guidelines further details. VREF should generated from voltage divider resistors matched resistors. Refer Intel® Pentium® Processor Developer's Manual more details VREF. measurements measured typical voltage, under maximum signal loading conditions. Voltage regulators designed with minimum equivalent internal resistance ensure that output voltage, maximum current output, greater than nominal (i.e., typical) voltage level VCCCORE (VCCCORE_TYP). this case, maximum current level regulator, ICCCORE_REG, reduced from specified maximum current ICCCORE _MAX calculated equation: ICCCORE_REG ICCCORE_MAX (VCCCORE_TYP VCCCORE_STATIC_TOLERANCE) VCCCORE_TYP 10.The current specified current required single processor. similar amount current drawn through termination resistors opposite AGTL+ bus, unless single-ended termination used. current specified also AutoHALT state. 12.Maximum values specified design/characterization nominal VCCCORE. 13.These values based simulation averaged over duration change current. these values compute maximum inductance tolerable reaction time voltage regulator. This parameter tested. 14.dICC/dt specifications measured specified PGA370 socket pins. 15.CLKREF must held 1.25 6.5%. This tolerance accounts power supply resistor divider tolerance. recommended that board generate CLKREF reference from either supply. should used risk AGTL+ switching noise coupling this analog reference. 16.Static voltage regulation includes: output initial voltage point adjust, output ripple noise, output load ranges specified tables above. 17.Listed value Pentium processor MHz. Refer datasheet other processor VCCCORE values.
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
3.1.2
System Guidelines
Table Table contain system guidelines defined processor pins. Table contains BCLK guidelines Table contains AGTL+ system guidelines. Processor system specifications AGTL+ signal group processor pins equivalent those MHz. specification documented processor datasheet.
Table Scalable Performance Board Processor System Guidelines (Clock)1,2,3 Processor Pins
Parameter System Frequency BCLK Period BCLK Period Stability BCLK High Time BCLK Time BCLK Rise Time BCLK Fall Time 10.0 ±250 Unit Figure Notes processor core frequencies @>2.0 @<0.5 (0.5 V-2.0 (2.0 V-0.5
NOTES: Unless otherwise noted, specifications this table apply processor frequencies cache sizes. timings AGTL+ signals referenced BCLK rising edge 1.25 processor core pin. AGTL+ signal timings (address bus, data bus, etc.) referenced 1.00 processor core pins. timings CMOS signals referenced BCLK rising edge 1.25 processor core pin. CMOS signal timings (compatibility signals, etc.) referenced 1.25 processor core pins. BCLK period allows +0.5 tolerance clock driver variation. This specification applies processor when operating with system frequency MHz. difficulty accurately measuring clock jitter system, recommended that clock driver used that designed meet period stability specification into test load This should measured rising edges adjacent BCLKs crossing 1.25 processor core pin. jitter present must accounted component BCLK timing skew between devices. clock driver's closed loop jitter bandwidth must allow PLL-based device track jitter created clock driver. attenuation point, measured into load, should less than KHz. This specification ensured design characterization and/or measured with spectrum analyzer.
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
Figure BCLK Waveform
2.0V 0.5V (Rise Time) (Fall Time) (High Time) (Low Time) (BLCK Period)
761a
1.25V
Table Processor System Guidelines (AGTL+ Signal Group) Processor Pins
Parameter System Frequency AGTL+ Output Valid Delay AGTL+ Input Setup Time AGTL+ Input Hold Time T10: RESET# Pulse Width 0.20 1.20 1.00 1.00 3.25 Unit Figure Notes processor core frequencies
NOTES: Unless otherwise noted, specifications this table apply processor frequencies. These specifications tested during manufacturing. timings AGTL+ signals referenced BCLK rising edge 1.25 processor pin. AGTL+ signal timings (compatibility signals, etc.) referenced 1.00 processor pins. This specification applies processor operating with system bus. Valid delay timings these signals specified into with VREF MHz, into with VREF minimum three clocks must guaranteed between active-to-inactive transitions TRDY#. RESET# asserted (active) asynchronously, must deasserted synchronously. Specification minimum 0.40 swing. Specification maximum swing. 10.After VCCCORE BCLK become stable.
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
Figure Processor System Valid Delay Timings Waveform
Signal Valid T11, (Valid Delay) Valid
T14, (Pulse Wdith) 1.0V GTL+ signal group; 1.25V CMOS, APIC JTAG signal groups
Figure Processor System Setup Hold Timings
Signal
Valid
T12, (Setup Time) T13, (Hold Time) 1.0V GTL+ signal group; 1.25V CMOS, APIC JTAG signal groups
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
Figure Power-On Reset Configuration Timings
BCLK
VCC, core, VREF PWRGOOD
Vil, Vih,
RESET#
(PWRGOOD Inactive Pulse Width) (RESET# Pulse Width)
3.1.3
Thermal Guidelines
Table Table provide recommended thermal design power dissipation designing scalable performance system board. maximum minimum case temperatures also specified. thermal solution should designed ensure that case temperature never exceeds these specifications. additional information, refer Intel® Pentium® Processor Thermal Metrology CPUID 068xh Family Processors.
Table Intel® CeleronProcessor PPGA Thermal Design Power
Processor Power 27.0 Minimum TCASE (°C) Maximum TCASE (°C)
NOTE: These values specified nominal VCCCORE processor core.
Table Intel® Pentium® Processor PGA370 Socket Thermal Design Power
Processor Power 26.7 Minimum Tjunction (°C) Maximum Tjunction (°C)
NOTE: These values specified nominal VCCCORE processor core.
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
PGA370 Socket Design Guidelines
This section summarizes PGA370 socket design considerations designs using Intel 440BX AGPset with PGA370-based processors. These scalable performance designs support full range Celeron Pentium processors that utilize PGA370 socket only). Additional design details provided Intel® 440BX AGPset Design Guide.
3.2.1
VCCCORE Power Plane Split
VCCCORE power planes must split scalable board design. This required accommodate different VCCCORE voltages depending 4-bit setting supported PGA370 socket-based processors.
3.2.2
BSEL[1:0] Implementation
PGA370-based processors utilize BSEL[0] pins select 66/100 system frequency setting from CK100 clock synthesizer. BSEL[1] unused, therefore must pulled down with resistor. Figure details BSEL[1:0] circuit design. Note: Celeron processor datasheet states that BSEL0 tolerant pin. Celeron processors with processor system bus, BSEL0 connected on-die; pulling signal effect processor operation.
Figure BSEL[1:0] Circuit Implementation PGA370 Designs
3.3V 3.3V 3.3V
PGA370 Socket
BSEL0 BSEL1
8.2K
8.2K
SEL0
CK100
SEL1 SEL100/66 MAB12#
440BX
A7193-01
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
3.2.3
CLKREF Circuit Implementation
CLKREF input requires 1.25 source. generated from voltage VCC2.5 VCC3.3 sources utilizing tolerance resistors. decoupling capacitor should included this input. Figure Table example CLKREF circuits.
Warning:
source input reference.
Figure CLKREF Circuit Implementation PGA370 Designs
PGA370 Socket
CLKREF
PGA370 Socket
CLKREF
4.7µf
4.7µf
A7169-01
Table Resistor Values CLKREF Divider (3.3 Source)
CLKREF Voltage 1.243 1.243 1.226 1.242
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
3.2.4
AGTL+ Reset Implementation
Scalable performance PGA370 socket designs must route AGTL+ reset signal from Intel 440BX AGPset pins processor well connector. This reset signal connected pins (RESET#) (RESET2#) PGA370 socket. AGTL+ reset signal must always terminated board. Figure
Figure AGTL+ Reset Implementation
PGA370 Socket
RESET# RESET2#
10pf Connector
RESET#
RESET#
82443BX
A7171-01
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
3.2.4.1
AGTL+ Reset Layout Topology
Figure shows routing layout recommendations AGTL+ reset signal. (length goes from stub junction stub from junction back 440BX output must <0.5", preferably 0.25" less. goes from junction junction with stub from junction must less than 0.5" should preferably 0.25" less. This also true stub from junction resistor. includes full length from junction ITP. Figure AGTL+ Reset Layout Topology
Jumper
Daisy Chain
440BX
10pf
PGA370 Socket
A7314-01
Parameter
Minimum 0.5" 1.0" 0.5" 0.5" 0.5"
Maximum 1.5" 3.0" 1.5" 1.5" 1.5"
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
3.2.5
CMOS Voltage Conversion Logic
Scalable PGA370 socket designs must implement voltage conversion logic processor's FERR# THERMTRIP# signals. conversion logic necessary convert CCCMOS signals (for FC-PGA processors) logic. When choosing switch, important ensure that saturation mode when turns Figure
Figure CMOS Conversion Logic
VCCCMOS
VCCCMOS
3.3V
1.5K PGA370 Socket
1.5K
PIIX4E
FERR#/ THERMTRIP#
A7170-01
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
Design Checklist
Overview
following checklist intended used schematic reviews Intel 440BX AGPset desktop designs. will revised information available.
Pull-up Pull-down Resistor Values
Pull-up pull-down values system dependent. appropriate value your system determined from AC/DC analysis pull-up voltage used, current drive capability output driver, input leakage currents devices signal net, pull-up voltage tolerance, pull-up/pull-down resistor tolerance, input high/low voltage specifications, input timing specifications rise time), other factors. addition, appropriate pull-up pull-down values that used signals connecting processor must meet processor signal quality specifications (overshoot/undershoot). Analysis should done determine minimum/ maximum values that used individual signal. Engineering judgment should used determine optimal value. This determination include cost concerns, commonality considerations, manufacturing issues, specifications, overshoot/undershoot, other considerations. simplistic calculation pull-up value
RMAX (VCCPU MIN) ILEAKAGE RMIN (VCCPU MAX)
Since ILEAKAGE normally very small, RMAX meaningful. RMAX also determined maximum allowable rise time. following calculation allows (maximum allowable rise time) (total load capacitance circuit, including input capacitance devices driven, output capacitance driver, line capacitance). This calculation yields largest pull-up resistor allowable meet rise time
RMAX VCCPU
recommended that SPICE equivalent simulation determine proper values.
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
Figure Pull-up Resistor Example
VccPU RMAX ILEAKAGE
VccPU
RMin
v009.vsd
4.3.1
Processor Checklist
PGA370-Based Processors
Table AGTL+ Connectivity (Sheet
A[35:3] ADS# AERR# AP[1:0] BERR# BINIT# BNR# BP[3:2]# BPM[1:0] BPRI# BR[0]# D[63:0]# DBSY# DEFER# DEP[7:0] Connection A[31:3]: Terminate Connect 82443BX A[35:32]: Leave CONNECT Terminate Connect 82443BX Leave CONNECT Leave CONNECT Leave CONNECT Leave CONNECT Terminate Connect 82443BX Leave CONNECT Optional Debug: used, terminate Leave CONNECT Optional Debug: used, terminate Terminate Connect 82443BX Terminate Connect 82443BX BREQ# Optional: connect ground with resistor Terminate Connect 82443BX Terminate Connect 82443BX Terminate Connect 82443BX Leave CONNECT
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
Table AGTL+ Connectivity (Sheet
DRDY# HIT# HITM# LOCK# REQ[4:0]# RESET# RESET2# RS[2:0]# RSP# TRDY# Connection Terminate Connect 82443BX Terminate Connect 82443BX Terminate Connect 82443BX Terminate Connect 82443BX Terminate Connect 82443BX Terminate Connect 82443BX. Section 3.2.4, "AGTL+ Reset Implementation" page Driven same signal RESET#. Section 3.2.4, "AGTL+ Reset Implementation" page Leave CONNECT Terminate Connect 82443BX Leave CONNECT Terminate Connect 82443BX
Table CMOS Connectivity
A20M# FERR# FLUSH# IERR# IGNNE# INIT# LINT[1] LINT[0] INTR PICD[1:0] PREQ# PWRGOOD SLP# SMI# STPCLK# THERMTRIP# Connection Pull-up VCCCMOS with ~280 resistor. Connect PIIX4E. Pull-up VCCCMOS with resistor. Connect PIIX4E voltage conversion logic. Section 3.2.5, "CMOS Voltage Conversion Logic" page Pull-up VCCCMOS with ~280 resistor. Leave CONNECT Optional: Pull-up CCCMOS with ~280 resistor connect error logic Pull-up VCCCMOS with ~280 resistor. Connect PIIX4E. Pull-up CCCMOS with ~280 resistor. Connect PIIX4E. Pull-up CCCMOS with ~280 resistor. Connect PIIX4E. Pull-up VCCCMOS with ~280 resistor. Connect PIIX4E. Pull-up VCCCMOS with ~200-330 resistor. Pull VCCCMOS with ~200-330 resistor. Optional debug; connect ITP. Pull-up VCC2.5 with ~200-330 resistor. Connect power sense logic. Pull-up VCCCMOS with ~280 resistor. Connect PIIX4E. Pull-up VCCCMOS with ~280 resistor. Connect PIIX4E. Pull-up VCCCMOS with ~280 resistor. Connect PIIX4E. CONNECT. Optional: pull-up VCCCMOS with resistor. Connect error logic voltage conversion logic. Section 3.2.5, "CMOS Voltage Conversion Logic" page
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
Table Connectivity (optional)
PRDY# TRST# Connection pull VTT, series resistor connector pull-up VCCCMOS. series resistor connector Connected ITP/processor. pull-up VCCCMOS Connected ITP/processor. ~200-330 pull-up VCCCMOS pull-up VCCCMOS. series resistor connector Connect ITP/processor. pull-down
NOTE: used, connect TCK, TD1, TMS, TRST# valid logic level; leave floating.
Table Clock Connectivity
BCLK PICCLK Connection Connect CK100. Gang with 82443BX HCLK. Tune series resistor signal integrity. Connect CK100. Tune series resistor signal integrity.
Table Miscellaneous Connectivity
BSEL0 BSEL1 CPUPRES# EDGCTRL RTTCTRL SLEWCTRL THERMDN THERMDP VCOREDET VID[3:0] VID[4] Connection Pull-up VCC3.3 with resistor. Connect CK100 SEL100/66# input, Connect 82443BX resistor. Section 3.2.2, "BSEL[1:0] Implementation" page resistor pull down GND. Optionally pull-up external logic. Pull-up VCCCORE with resistor pull down pull down CONNECT used CONNECT used Leave CONNECT pull-up connect VRM. processor. Connect controller GND.
Celeron processor datasheet states that BSEL0 tolerant pin. Celeron processors with processor system bus, BSEL0 bonded out; pulling signal effect processor operation.
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
Table Power Connectivity
Connection Board divider VCC2.5 VCC3.3 create 1.25 reference with decoupling capacitor. Resistor divider must created from tolerance resistors. source voltage this reference!. Section 3.2.3, "CLKREF Circuit Implementation" page pass filter VCCCORE provided board. Typically inductor series with VCCCORE connected PLL1 then through series capacitor PLL2. Section 1.5.7, "Phase Lock Loop (PLL) Power" page inductor capacitor values. Connect supply Connect supply system CMOS pull-up voltage. Provide decoupling Connect output/ VCCCORE Decoupling Guidelines: (min) 1206 package Connect VREF voltage divider made resistors connected VTT. Decoupling Guidelines: (min) 0603 package Connect AH20, AK16, AL13, AL21, AN11, AN15, regulator. Decoupling Guidelines: (min) 0603 package placed within mils AGTL+ termination resistor packs. capacitor every rpacks.
CLKREF
PLL1 PLL2
VCC1.5 VCC2.5 VCCCMOS
VREF[7:0]
Table Connects
Reserved Connection following pins must left CONNECTS: AA33, AA35, AN21, E23, S33, S37, U35, U37. following pins must left CONNECTS: AK30, AM2, F10, G37, L33, N33, N35, N37, Q33, Q35, Q37, W35,
4.3.2
Power Definition
Refer Celeron processor Intel 440BX datasheets, Pentium® Processor PGA370 Socket datasheet this information.
4.3.3
Processor Clocks PICCLK must driven clock even APIC being used. This clock
high 33.3 uniprocessor system.
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
4.3.4
Processor Signals THERMTRIP# must pulled-up VCCCMOS (1.5 used system logic
voltage conversion logic shown Figure signal wire-OR'ed does require external gate. left CONNECT used. voltage conversion logic shown Figure Please reference schematics.
FERR# output must pulled VCCCMOS (1.5 connected PIIX4E PICD[1:0] must have ~200-330 pull-ups VCCCMOS even APIC being
used.
CMOS inputs should pulled VCCCMOS with appropriate resistor value. processor inputs should driven logic. Logic translation
signals accomplished using open-drain drivers pulled-up VCCCMOS.
PWRGOOD input should driven appropriate level from active-high "AND"
"Power Good" signals from CCCORE supplies. output logic used drive PWRGOOD should level processor.
VREF should generated processor. Intel recommends using
resistor divider with generating VREF. VREF locally generated processor S.E.P. package.
must have adequate bulk decoupling based reaction time regulator used
generate VTT. regulator must provide current ramp A/ms while maintaining voltage tolerance defined Intel® CeleronProcessor datasheet Pentium® Processor PGA370 Socket datasheet. addition, must have adequate high-frequency decoupling system board. decoupling guidelines. decoupling based reaction time regulator used generate VCCCORE. regulator must provide current ramp A/µs while maintaining compliance with DC-DC Converter Design Guidelines.
on-board voltage regulator used instead VRM, VCCCORE must have adequate bulk
lines should have pull-up resistors them ONLY they required Voltage
Regulator Module on-board regulator used. pull-up voltage used should regulator input voltage however, used, resistor divider should utilized lower signal CMOS/TTL levels. pull-up required unless signals used other logic requiring CMOS/TTL logic levels. lines processor tolerant.
port must properly terminated even used. TRST# must driven during reset components with TRST# pins. Connecting
pull-down resistor TRST# will accomplish reset port. figures Integration Tools chapter Family Processors Developer's Manual.
single regulator used. simplistic, single-ended termination, calculation
maximum worst case current This takes into consideration that some signals used Intel 440BX AGPset.
Boards planning support boxed processor must provide matched power header
boxed processor fan/heatsink power cable connector. Consult Intel® CeleronProcessor datasheet specifications power cable connector. power header must positioned close PGA370 socket.
CPUPRES# signal ground processor. presence core
determined with this pulled system board. used, connect ground provide additional support processor.
DBRESET (ITP Reset signal) requires pull-up VCC3.3.
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
system board should connect processor's BR0# signal BREQ0# signal
82443BX. This assigns agent processor. Optionally, this signal grounded with resistor.
4.3.5
Processor Decoupling Capacitors 4.3.5.1 Core Voltage High-Frequency Decoupling
0805 package. capacitors should placed within socket cavity mounted directly primary side board. capacitors should arranged minimize overall inductance between VCC/VSS power pins (See Figure 24).
Intel recommends more capacitors 1206 package, more
Figure Example Capacitor Placement Within PGA370 Socket
Contact your regulator vendor bulk decoupling recommendations that meet
DC-DC Converter Guidelines.
Decoupling capacitor traces should short wide possible. regulator provides scalable performance board PGA370 socket guidelines
processor voltage current.
4.3.5.2
Decoupling
capacitor every R-packs. These capacitors shown outer exterior Figure These located board.
Intel recommends more 0603 package placed within mils R-packs,
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
4.3.5.3
VREF Decoupling
mils).
Intel recommends four more 0603 package placed near VREF pins (within
Board Component Keep-Out
Keep-Out area represents space where board component placement restricted combined effect thermal solution components. board component Keep-Out area with component height restrictions shown Figure
Figure Board Component Keep-Out
1.315
1.315
PGA370S PGA370 DESIGN SPEC.
components 122" Max. Height 060" Max. Height 127" Max. Height Pads
022" Max. Height
dimensions minimum unless otherwise specified
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
Thermals/Cooling Solutions
PGA-370 based processors, adequate heat sink ventilation must provided
ensure that TCASE/TJUNCTION specifications met. These specifications found Intel® CeleronProcessor datasheet Pentium® Processor PGA370 Socket datasheet. additional thermal information, refer Intel® Pentium® Processor Thermal Metrology CPUID 068xh Family Processors.
scalable performance board guidelines processor power dissipation TCASE
PPGA processors, 26.7 FC-PGA processors.
Verify that major components, including 82443BX cooled given they
placed.
4.5.1
Thermal Solution Design Considerations
following questions should considered when implementing thermal solution.
Could anything block airflow from processor (I/O cards, etc.)? there anything between processor intake that preheat flowing into
fan/heatsink?
system (other than power supply fan) used, have recirculation paths been
eliminated?
What flow through PSU/system fan? What maximum ambient operation temperature system?
Mechanical Design Considerations
processor: physical space requirements processor must met.
Intel® CeleronProcessor datasheet Pentium® Processor PGA370 Socket datasheet details. addition, physical space requirements your heatsink must met. must met. Intel® CeleronProcessor datasheet Pentium® Processor PGA370 Socket datasheet details.
boxed processor: physical space requirements boxed processor fan/heatsink
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
Electrical Design Considerations
recommended that simulations performed AGTL+ ensure that proper
timings signal integrity met, especially layout recommendations this document followed.
recommended that simulations performed ensure that proper signal integrity
non-AGTL+ (CMOS) signals.
Verify that voltage range tolerance your on-board regulator adequately
cover VCCCORE requirements PGA370-based processors.
maximum current value your on-board regulator support VCCCORE should
meet value specified DC-DC Converter Guidelines. specified DC-DC Converter Guidelines.
voltage tolerance your on-board regulator VCCCORE should meet value Adequate and/or decoupling should provided components. VREF AGPset should decoupled with 0.001 capacitors each voltage
divider. should decoupled ground ensure better solution.
recommended that AC/DC signal integrity analysis performed determine proper
pull-up pull-down values.
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
Third-Party Vendor Information
This section refers listings various third-party vendors provide products support PGA-370-based processors Intel 440BX AGPset. lists vendors used starting point designer. Intel does endorse vendor guarantee availability functionality outside components. Contact manufacturer specific information regarding performance, availability, pricing, compatibility.
Voltage Regulator Control Silicon
Intel's Developer website lists vendors offer DC-DC converter silicon reference designs that meet Celeron Pentium processor voltage current requirements:
Clock Drivers
Intel's Developer website lists vendors offer clock drivers Celeron Pentium processors Intel 440BX AGPset.
PGA370 Socket
PGA370 Socket Guidelines document obtained from:
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
Index
440BX AGPset features 82443BX pins Decoupling Decoupling capacitors Design considerations electrical mechanical Design recommendations-general Discrete Documents-related
guidelines system AGTL+ description connection checklist RESET signal signal integrity signals simulations termination form factor
Electrical design considerations
Flight time simulation
pins Board impedance keep-out area layout rules routing guidelines stack-up topology board description Boxed processors BSEL frequency selection
Host clock routing topology
Impedance board Intel 440BX AGPset features
Keep-out area
Celeron processor design checklist CLKREF Clocks host clock routing host clock topology connections processor clock design guidelines system clock layout CMOS design guidelines CMOS connections CMOS voltage conversion Crosstalk
Layout, board
Mechanical design considerations Multi-bit timing adjustment factor
pins form factor Notation
guidelines PGA370-based processors
Parametric sweeps PGA370-based processors
Intel® 440BX AGPset PGA370 Scalable Performance Board Design Guide
design features pins socket design voltage specs connections Celeron processor 42-45 Pins PGA370 filter recommendation specification topology Power-on timings Pull-up/pull-down resistors
post-layout pre-layout Socket design Stack-up board guidelines system board System board description System guidelines timing diagrams System clock layout
connections Terminology Thermal guidelines Thermal solutions Third-party vendors Timing analysis Topology AGTL+ board Trace lengths
Related documents Routing guidelines board
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