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Pentium® Processor Low-Power Module 66-MHz SDRAM DIMM Routing Guidelines
Order Number: 273230-002
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Pentium® processor Low-Power Module contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. MPEG international standard video compression/decompression promoted ISO. Implementations MPEG CODECs, MPEG enabled platforms require licenses from various entities, including Intel Corporation. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800-548-4725 visiting Intel's website http://www.intel.com.
Copyright Intel Corporation, 1999 *Third-party brands names property their respective owners.
Low-Power Module 66-MHz SDRAM DIMM Routing Guidelines
Contents
Introduction
Terms Related Documents. SDRAM DIMM System Considerations
66-MHz SDRAM DIMM Memory Guidelines
66-MHz SDRAM DIMM Interface Overview 2.1.1 SDRAM Interface Signals.6 66-MHz SDRAM DIMM Layout Guidelines 2.2.1 DIMM Connection SDRAM 2.2.2 Trace Lengths DIMM Design 2.2.2.1 Data MD[63:0], MECC[7:0] 2.2.2.2 Chip Select CSA[3:0]# 2.2.2.3 Clock Enable CKE[3:0]. 2.2.2.4 Command MAB[13:0]x, WEA#, SRASA#, SCASA#
SDRAM Clock Guidelines
Timing Guidelines. Clock Layout Guidelines.
Figures
SDRAM DIMMs. MD[63:0], MECC[7:0] Topology DQMA[7:0] Topology. CSA[3:0]# Topology CKE[3:0] Topology MAB[13:0]x, WEA#, SRASA#, SCASA# Topology SDRAM Clock Timing Specification Clocking Layout Diagram MHz.
Tables
Related Intel Documents SDRAM DIMM SO-DIMM Differences. SDRAM Connectivity. Trace lengths MD[63:0], MECC[7:0] Trace Lengths DQMA[7:0] Trace Lengths CSA[3:0]#. Trace lengths CKE[3:0] Trace Lengths MAB[13:0]x, WEA#, SRASA#, SCASA# Timing Specifications Maximum Minimum SDRAM Clock Skews Trace Lengths SDRAM Clocks DCLK.
Low-Power Module 66-MHz SDRAM DIMM Routing Guidelines
Introduction
purpose this application note define routing guidelines 66-MHz SDRAM DIMM memory systems Pentium Processor Low-Power Module/Intel 440BX AGPset systems. routing guidelines specified pre-layout simulation results only. Post-layout simulations post-silicon signal integrity analysis available correlate with prelayout simulation results. Therefore, when following these guidelines, recommended that developer simulate these signals proper signal integrity, flight time cross talk.
Terms
Pentium® Processor Low-Power Module identical Intel® Pentium Processor Mobile Module Connector (MMC-2). complete description this module located Intel® Pentium® Processor Low-Power Module datasheet (order number 273256). Intel 440BX AGPset refers both 82443BX Host Bridge/Controller 82371EB Xcelerator. complete description this chipset located Intel® 440BX AGPset: 82443BX Host Bridge/Controller datasheet (order number 290633). SDRAM DIMM refers synchronous DRAM dual in-line memory modules.
Related Documents
These documents available download from Intel's World Wide site http://www.intel.com.
Table
Related Intel Documents
Document Title Order Number 273256 243887 290633 273218 290639 Contact your Field Sales Representative
Intel® Pentium® Processor Low-Power Module datasheet Mobile Pentium® Processor Specification Update Intel® 440BX AGPset: 82443BX Host Bridge/Controller datasheet
82443BX Host Bridge/Controller Electrical Thermal Specification datasheet addendum Intel® 440BX AGPset: 82443BX Host Bridge/Controller Specification Update 4-Clock 72-Bit Unbuffered SDRAM DIMM Specification, Rev.
Low-Power Module 66-MHz SDRAM DIMM Routing Guidelines
SDRAM DIMM System Considerations
66-MHz SDRAM DIMM system differs from 66-MHz SO-DIMM system; there fundamental differences that must understood when designing system support 66-MHz SDRAM DIMM operation. Refer Table list these differences.
Table
SDRAM DIMM SO-DIMM Differences
66-MHz SDRAM DIMM Routing Length Clocking Board Impedance Clocks 66-MHz SO-DIMM 3.94 Clock
Depending signal traces, routing lengths vary. Refer 4-Clock 72-Bit Unbuffered SDRAM DIMM Specification more information.
66-MHz SDRAM DIMM Memory Guidelines
This section lists guidelines followed when routing signal traces board design. order which signals routed first last will vary from designer designer. Some designers prefer routing clock signals first, while others prefer routing high speed signals first. Either order used, long guidelines listed here followed. Even when these guidelines followed, still highly recommended that developer simulate these signals proper signal integrity, flight time cross talk.
66-MHz SDRAM DIMM Interface Overview
82443BX Host Bridge/Controller integrates main memory DRAM controller that supports 72-bit SDRAM array 66-MHz environments. DRAM controller interface fully configurable through control registers. complete description these registers provided Intel® 440BX AGPset: 82443BX Host Bridge/Controller datasheet (order number 290633).
2.1.1
SDRAM Interface Signals
following section explains connectivity between Low-Power Module 66-MHz SDRAM DIMMs. list signal names that used 66-MHz SDRAM DIMM interface provided Table Note: MAB[13,10] inverted. These address bits used define various SDRAM commands.
Low-Power Module 66-MHz SDRAM DIMM Routing Guidelines
Table
66-MHz SDRAM DIMM Layout Guidelines
SDRAM Connectivity
82443BX Pins/Connection CKBF buffer outputs DCLK[x:y] CKE[3:0] CSA#[3:0] MAB10, MAB#[9:0] MAB#11 MAB#12 MAB13 MD[63:0] MECC[7:0] Strap SMBus Individual Address SMBDATA SMBCLK SCASA# SRASA# WEA# DIMM Pins CK[3:0] DCLKs DIMM) CKE[1:0] S#[1:0] DIMM) S#[3:2] DIMM) A[10:0] BA1, DQ[63:0] CB[7:0] SA[2:0] CAS# RAS# WE0# Clock Clock Enable Chip Select Address Address Address Address Address Data Error Checking Correction SMBus Address SMBus Data SMBus Clock SDRAM Column Address Select SDRAM Address Select Write Enable Function
NOTES: Some ranges above dependent which DIMM being reviewed; indicate signal copies. memory data traces byte-swapped simplify board routing minimize trace lengths. This should also done data bits within byte channel. Board impedance should 10%. resistors should maximum tolerance. Populate furthest DIMM first avoid stub reflections. SDRAM Serial Presence Detect Data Structure Specification information EEPROM register contents
Low-Power Module 66-MHz SDRAM DIMM Routing Guidelines
2.2.1
DIMM Connection SDRAM
Figure shows DIMM connections system electronics. guidelines described this document based assumption that 2-DIMM slots present system electronics.
Figure SDRAM DIMMs
CSA[3:2]# CSA[1:0]#
SRASA# SCASA#
DQMA[7:0]
Low-Power Module
WEA#
MAB[12:11, 9:0]#, MAB[13, MD[63:0] MECC[7:0] CKE[1:0] CKE[3:2]
DIMM0
DIMM1
Low-Power Module 66-MHz SDRAM DIMM Routing Guidelines
2.2.2
Trace Lengths DIMM Design
following section illustrates signal topology provides minimum maximum trace lengths DIMM connector pads each signal group 2-DIMM design.
2.2.2.1
Data MD[63:0], MECC[7:0]
Figure MD[63:0], MECC[7:0] Topology
LowPower Module
DIMM1
Table Trace lengths MD[63:0], MECC[7:0]
Section L0+L1+L2 Series Minimum
DIMM0
Maximum
Low-Power Module 66-MHz SDRAM DIMM Routing Guidelines
Figure DQMA[7:0] Topology
LowPower Module
DIMM1
Table Trace Lengths DQMA[7:0]
Section Minimum
DIMM0
Maximum
Low-Power Module 66-MHz SDRAM DIMM Routing Guidelines
2.2.2.2
Chip Select CSA[3:0]#
Figure CSA[3:0]# Topology
LowPower Module
DIMM1
DIMM0
Table
Trace Lengths CSA[3:0]#
Section Minimum Maximum
Low-Power Module 66-MHz SDRAM DIMM Routing Guidelines
2.2.2.3
Clock Enable CKE[3:0]
Figure CKE[3:0] Topology
LowPower Module
DIMM1
DIMM0
Table
Trace lengths CKE[3:0]
Section Minimum Maximum
Low-Power Module 66-MHz SDRAM DIMM Routing Guidelines
2.2.2.4
Command MAB[13:0]x, WEA#, SRASA#, SCASA#
Figure MAB[13:0]x, WEA#, SRASA#, SCASA# Topology
LowPower Module
DIMM1
Table
DIMM0
Trace Lengths MAB[13:0]x, WEA#, SRASA#, SCASA#
Section Minimum Maximum
Low-Power Module 66-MHz SDRAM DIMM Routing Guidelines
SDRAM Clock Guidelines
This section defines clock timing, lengths series termination SDRAM-related clocks.
Timing Guidelines
Figure Table show simplified SDRAM clock layout timing specifications. Note: Even when following SDRAM clock layout guidelines, highly recommended that developer ensure that maximum minimum SDRAM clock skews within timing specifications.
Figure SDRAM Clock Timing Specification
Mobile Pentium® Processor
82443BX
DCLKW DIMM SDRAM Component
Clock Buffer
Table
Timing Specifications Maximum Minimum SDRAM Clock Skews
Symbol Description DCLKWR SDRAM (SCLK) skew Ck100-M Pin-to-Pin (max) -250 (min) Boards (max) -400 (min) Total (max) -650 (min)
Low-Power Module 66-MHz SDRAM DIMM Routing Guidelines
Clock Layout Guidelines
following guidelines required proper clock layout:
Series matching resistors required.
Place near driver possible, less than 1inch.
Route clocks internal layers provide better trace delay consistency
containment.
board impedance 10%. Minimize usage vias clock signals. width spacing ratio clocks 1:2.
Figure Clocking Layout Diagram
LowDCLKWR Power Module
DCLKO
buf_in
DIMM CKBF-M
DIMM
Table Trace Lengths SDRAM Clocks DCLK
Variable Trace Impedance Trace Length Minimum Maximum Resistor

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