Notice: 80960 microprocessors contain design defects errors known erra
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80960Jx Microprocessor
Notice: 80960 microprocessors contain design defects errors known errata which cause product's behavior deviate from published specifications. Current characterized errata documented this specification update. Order Number: 272852-009
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. 80960Jx microprocessors contain design defects errors known errata which cause products deviate from published specifications. Current characterized errata documented this specification update. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 1999 *Third-party brands names property their respective owners.
80960Jx Microprocessor Specification Update
Contents
Revision History Preface. Summary Table Changes. Identification Information. Errata Specification Changes Specification Clarifications Documentation Changes
80960Jx Microprocessor Specification Update
Revision History
Date
Version
Description Added specification change 80960JS/JC/JT Extended Temperature TOV1 (min) Specification Change. Added Documentation Change Revised 80960JA/JF/JD/JS/JC/JT datasheet. Note: June, 1999, 80960JS/JC datasheet information incorporated into 80960JA/JF/JD/JT datasheet create 80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor datasheet, order #273159-003. Added Documentation Change "New 80960JA/JF/JD/JS/JC/JT Datasheet." Added Documentation Change "Updated MPBGA Thermal Data.
10/08/99
06/14/99
Removed previous Documentation Changes. These items referenced prior revisions (002 earlier) 80960JA/JF/JD/JT 80960JS/JC datasheets 80960Jx Microprocessor Developer's Manual. Each documentation change later incorporated into newer revision document referenced. Changed name this document 80960Jx Microprocessor Specification Update (added "Micro") consistency with other 80960Jx document names. Added Specification Changes 80960JT TIH1 Specification Change 80960JS/JC TIH1 Specification Change.
02/12/99
Added Documentation Change Note Reference TOV1 Timing Characteristics Tables Omitted. Incorporated 80960JS/JC stepping information Summary Table Changes. Added Document Changes Orientation Pinout Diagrams 196-Ball MPGBA Changed Timings Diagrams Apply 80960JT Processor. Added 80960JS/JC processor information Stepping Register. Removed references 80960JA/JF 80960JD data sheets (both combined into 80960JA/JF/JD/JT datasheet).
12/15/98
05/27/98
Added Specification Change Specification Changes Revised Document Change Index Update i960® Microprocessor Developer's Manual Revised 80960JD Device Stepping Identifier Added errata #17: Power Supply Sequence Damage Internal Diodes.
04/09/98
Incorporated 80960JT processor into this specification update. Added Document Change Index Update i960® Microprocessor Developer's Manual. Updated "Errata" section reflect stepping. Added Specification Clarification #10: timing specification derating versus capacitive loading. Updated "Document Changes" section reflect user manual.
02/03/98
80960Jx Microprocessor Specification Update
Date
Version Some improved timings
Description
04/09/97
HALT Mode current corrections errata modified, Errata does effect application datasheet correction This Specification Update document. contains identified errata published before this date. Added errata #16: level TRST#/RESET# Greater than Specified Data Sheets. Added errata #15: Actual Greater than Specified Datasheets. Added errata sheet. Added stepping, whose only difference from stepping RDYRCV# errata during Th(hold cycle). technote added list 80960Jx technotes. Added errata section User's Manual Errata containing only application critical users's manual errata.
07/01/96 11/29/95 10/31/95
3/30/95
3/10/95
Added user's manual errata Manual Errata: IPND should Modified using Format Instruction. lines code errata Fault Stack Alignment were changed shown: from: sele r10, r8to: sele r10, from: sele r10, r9to: sele r10,
2/9/95 1/23/95
Added errata #13: Data Breakpoints System Procedure Entries Lost Certain Fault Types. Added errata #12: "balx" Instruction Does Branch When targ Same Register.
80960Jx Microprocessor Specification Update
Preface
Preface
July, 1996, Intel's Computing Enhancement Group consolidated available historical device documentation errata into this document type called Specification Update. have endeavored include documented errata consolidation process, however, make representations warranties concerning completeness Specification Update. This document update specifications contained Affected Documents/Related Documents table below. This document compilation device documentation errata, specification clarifications changes. intended hardware system manufacturers software developers applications, operating systems, tools. Information types defined Nomenclature consolidated into specification update longer published other documents. This document also contain information that previously published.
Affected Documents/Related Documents
Title i960® Microprocessor Developer's Manual 80960JA/JF Embedded 32-Bit Microprocessor datasheet 80L960JA/JF Embedded 32-Bit Microprocessor datasheet 80960JD Embedded 32-Bit Microprocessor datasheet 80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor datasheet 712: DRAM Controller i960® JA/JF/JD Processors AP-716: Architectural Comparison 80960Cx/Jx/Hx AP-727: Interfacing i960® Processor Order 272483 272504 272744 272596 273159 272674 272694 272779
80960Jx Microprocessor Specification Update
Preface
Nomenclature
Errata design defects errors. These cause 80960Jx microprocessor's behavior deviate from published specifications. Hardware software designed used with given stepping must assume that errata documented that stepping present devices. Specification Changes modifications current published specifications. These changes will incorporated release specification. Specification Clarifications describe specification greater detail further highlight specification's impact complex design situation. These clarifications will incorporated release specification. Documentation Changes include typos, errors, omissions from current published specifications. These will incorporated release specification. Note: Errata specification changes remain specification update throughout product's lifecycle, until particular stepping longer commercially available. Under these circumstances, errata specification changes removed from specification update archived available upon request. Specification clarifications documentation changes removed from specification update when appropriate changes made appropriate product specification user documentation (datasheets, manuals, etc.).
80960Jx Microprocessor Specification Update
Summary Table Changes
Summary Table Changes
following table indicates errata, specification changes, specification clarifications, documentation changes which apply 80960Jx microprocessor product. Intel some errata future stepping component, account other outstanding issues through documentation specification changes noted. This table uses following notations:
Codes Used Summary Table
Stepping
mark) (Blank box): This erratum fixed listed stepping specification change does apply listed stepping. Errata exists stepping indicated. Specification Change Clarification that applies this stepping.
Page
(Page): Page location item this document.
Status
Doc: Fix: Fixed: NoFix: Eval: Document change update will implemented. This erratum intended fixed future step component. This erratum been previously fixed. There plans this erratum. Plans this erratum under evaluation.
Change left table indicates this erratum either modified from previous version document.
80960Jx Microprocessor Specification Update
Summary Table Changes
Errata
Steppings JA/JF/JD Steppings JS/JC/JT Fixed Fixed Fixed Fixed Fixed Fixed Fixed Fixed Fixed Fixed Fixed Fixed Fixed Fixed Fixed Fixed NoFix RDYRCV# Restriction During Cycles (A-0 Stepping Only) RDYRCV# Restriction During Cycles (A-2 Stepping Only) System-Local Fault Calls System-Supervisor Trace Enable Instructions "inten" "intdis" Fully Implemented Fault Stack Alignment Software Interrupt Erratum Pullup LOCK#/ONCE# Does Turn Software Reinitialization Values LMMR0, LMMR1, DLMCON Power Supply Current (ICC) Higher than Anticipated Cycle Performance Instruction Order with LOAD Instructions "divi" Instruction Performance When src2 Instructions Executed Between Back-to-Back Interrupts "balx" Instruction Does Branch When targ Same Register Data Breakpoints System Procedure Entries Lost Certain Fault Types Actual Greater than Specified Data Sheets level TRST#/RESET# Greater than Specified Data Sheets Power Supply Sequence Damage Internal Diodes Page Status ERRATA
80960Jx Microprocessor Specification Update
Summary Table Changes
Specification Changes
Steppings JA/JF/JD
Steppings JS/JC/JT
Page
Status
Specification Changes
Specifications Changes Specification Changes 80960JT TIH1 Specification Change 80960JS/JC TIH1 Specification Change 80960JS/JC/JT Extended Temperature TOV1 (min) Specification Change
Applies JA/JF only.
Specification Clarifications
Steppings JA/JF/JD Steppings JS/JC/JT None this revision specification update. Page Status Specification Clarifications
Documentation Changes
Document Revision 273159-002 273159-003 273200-002 273159-002 273200-002 273159-004 Page Status Documentation Changes 80960JA/JF/JD/JS/JC/JT Datasheet
Updated MPBGA Thermal Data Revised 80960JA/JF/JD/JS/JC/JT datasheet
80960Jx Microprocessor Specification Update
Identification Information
Identification Information
Markings
80960Jx microprocessors identified electrically according device type stepping.
Stepping Register
following table lists devices which this errata sheet applies:
Device Stepping 80960JA 80960JA 80960JF 80960JF 80960JD 80960JD 80960JT 80960JC 80960JS Identifier 0x08821013 0x30821013 0x08820013 0x30820013 0x08820013 0x30830013 0x0082B013 0x30833013 0x30823013
80960Jx Microprocessor Specification Update
Errata
Errata
Problem:
RDYRCV# Restriction During Cycles (A-0 Stepping Only)
RDYRCV# indicates that data address-data (AD) lines sampled removed. RDYRCV# asserted during cycle, then cycle extended next cycle inserting wait state (Tw). Normally processor ignores this during address state (Ta). this stepping, however, processor recognize assertion RDYRCV# during address state access prematurely terminate access. example, quad-word load (with RDYRCV# asserted during processor will erroneously take first word data during address cycle, will then read only three more words data. This will cause last word data lost, first three will corrupted. processor also incorrectly responds RDYRCV# assertion during idle (Ti) (Th) states. Under these conditions, processor will deassert HOLDA asserted), clock after RDYRCV# assertion. Hold acknowledge never asserted reasserted) until clock after RDYRCV# sampled high.
Implication: Workaround:
RDYRCV# generation logic must designed only assert RDYRCV# during either states, should used multi-master system other masters. Make sure that system implementation does allow RDYRCV# assertion during state except valid data (Td) recovery (Tr) states. Typical synchronous state logic 80960Jx described "normally-not-ready" (i.e., only asserted when system ready). Normally-not-ready logic will usually satisfy requirement without modification. Strict "normally-ready" state logic cannot used 80960Jx systems because logical sense RDYRCV# changes during recovery state. Driving RDYRCV# indefinitely during would, definition, cause processor hang states indefinitely. ready logic resembles normally-ready system, then change normally-not-ready. 80960Jx sole master, then multiple open-drain ready signals wire-OR'ed with pull-up resistor drive RDYRCV#. sure satisfy processor's setup hold timing requirements every clock. 80960Jx part multi-master system, then share RDYRCV# signal with other masters. Providing separate ready signals will prevent 80960Jx from spuriously deasserting HOLDA.
Status:
Fixed. Refer Summary Table Changes determine affected stepping(s).
Problem:
RDYRCV# Restriction During Cycles (A-2 Stepping Only)
RDYRCV# signal indicates that data lines sampled removed. RDYRCV# asserted during cycle, then cycle extended next cycle inserting wait state (Tw). Normally processor ignores this during address state (Ta). this stepping, however, processor recognize assertion RDYRCV# during address state access prematurely terminate access. example, quad-word load (with RDYRCV# asserted during processor erroneously takes first word data during address cycle, then reads only three more words data. This causes last word data lost, first three corrupted.
80960Jx Microprocessor Specification Update
Errata
processor also incorrectly responds RDYRCV# assertion during idle (Ti) state.
Implication:
RDYRCV# generation logic must designed only assert RDYRCV# during either states. Typical synchronous state logic 80960Jx described "normally-not-ready" (i.e., only asserted when system ready). Normally-not-ready logic will usually satisfy requirement without modification.
Workaround:
Make sure that system implementation does allow RDYRCV# asserted during state except valid data (Td) recovery (Tr) states. Typical synchronous state logic 80960Jx described "normally-not-ready" (i.e., only asserted when system ready). Normally-not-ready logic will usually satisfy requirement without modification. Strict "normally-ready" state logic cannot used 80960Jx systems because logical sense RDYRCV# changes during recovery state. Driving RDYRCV# indefinitely during would, definition, cause processor hang states indefinitely. ready logic resembles normally-ready system, then change normally-not-ready. 80960Jx sole master, then multiple open-drain ready signals wire-OR'ed with pull-up resistor drive RDYRCV#. sure satisfy processor's setup hold timing requirements every clock.
Status:
Fixed. Refer Summary Table Changes determine affected stepping(s).
Problem:
System-Local Fault Calls System-Supervisor Trace Enable
When fault handler implemented through system-local fault call, fault handler found system procedure table. other characteristics call those local call: PC.te (trace enable Process Controls), PC.em (execution mode flag Process Controls) remain unchanged there stack switch. system-local fault call 80960Jx previously mentioned characteristics, except that PC.te copied from SSP.te (trace control Supervisor Stack Pointer). This erratum could cause tracing toggled when entering system-local fault call. addition when processor user mode while executing fault handler, PC.te will restored upon return from fault handler. Little none. system-supervisor calls local-call handler instead system-local fault handler. system-local fault handlers. local fault handler required, then local-call handler place handler pointer directly fault table. other option only system-supervisor calls from system procedure table. system-local fault handlers must used, then designer should make sure that PC.te user mode same SSP.te System Procedure Table. Fixed. Refer Summary Table Changes determine affected stepping(s).
Implication: Workaround:
Status:
Problem: Implication: Workaround: Status:
Instructions "inten" "intdis" Fully Implemented
instructions used interrupt control, inten intdis, 80960Jx were fully implemented. Must intctl instruction instead either inten intdis; however, intctl takes more cycles execute. inten intdis globally enabling disabling interrupts. Instead, interrupt control instruction intctl which both enable disable interrupts. Fixed. Refer Summary Table Changes determine affected stepping(s).
80960Jx Microprocessor Specification Update
Errata
Problem:
Fault Stack Alignment
some situations, when fault occurs, unaligned (not quad-word aligned) fault record written stack; result, incorrectly restores arithmetic controls (AC) register process controls (PC) register. Furthermore, while within fault handler, incorrectly points beginning fault record. This case happens when: local fault handler selected fault current execution mode Supervisor when fault occurs; current stack offset from quad-word boundary bytes: Where positive integer. other possible values generate erratum: Code Sequences Affected Assuming described above, erratum manifests itself time fault taken does result stack switch (all cases except system supervisor fault taken from user mode). This forces fault record become misaligned with respect stack pointer (SP) become non-quad-word aligned. fault type fault fields fault record then stored address FP+4 respectively. user cannot retrieve information from fault record location expected memory. Upon return from fault handler cleared. also cleared upon return fault handler executing supervisor mode. through
Implication: Workaround:
Requires extra code every fault handler extra time implement workaround. workaround requires special code beginning each fault handler that corrects unaligned fault record makes accessing fault record returning from fault handler operate correctly. There limitation workaround (discussed further detail below). workaround code guaranteed work versions 80960Jx present future. workaround consists assembly code that rewrites entire fault record aligned location when situation detected. This code should placed beginning fault handlers. RESTRICTION: application composed only code compiled Intel CTools compiler, then this anomaly cannot occur. application compiled another compiler contains customer routines coded directly 80960 assembly code, then possible improper fault record generated when fault occurs. code generated latter method, code restriction should followed ensure that improper fault record generated: always quadword aligned (i.e., always incremented decremented multiples 16), then proposed workaround needed.
80960Jx Microprocessor Specification Update
Errata
Start Place beginning fault handlers. Uses through not0xf, cmpobesp, 1f## needed equal
Problem detected: Unaligned Fault Record 24(sp),sp## stack quadword aligned 32(fp),fp## frame pointer -72(fp), r3## base fault record r5## 0xFFFF FFFF Wrong type value 40(r3), r10## r10= fault type (from fault record) r11= fault (from fault record) subo r12## r12= original value Were fault type fault clobbered frame spill? cmpo r11, r12## first fault interrupt occurred?
sele r10, r4## fault type* 0xFFFF FFFF sele r11, r5## fault 0xFFFF FFFF from original fault record information from existing fault record -24(r3),r8## Fault type, Fault Address, saved fault (resumption record) 24(r3),r12## Fault Data, Otype, saved Write fault record 64(r3)## Store Fault Type Fault (r3)## Write Fault Address Fault Type r10, 8(r3)## Write Record r12, 48(r3)## Write Fault Data Otype r14, 56(r3)## Write Saved Start actual fault handler code.
Limitations Workaround
80960Jx Microprocessor Specification Update
Errata
workaround will work following conditions occur:
interrupt occurs fault handler. local register frame fault handler spilled interrupt.
When this limitation occurs fault record incomplete, value 0xFFFF FFFF written fault type fault fields fault record (created workaround code listed above).
Status:
Fixed. Refer Summary Table Changes determine affected stepping(s).
Problem:
Software Interrupt Erratum
When processor executing supervisor mode process priority fault interrupt that comes from user mode lower process priority, software interrupt posted priority where Then fault interrupt return user mode executed. When restored return user mode process priority reset where U<S. result, before first instruction user mode execute, control transferred software interrupt handling mechanism interrupt posted priority error occurs when software interrupt handling mechanism updates interrupt table Software-Interrupt Priority Register before switching Supervisor mode. Because processor wrong mode, type.mismatch fault will occur control will transferred fault handling mechanism before first instruction software interrupt handler issued. Upon return from fault handler, execution interrupt handler will continue; however, subsequent software interrupts lost.
Implication: Workaround: Status:
Overhead needed make sure software interrupts occur user mode, loss software interrupt capabilities will result. only workarounds this erratum either allowing software interrupts while processor user mode avoiding software interrupts altogether. Fixed. Refer Summary Table Changes determine affected stepping(s).
Problem:
Pullup LOCK#/ONCE# Does Turn
LOCK#/ONCE# signals provided with weak pullup device intended keep processor from accidentally entering ONCE mode reset. pullup device supposed turn after deassertion RESET#. However, pullup remains even ONCE high impedance mode. strength pullup device measured which means looks approximately like resistor attached VCC.
Implication: Workaround:
Ensure driver strengths will overdrive pullup transistor. workaround necessary; erratum mostly affects factory test procedures. LOCK# pulldown transistor reasonable driver attached during ONCE mode have ample strengths overdrive pullup transistor. Fixed. Refer Summary Table Changes determine affected stepping(s).
Status:
80960Jx Microprocessor Specification Update
Errata
Problem:
Software Reinitialization Values LMMR0, LMMR1, DLMCON
After software reinitialization, LMMR0.lmte, LMMR1.lmte, DLMCON.dcen should zero (refer i960® Microprocessor User's Manual, Table 11-2). current implementation, both processor user's manual, these bits retain their values prior software reinitialization. Software should take into account fact that these values change future stepping 80960Jx should able handle both current future values these registers. None. Fixed. Refer Summary Table Changes determine affected stepping(s).
Implication: Workaround: Status:
Problem: Implication: Workaround: Status:
Power Supply Current (ICC) Higher than Anticipated
values measured early silicon samples approximately higher than targeted values data sheet. User must account higher current required from power supply. Intel will publish corrected when device fully characterized. Fixed. Refer Summary Table Changes determine affected stepping(s).
Problem:
Cycle Performance Instruction Order with LOAD Instructions
Under certain conditions, LOAD instruction immediately followed instruction could cause extra cycle added execution time. This internal processor availability non-predictable. Instructions need re-ordered avoid performance loss. critical code sequences that contain LOAD's followed instruction, experiment with order instructions that follow LOAD instruction. This eliminate extra cycle. There workaround this problem. Fixed. Refer Summary Table Changes determine affected stepping(s).
Implication: Workaround:
Status:
Problem: Implication: Workaround:
"divi" Instruction Performance When src2
Execution divi instruction takes approximately extra cycles when register used src2 operand equal operand register. less register available performance avoided. avoid cycle performance divi, same register src2 dst. application composed only code compiled Intel CTools compiler version above, then this situation will occur. Fixed. Refer Summary Table Changes determine affected stepping(s).
Status:
Problem:
Instructions Executed Between Back-to-Back Interrupts
processor insert instructions from interrupted process code between back-to-back interrupts under certain conditions. This situation could cause slightly longer interrupt latency depending instruction(s) executed. This situation occurs when processor executing interrupt handler, interrupt(s) pending priority which lower than current interrupt handler priority higher than interrupted process priority. Upon return from current interrupt handler, processor retains interrupt handler process priority cycles. This prevents lower priority interrupts from
80960Jx Microprocessor Specification Update
Errata
being serviced immediately allows interrupted process code executed until priority lowered. Extra cycles will added interrupt latency pending interrupts based instructions executed during process priority interim.
Implication: Workaround: Status:
Increased interrupt latency result. There workaround this latency problem. Fixed. Refer Summary Table Changes determine affected stepping(s).
Problem:
"balx" Instruction Does Branch When targ Same Register
When targ operands balx same register, balx does branch. Typically, targ register holds address branch specified user, register automatically loaded processor with address return When same register used targ, targ register, after being used calculate target address, receives processor-loaded address return Architecturally, using same registers targ permissible works other 80960 family members, 80960Jx this causes balx become non-functional. following example, balx should compute target address "xyz", load "abc" into r12, branch "xyz". However, "abc" gets loaded into processor branches "abc".
xyz, balx(r12), abc:addo xyz:
Implication: Workaround:
This erratum reduces number registers available other use. Avoid using same register targ registers balx instruction. application composed only code compiled Intel CTools compiler, then this situation will occur. Fixed. Refer Summary Table Changes determine affected stepping(s).
Status:
Problem:
Data Breakpoints System Procedure Entries Lost Certain Fault Types
This erratum occurs when tracing enabled (PC.te system supervisor fault call serviced from supervisor mode system local fault call serviced from either user supervisor mode. there data breakpoint fault handler entry system procedure table, then breakpoint trace fault will lost. data breakpoint cannot break upon entering fault handler pointed system procedure table. Avoid setting data breakpoints fault handler entries system procedure table above mentioned fault cases. Fixed. Refer Summary Table Changes determine affected stepping(s).
Implication: Workaround: Status:
80960Jx Microprocessor Specification Update
Errata
Problem:
Actual Greater than Specified Data Sheets
actual maximum output valid delay PQFP packages outputs except ALE/ ALE# inactive DT/R# 15nS. original errata discussing increase TOV1 error should have been reported errata. following text errata number does apply designs effected. actual maximum output valid delay PQFP packages outputs except ALE/ALE# inactive DT/R# 18ns cold room temperatures degrees Celsius). This exceeds specified value (15ns) 80960Jx data sheets. systems requiring output valid times less than 18ns, wait states have added. There workarounds. Fixed. Refer Summary Table Changes determine affected stepping(s).
Problem:
Implication: Workaround: Status:
Problem:
level TRST#/RESET# Greater than Specified Data Sheets
input high level voltage (VIH) PQFP packages inputs TRST# RESET# 2.6V cold, room temperatures (-6, degrees Celsius). This exceeds specified value (2.0V) 80960Jx data sheets. Increased drive needed ensure threshold affected signals exceeded. There workarounds. Fixed. Refer Summary Table Changes determine affected stepping(s).
Implication: Workaround: Status:
Problem:
Power Supply Sequence Damage Internal Diodes
voltage VCCPLL VCC(I/O) power supply pins exceeds voltage time, including during power power down sequences, excessive currents permanently damage on-chip electrostatic discharge (ESD) protection diodes. damage accumulate over multiple episodes. VCC(I/O) pins appear only 132-lead PQFP package. Pragmatically, this problem only occurs when VCCPLL, VCC(I/O), pins driven separate power supplies voltage regulators. Applications that power supply VCCPLL, VCC(I/O), typically risk. Verify that your application does allow VCCPLL voltage exceed diodes connect VCCPLL VCC(I/O) circuitry VCC. Normally, those diodes unbiased reverse-biased, current flows. event positive electrostatic pulse VCCPLL VCC(I/O), diodes protect phase-locked loop input/output circuitry shunting excess charge VCC. However, when power supplies forward-bias these diodes length time, current flow damage destroy diodes. VCCPLL low-pass filter recommended datasheet does promote this problem. VCC5 power supply also susceptible excessive current damage, adequately protected series resistor recommended datasheet. 80960JA/JF/JD/JT Embedded 32-Bit Microprocessor datasheet more details.
Implication:
Diode damage manifest itself following:
Resistive short circuits between VCCPLL, VCC(I/O), pins Compromised protection VCCPLL VCC(I/O) pins
80960Jx Microprocessor Specification Update
Errata
Unspecified functional parametric failures resulting from damage circuitry near
diodes
Workaround:
common power supply regulator VCCPLL, VCC(I/O), pins. Otherwise, ensure that pins power-up before VCCPLL VCC(I/O) power-down after VCCPLL VCC(I/O). alternative VCCPLL limit VCCPLL diode current flow providing least resistance series with VCCPLL pin. Series resistance recommended VCC(I/O). NoFix. Refer Summary Table Changes determine affected stepping(s).
Status:
80960Jx Microprocessor Specification Update
Specification Changes
Specification Changes
Problem:
Specifications Changes
80960JA/JF Embedded 32-Bit Microprocessor Datasheet (272504-004), several timing specifications values have changed.
Table Halt Mode Jx-16 TOV1 TOV1 TBSOF1 TBSOF2 Jx-25 Jx-16 Jx-16 Jx-16 Spec Device Jx-33 Jx-25 Jx-16 Jx-25 Value 62.5 62.5 62.5 Value
Problem:
Specification Changes
80960JA/JF/JD/JT Embedded 32-Bit Microprocessor Datasheet (273159-001), values have changed.
Table Spec Active Power Supply Active Power Supply Device JA/JF-25 JA/JF-16 Value Value
Problem:
80960JT TIH1 Specification Change
80960JA/JF/JD/JT Embedded 32-Bit Microprocessor Datasheet (273159-002), timing specification changed 80960JT microprocessor.
Table Spec TIH1 Device Value Value
Problem:
80960JS/JC TIH1 Specification Change
80960JS/JC Microprocessor Datasheet (273200-002), timing specification changed.
Table Spec TIH1 Device JS/JC Value Value
80960Jx Microprocessor Specification Update
Specification Changes
Problem:
80960JS/JC/JT Extended Temperature TOV1 (min) Specification Change
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor Datasheet (273159-004), timing specification been added extended temperature 80960JS/JC/JT microprocessor.
Table Spec TOV1 (min) Device JS/JC/JT Value Value 1.75
80960Jx Microprocessor Specification Update
Specification Clarifications
Specification Clarifications
None this revision Specification Update.
80960Jx Microprocessor Specification Update
Documentation Changes
Documentation Changes
Issue:
80960JA/JF/JD/JS/JC/JT Datasheet
Incorporated 80960JS/JC datasheet into 80960JA/JF/JD/JT datasheet minimize redundant information.
Affected Docs: Previous datasheets:
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor datasheet,
Order #273159-002
80960JS/JC Microprocessor datasheet,
Order #273200-002 datasheet:
80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor datasheet,
Order #273159-003
Issue:
Updated MPBGA Thermal Data
Revised MPBGA thermal characteristics Section datasheet. Refer datasheet (listed Document Change above) specific changes. 80960JS/JC Microprocessor datasheet, Order #273200-002
Affected Docs: 80960JA/JF/JD/JT Embedded 32-Bit Microprocessor datasheet, Order #273159-002
Issue:
Revised 80960JA/JF/JD/JS/JC/JT datasheet
Revised 80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor datasheet, Order #273159 rev. 4.0. following changes were made datasheet:
Added extended temp JS/JC/JT timing parameter TOV1 (min). Specification
Change details).
Removed package offering 80960JS/JC/JT processors. Added extended temperature device offerings. Table datasheet.
Affected Docs: 80960JA/JF/JD/JS/JC/JT Embedded 32-Bit Microprocessor datasheet, Order #273159-004
80960Jx Microprocessor Specification Update
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