Bidirectional 4-Address Synthesiser DS3090 January 1997 SP55

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Bidirectional 4-Address Synthesiser DS3090 January 1997 SP55

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SP5511
Bidirectional 4-Address Synthesiser
DS3090 January 1997
SP5511 single-chip frequency synthesiser designed tuning systems. Control data entered standard format. 18-lead plastic package, SP5511 three addressable current-limited output ports (P0-P3) four bi-directional output ports (P0-P2) four addressable bi-directional open-collector ports (P4-P7) which also 3-bit 5-level input. information these ports read BUS. SP5511S variant 16-lead miniature plastic package, without P0-P2 functionally identical other respects SP5511. device four programmable addresses, allowing more synthesisers used system.
CHARGE PUMP CRYSTAL CRYSTAL
DRIVE OUTPUT INPUT INPUT OUTPUT PORT OUTPUT PORT OUTPUT PORT SELECT PORT
SP5511
PORT
FEATURES Complete Single Chip System
PORT
PORT PORT
Programmable Power Consumption (240mW Typ.) Radiation Phase Lock Detector Varactor Drive Disable Controllable Outputs, Bi-directional (SP5511) Bi-directional Controllable Outputs (SP5511S) 5-Level Variable Address Picture Picture Protection
DP18
CHARGE PUMP CRYSTAL CRYSTAL
DRIVE OUTPUT INPUT INPUT SELECT PORT PORT
SP5511S
PORT
PORT
PORT
Normal handling precautions should observed.
APPLICATIONS
Logic level port 3-bit input
MP16
Cable Tuning Systems VCRs
ORDERING INFORMATION
SP5511 (18-lead plastic package) SP5511S (16-lead miniature plastic package)
Fig. connections view
SP5511
ELECTRICAL CHARACTERISTICS
TAMB 210°C 180°C, references SP5511 (DP18 package). These Characteristics guaranteed either production test design. They apply within specified ambient temperature supply voltage ranges unless otherwise stated. Reference frequency 4MHz unless otherwise stated. Value Characteristic Supply current Prescaler input voltage Prescaler input impedance Prescaler input capacitance SDA, Input high voltage Input voltage Input high current Input current Leakage current Output voltage Charge pump current Charge pump current high Charge pump output leakage current Charge pump drive output current Charge pump amplifier gain Recommended crystal series resistance Crystal oscillator drive level Crystal oscillator negative resistance Output Ports P0-P2 sink current (see note P0-P2 leakage current (see note P4-P7 sink current P4-P7 leakage current Input Ports input current high input current input voltage input voltage high input current high input current Min. 15,16 15,16 Typ. 6170 6400 11-13 11-13 6,8,9 6,8,9 Parallel resonant crystal (note VOUT VOUT VOUT VOUT Max. mVrms 80MHz 1GHz mVrms Fig. Units Conditions
Input voltage Input voltage When Sink current Byte Byte Byte
Table levels
NOTES Ports P0-P2 present SP5511S maximum resistance quoted refers conditions, including start-up.
SP5511
ABSOLUTE MAXIMUM RATINGS
voltages referred Parameter SP5511 Supply voltage input voltage Port voltage 15,16 6-9,11-13 11-13 6-9,11-13 15-16 SP5511S 13,14 13-14 Min. Value Max. 1150 1150 °C/W °C/W °C/W °C/W With applied applied Port state Port state Port state Units Conditions
Total port output current input offset Charge pump offset Drive output offset Crystal oscillator offset SDA, input voltage
Storage temperature Junction temperature DP18 thermal resistance, chip-to-ambient DP18 thermal resistance, chip-to-case MP16 thermal resistance, chip-to-ambient MP16 thermal resistance, chip-to-case Power consumption
POWER DETECTOR LOCK DETECTOR DIVIDER RATIO LATCH TRANSCEIVER 8-BIT LATCH PORT INFORMATION ADDRESS SELECT 3-BIT LEVEL COMP CHARGE PUMP CONTROL DATA LATCH
PRESCALER
PROGRAMMABLE DIVIDER
FDIV
PHASE COMP
FCOMP
DIVIDER 4512
4MHz
CRYSTAL
CHARGE PUMP DRIVE OUTPUT
LOGIC
Fig. Block diagram. (Ports P0-P2 present SP5511S)
SP5511
SP5511 programmed from BUS. Data Clock lines respectively defined format. synthesiser either accept data (write mode) send data (read mode). Tables Fig. illustrate format data. device programmed respond several addresses, which enables more than synthesiser system. Table shows address selected applying voltage address input circuit shown Fig.6.The address Byte (R/W) sets device into read mode high write mode low. When SP5511 receives correct address Byte pulls line during acknowledge period during following acknowledge periods after further data Bytes programmed. When SP5511 programmed into read mode controlling device accepting data must pull down line during following acknowledge period read another status Byte.
FUNCTIONAL DESCRIPTION
WRITE MODE (FREQUENCY SYNTHESIS)
When device write mode Bytes select synthesised frequency while Bytes select output port states charge pump information. Once correct address received acknowledged, first next Byte determines whether that Byte interpreted Byte logic frequency information logic charge pump output port information. Additional data Bytes entered without need readdress device until stop condition recognised. This allows smooth frequency sweep fine tuning purposes. transmission data stopped mid-byte (i.e., another device bus) then previously programmed byte maintained. Frequency data from Bytes stored 15-bit shift register used control division ratio 15-bit programmable divider which preceded divide-by-8 prescaler amplifier give excellent sensitivity local oscillator input; input impedance shown Figs. programmed frequency calculated multiplying programmed division ratio times comparison frequency FCOMP. When frequency data entered, phase comparator, charge pump varactor drive amplifier, adjusts
local oscillator control voltage until output programmable divider frequency phase locked comparison frequency. reference frequency generated external source capacitively coupled into provided onchip 4MHz crystal controlled oscillator. Note that comparison frequency when 4MHz reference used. Byte programming data (CP) controls current charge pump circuit, logic 6170µA logic 650µA, allowing compensation variable tuning slope tuner also enable fast channel changes over full band. Byte (T0) disables charge pump logic Byte (OS) switches charge pump drive amplifier's output when logic Byte (T1) selects test mode where phase comparator inputs available logic connects FCOMP FDIV Byte programs output ports P0-P7, logic high impedance output, logic impedance (on).
READ MODE
When device read mode status data read from device line takes form shown Table (POR) power reset indicator logic power supply device dropped below nominal programmed information lost (e.g., when device initially turned on). when read sequence terminated stop command. outputs high impedance when device initially powered (FL) indicates whether device phase locked, logic present device locked logic device unlocked. Bits (I2, show status Ports respectively. logic indicates level logic high level. ports used inputs they should programmed high impedance state (logic1). These inputs will then respond data complying with standard voltage levels. Bits (A2,A1,A0) combine give output 5-level ADC. 5-level used feed information microprocessor from section television, illustrated Fig.
SP5511
Address Programmable divider Programmable divider Charge pump test bits port control bits
Byte Byte Byte Byte Byte
Table Write data format (MSB transmitted first)
Address Status byte
Byte Byte
Table Read data format
Voltage input Voltage input Open circuit
Table levels
MA1, P2*, P1*, NOTE
Table Address selection
Acknowledge Variable address bits (see Table Charge Pump current select Test mode selection Charge pump disable Varactor drive Output disable Switch Control output port states Power Reset indicator Phase lock detect flag Digital information from ports respectively 5-level data from (see Table
Programmed connecting resistor between Don't care condition SP5511S.
Fig. Data formats
SP5511
APPLICATION
typical application shown Fig. input/output interface circuits shown Fig.
130V 112V 180n 4MHz 2N3906 2N3906 2N3906 OSCILLATOR OUTPUT 2N3904 VARACTOR DRIVE
CONTROL MICRO
SP5511
TUNER
BAND INPUTS
112V
SECTION
SIGNAL
Fig. Typical application
INTO
OPERATING WINDOW
1000 FREQUENCY (MHz)
1300
1500
Fig. Typical input sensitivity
SP5511
VREF
CHARGE PUMP
INPUTS DRIVE OUTPUT
input
Loop amplifier
SCL/SDA
ONLY
Address programming port
inputs
P0-P2 PORT
12k* CRYSTAL
RESISTOR
P4-P7
CRYSTAL
Reference oscillator
Ports P0-P2 P4-P7 (SP5511). only SP5511S
Fig. SP5511 input/output interface circuits
SP5511
S11:ZO NORMALISED
FREQUENCY MARKER STEP 250MHz
Fig. Typical input impedance, SP5511
S11:ZO NORMALISED
FREQUENCY MARKER STEP 250MHz
Fig. Typical input impedance, SP5511S
SP5511
PACKAGE DETAILS
Dimensions shown thus: (in).
NOTCH CTRS
LEADS NOM. SPACING
18-LEAD PLASTIC DP18
This package outline diagram guidance only. Please contact your Customer Service Centre further information.
345°
SPOT REF. CHAMFER REF.
0-8°
LEADS SPACING
16-LEAD MINIATURE PLASTIC MP16
This package outline diagram guidance only. Please contact your Customer Service Centre further information.
SP5511
NOTES
SP5511
NOTES
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Bidirectional 4-Address Synthesiser DS3090 January 1997 SP55

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