PRODUCT DESCRIPTION FEATURES Multiple gate array sizes 600,000 usable

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PRODUCT DESCRIPTION FEATURES Multiple gate array sizes 600,000 usable

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UT0.6µCR/SRH Commercial RadHardand Strategic RadHardGate Array Family
PRODUCT DESCRIPTION FEATURES Multiple gate array sizes 600,000 usable equivalent gates Toggle rates Advanced 0.6µ (0.5µLeff radiation-tolerant silicon gate CMOS processed commercial Operating voltage and/or 3.3V Class compliant Designed specifically high reliability applications Commercial RadHardfor radiation-tolerant 300K rads meet space requirements SEU-immune less than 2.0E-10 errors/bit-day Strategic RadHard radiation environments Mega rads meet space requirements SEU-immune less than 2.0E-10 errors/bit-day JTAG (IEEE 1149.1) boundary-scan supported noise package technology high speed circuits Design support using Mentor Graphics® Synopsysin VHDL Verilog design languages Sun® Linux workstations Supports cold sparing power down applications Supports voltage translation 3.3V 3.3V high-performance UT0.6µCRH/SRH gate array family features densities 600,000 equivalent gates available MIL-PRF-38535 product assurance levels radiation-tolerant. Commercial RadHard Strategic RadHardsilicon fabricated American Microsystems Incorporated (AMI) using minimally invasive processing module, developed UTMC, that enhances total dose radiation hardness field gate oxides while maintaining circuit density reliability. addition, both greater transient radiation-hardness latchup immunity, UTMC 0.6µ process built epitaxial substrate wafers. Developed using UTMC's patented architectures, UT0.6µCRH/SRH gate array family uses highly efficient continuous column transistor architecture internal cell construction. Combined with state-of-the-art placement routing tools, utilization available transistors maximized using three levels metal interconnect. UT0.6µCRH/SRH family gate arrays supported extensive cell library that includes SSI, MSI, 54XX equivalent functions, well configurable cores. UTMC's core library includes following functions: Intel 80C31® equivalent Intel 80C196® equivalent MIL-STD-1553 functions (BRCTM, RTI, RTMP) MIL-STD-1750 microprocessor RISC microcontroller Configurable (SRAM, DPSRAM) USART (82C51) EDAC
Table Gate Densities DEVICE PART NUMBERS UT06MRA010 UT06MRA025 UT06MRA050 UT06MRA075 UT06MRA100 UT06MRA150 UT06MRA200 UT06MRA250 UT06MRA300 UT06MRA350 UT06MRA400 UT06MRA450 UT06MRA500 UT06MRA550 UT06MRA600 EQUIVALENT USABLE GATES1 SIGNAL I/O2 10,000 25,000 50,000 75,000 100,000 150,000 200,000 250,000 300,000 350,000 400,000 450,000 500,000 550,000 600,000 POWER GROUND PADS3
Notes: .Based NAND2 equivalents. Actual usable gate count design-dependent. Estimates reflect functions including RAM. .Includes five pins that reserved JTAG boundary-scan, depending user requirements. .Reserved dedicated DD/V DDQ/V SSQ.
Low-noise Device Package Solutions UT0.6µCR H/SRH array family's output drivers feature programmable slew rate control minimizing noise switching transients. This feature allows user optimize edge characteristics match system requirements. Separate on-chip power ground buses provided internal cells output drivers which further isolate internal design circuitry from switching noise. addition, Aeroflex UTMC offers advanced low-noise package technology with multi-layer, co-fired ceramic construction featuring built-in isolated power ground planes (see Table These planes provide lower overall resistance/inductance
through power ground paths which minimize voltage drops during periods heavy switching. These isolated planes also help sustain supply voltage during dose rate events, thus preventing rail span collapse. Flatpacks available with leads; PGAs available with pins LGAs pins. Aeroflex UTMC's flatpacks feature non-conductive that helps maintain lead integrity through test handling operations. addition packages listed Table Aeroflex UTMC offers custom package development package tooling modification services individual requirements.
Table Packages
PACKAGE TYPE/ LEADCOUNT1
Flatpack PGA2
Notes: number device pads available restricted selected package. packages have additional non-connected index (i.e., index total package pins PGA). Contact Aeroflex UTMC specific package drawings.
Extensive Cell Library UT0.6µCRH/SRH family gate arrays supported extensive cell library that includes SSI, MSI, 54XX-equivalent functions, well other library functions. Userselectable options cell configurations include scan register elements, well output drive strength. Aeroflex UTMC's core library includes following functions: Intel® 80C31 equivalent Intel® 80C196 equivalent MIL-STD-1553 functions (BCRTM, RTI, RTMP) MIL-STD-1750 microprocessor Standard microprocessor peripheral functions Configurable (SRAM, DPsRAM) RISC Microcontroller USART (82C51) EDAC
JTAG Boundary-Scan UT0.6µCRH/SRH arrays provide test access port boundary-scan that conforms IEEE Standard 1149.1 (JTAG). Some benefits this capability are: Easy test complex assembled printed circuit boards Gain access control internal scan paths Initiation Built-In Self Test Clock Driver Distribution Aeroflex UTMC design tools provide methods balanced clock distribution that maximize drive capability minimize relative clock skew between clocked devices. Speed Performance Aeroflex UTMC specializes high-performance circuits designed operate harsh military radiation environments. Table presents sampling typical cell delays. Note that propagation delay CMOS device function fanout loading, input slew, supply voltage, operating temperature, processing radiation tolerance. radiation environment, additional performance variances must considered. UT0.6µCRH/SRH array family simulation models account these effects accurately determine circuit performance particular conditions. Power Dissipation Each internal gate driver average power consumption based switching frequency capacitive loading. Radiation-tolerant processes exhibit power dissipation that typical CMOS processes. rigorous power estimating methodology, refer Aeroflex UTMC UT0.6µCRH/SRH Design Manual consult with Aeroflex UTMC Applications Engineer. Typical Power Dissipation 1.1µW/Gate-MHz@5.0V 0.4µW/Gate-MHz@3.3V
Refer Aeroflex UTMC's UT0.6µCRH/SRH Design Manual complete cell listing details. Buffers UT0.6µCRH/SRH gate array family offers signal locations (note: device signal availability affected package selection pinout.) cells configured user serve input, output, bidirectional, three-state, additional power ground pads. Output drive options range from 12mA. drive larger off-chip loads, output drivers combined parallel provide additional drive 24mA. Other buffer features options include: Slew rate control Pull-up pull-down resistors TTL, CMOS, Schmitt levels Cold sparing Voltage translation 3.3V 3.3V
Table Typical Cell Delays CELL Internal Gates INV1, Inverter INV4, Inverter NAND2, 2-Input NAND NOR2, 2-Input Output Buffers OC5050N4, CMOS OT5050N4, TTL, OT5050N12, TTL, 12mA Input Buffers IC5050, CMOS IT5050, 1.16 1.39 1.16 1.07 1.18 1.12 1.30 3.85 4.66 5.58 2.52 2.42 1.29 2.15 3.76 5.49 2.93 OUTPUT TRANSITION PROPAGATION DELAY 5.0V 3.3V 1.12 1.06 1.05
Note: specifications (typical). Output load capacitance 50pF. Fanout loading input buffers gates equivalen gate input loads.
ASIC DESIGN SOFTWARE Using combination state-of-the-art third-party proprietary design tools, Aeroflex UTMC delivers support capability handle complex, high-performance ASIC designs from design concept through design verification test. Aeroflex UTMC's flexible circuit creation methodology supports high level design providing UT0.6µCRH/SRH libraries Mentor Graphics Synopsys synthesis tools. Design verification performed VHDL Verilog simulator Mentor Graphics environment, using Aeroflex UTMC's robust libraries. Aeroflex UTMC also supports Automatic Test Program Generation improve design testing. Aeroflex UTMC DESIGN SYSTEMS
VHDL libraries VITAL compliant, Verilog libraries compliant.With library capabilities Aeroflex UTMC provides, High Level Design methods synthesize your design simulation. Aeroflex UTMC also provides tools verify that your design will result working ASIC devices. Either Aeroflex UTMC's design system lets easily access Aeroflex UTMC's RadHard capabilities. ADVANTAGES AEROFLEX UTMC DESIGN SYSTEMS Aeroflex UTMC Design System gives freedom tools from Synopsys, Mentor Graphics, Cadence, Viewlogic, other vendors help synthesize verify design. Aeroflex UTMC's Logic Rules Checker Tester Rules Checker allow verify partial complete designs compliance with Aeroflex UTMC design rules. Aeroflex UTMC Design System accepts backannotation timing information through SDF. Your design stays entirely within language which started (VHDL Verilog) preventing conversion headaches.
Aeroflex UTMC offers Hardware Description Language (HDL) design system supporting VHDL Verilog. Both VHDL Verilog libraries provide sign-off quality models robust tools. High Level Design Activities
XDTsm (eXternal Design Translation) Tool Supplier Mentor ModelSim Through Aeroflex UTMC's services, customers convert existing non-Aeroflex UTMC design Aeroflex UTMC's processes. tool particularly useful converting FPGA Aeroflex UTMC radiation-tolerant gate array. translation tools convert industry standard netlist formats vendor libraries Aeroflex UTMC formats libraries. Industry standard netlist formats supported Aeroflex UTMC include: VHDL Verilog HDLFPGA source files (Actel, Altera, Xilinx) EDIF Third-party netlists supported Synopsys
Synopsys VSS/VCS
Cadence Leapfrog Verilog
Viewlogic SpeedWave/
UTMC Design System
Completed ASIC Design
Aeroflex UTMC Design Flow
AEROFLEX UTMC MENTOR GRAPHICS DESIGN SYSTEM Aeroflex UTMC Mentor Graphics Design System software fully integrated into Mentor Graphics design environment, making familiar easy use. Aeroflex UTMC tools support Mentor functions such crosshighlighting, graphical menus, design navigation.
Design Idea
Convert FPGA
Schematic Entry Translate External Design
ADVANTAGES AEROFLEX UTMC MENTOR DESIGN SYSTEM Aeroflex UTMC customers have successfully used Aeroflex UTMC Mentor Graphics Design System over decade. Aeroflex UTMC's Logic Tester Rules Checker tools allow verify partial complete designs compliance with Aeroflex UTMC manufacturing practices procedures. Design System accepts pre-and post-layout timing information ensure your design results devices that meet your specifications. Design System supports Leonardo, database transfer between Synopsys Mentor. Design System supports powerful Mentor Graphics ATPG capabilities. TOOLS SUPPORTED AEROFLEX UTMC Aeroflex UTMC supports libraries for: Mentor Graphics ModelSim Synopsys Design Compiler PrimeTime Formality TetraMax VITAL-compliant VHDL Tools OVI-compliant Verilog Tools
Synthesis
UTMC Mentor Design System
Design Manufacturing Aeroflex UTMC Mentor Graphics Design
TRAINING SUPPORT After creating design Mentor Graphics environment, easily verify design electrical rules compliance with Aeroflex UTMC Logic Rules Checker. Testability verified with Aeroflex UTMC Tester Rules Checker. Both these tools fully integrated into Mentor Graphics Environment. When have completed design activities, Aeroflex UTMC's Design Transfer tool captures required files prepares them easy transfer Aeroflex UTMC. Aeroflex UTMC uses this data convert your design into packaged tested device. Aeroflex UTMC personnel conduct training classes tailored meet individual needs. These classes address wide engineering backgrounds specific customer concerns. Applications assistance also available through phases ASIC Design.
PHYSICAL DESIGN Using three layers metal interconnect, Aeroflex UTMC achieves optimized layouts that maximize speed critical nets, overall chip performance, design density 600,000 equivalent gates. Test Capability Aeroflex UTMC supports phases test development from test stimulus generation through high-speed production test. This support includes ATPG, fault simulation, fault grading. Scan design options available UT0.6µCRH/SRH storage elements. Automatic test program development capabilities handle large vector sets with Aeroflex UTMC's LTX/ Trillium MicroMasters, supporting high-speed testing 80MHz with multiplexing). Unparalleled Quality Reliability Aeroflex UTMC dedicated meeting stringent performance requirements aerospace defense systems suppliers. Aeroflex UTMC maintains highest level quality reliability through Quality Management Program under MILPRF-38535 ISO-9001. 1988, were first gate array manufacturer achieve certification qualification technology families. product assurance program kept pace with demands certification qualification. quality management plan includes following activities initiatives. Quality improvement plan Failure analysis program plan Corrective action plan Change control program Standard Evaluation Circuit (SEC) Technology Characterization Vehicle (TCV) assessment program Certification qualification program Because numerous product variations permitted with customer specific designs, much reliability testing performed using Standard Evaluation Circuit (SEC) Technology Characterization Vehicle (TCV). utilizes test structures
evaluate carrier aging, electromigration, time dependent test samples reliability testing. Data from wafer-level testing provide rapid feedback fabrication process, well establish reliability performance product before packaged shipped. Radiation Tolerance Aeroflex UTMC incorporates radiation-tolerance techniques process design, design rules, array design, power distribution, library element design. radiation-tolerance process parameters controlled monitored using statistical methods in-line testing.
PARAMETER Total dose
RADIATION TOLERANCE 1.0E5 rad(SiO 3.0E5 rad(SiO2) 1.0E8 rad(Si)/sec 1.0E11 rad(Si)/sec <2.0E-10 errors cell-day 1.0E14 n/sq Latchup-immune over specified conditions
NOTES
Dose rate upset Dose rate survivability Projected neutron fluence Latchup
Notes: Total dose Co-60 testing accordance with MIL-STD-883, Method 1019. Data sheet electrical characteristics guaranteed 1.0E5 rads(Si O2). post-radiation values measured Total dose Co-60 testing accordance with MIL-STD-883, Method 1019 dose rates rad(Si )/s. Short pulse 20ns FWHM (full width, half maximum). design dependent; limit based standard evaluation circuit 4.5V worst case condition. SEU-hard flip-flop cell. Non-hard flip-flop typical 4E-8.
ABSOLUTE MAXIMUM RATINGS (Referenced SYMBOL TSTG PARAMETER supply voltage Voltage Storage temperature Maximum junction temperature Latchup immunity input current Lead temperature (soldering sec) LIMITS -0.3 6.0V -0.3V +150°C +175°C
+150mA +10mA
+300°C
Note: Stresses outside listed absolute maximum ratings cause permanent damage device. This stress rating only, functional operation device these other conditions beyond limits indicated operational sections this specification recommended. Exposure absolute maximum rating conditions extended periods affect device reliability.
RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER Positive supply voltage Case temperature range input voltage LIMITS 5.5V +125C
ELECTRICAL CHARACTERISTICS (VDD 5.0V +10%; -55°C +125°C) SYMBOL PARAMETER Low-level input voltage inputs CMOS High-level input voltage inputs CMOS Schmitt Trigger, positive going threshold Schmitt Trigger, negative going threshold Schmitt Trigger, typical range hysteresis Input leakage current TTL, CMOS, Schmitt inputs Inputs with pull-down resistors Inputs with pull-down resistors Inputs with pull-up resistors Inputs with pull-up resistors Cold Spare Inputs Normal Mode Cold Spare Inputs Cold Spare Mode 5.5V 5.5V 5.5V 4.5V 2.0mA 4.0mA 8.0mA 12.0mA 1.0µA 100µA 100µA 4.5V -2.0mA -4.0mA -8.0mA -12.0mA -1.0µA -100µA -100µA CONDITION 4.5V 5.5V .7VDD -225 +225 UNIT
4.5V 5.5V
4.5V 5.5V 4.5V 5.5V
Low-level output voltage3 2.0mA buffer 4.0mA buffer 8.0mA buffer 12.0mA buffer CMOS outputs CMOS outputs (optional) CMOS outputs (cold spare)
0.05 0.25 0.25 DD-0.05 DD-0.35 DD-0.35
High-level output voltage 2.0mA buffer 4.0mA buffer 8.0mA buffer 12.0mA buffer CMOS outputs CMOS outputs (optional) CMOS outputs (cold spare)
SYMBOL
PARAMETER Three-state output leakage current 2.0mA buffer 4.0mA buffer, CMOS 8.0mA buffer 12.0mA buffer Cold Spare Inputs normal mode Cold Spare Inputs cold spare mode
CONDITION 5.5V
UNIT
5.5V 5.5V 5.5V
Short-circuit output current 2.0mA buffer 4.0mA buffer, CMOS 8.0mA buffer 12.0mA buffer Quiescent Supply Current Group subgroups
-100 -200 -300
IDDQ
5.5V 200K gates 400K gates 600K gates
Group subgroup
5.5V 200K gates 400K gates 600K gates
Group subgroup Designator:
5.5V 200K gates 400K gates 600K gates
COUT
Input capacitance
Output capacitance 2.0mA buffer 4.0mA buffer 8.0mA buffer, CMOS 12.0mA buffer Bidirect capacitance 4.0mA buffer 8.0mA buffer, CMOS 12.0mA buffer
Notes: Contact Aeroflex UTMC prior usage. Functional tests conducted accordance with MIL-STD-883 with following input test conditions: IH(min) 20%, (max) 50%, specified herein, TTL, CMOS, Schmitt compatible inputs. Devices tested using input voltage within above specified range, guaranteed VIH(min) IL(max). Supplied design limit guaranteed tested. MIL-PRF-38535, current density 5.0E5 amps/cm maximum product load capacitance (per output buffer) times frequency should exceed 3,765pF*MHz. more than output shorted time maximum duration second. Capacitance measured initial qualification when design changes affect value. Capacitance measured between designated terminal frequency 1MHz signal amplitude <50mV RMS. inputs with internal pull-ups should left floating. other inputs should tied high low.
ELECTRICAL CHARACTERISTICS (VDD 3.3V +.3V; -55°C +125°C) SYMBOL PARAMETER Low-level input voltage CMOS High-level input voltage CMOS
CONDITION 3.0V 3.6V
.3VDD
UNIT
3.0V 3.6V .7VDD 3.0V 3.6V 3.0V 3.6V .3VDD 3.6V 3.6V 3.6V .7VDD
Schmitt Trigger, positive going threshold Schmitt Trigger, negative going threshold Schmitt Trigger, typical range hysteresis Input leakage current TTL, CMOS, Schmitt inputs Inputs with pull-down resistors Inputs with pull-down resistors Inputs with pull-up resistors Inputs with pull-up resistors Cold Spare Inputs normal mode Cold Spare Inputs cold spare mode
-225
+225
Low-level output voltage CMOS outputs CMOS outputs (optional) CMOS outputs (cold spare) High-level output voltage CMOS outputs CMOS outputs (optional) CMOS outputs (cold spare)
1.0µA 100µA 100µA 0.05 0.25 0.25 -1.0µA -100µA -100µA -0.05 -0.35 -0.35
SYMBOL
PARAMETER Three-state output leakage current CMOS Cold Spare Inputs normal mode Cold Spare Inputs cold spare mode
CONDITION 3.6V 3.6V
UNIT
IDDQ
Short-circuit output current CMOS Quiescent Supply Current Group subgroups
-200
5.5V 200K gates 400K gates 600K gates
Group subgroup
5.5V 200K gates 400K gates 600K gates
Group subgroup designator:
5.5V 200K gates 400K gates 600K gates
COUT
Input capacitance
Output capacitance CMOS
Bidirect capacitance CMOS
Notes: Contact Aeroflex UTMC prior usage. Functional tests conducted accordance with MIL-STD-883 with following input test conditions: IH(min) 20%, (max) 50%, specified herein, TTL, CMOS, Schmitt compatible inputs. Devices tested using input voltage within above specified range, guaranteed VIH(min) IL(max). Supplied design limit guaranteed tested. MIL-PRF-38535, current density 5.0E5 amps/cm maximum product load capacitance (per output buffer) times frequency should exceed 3,765pF*MHz. more than output shorted time maximum duration second. Capacitance measured initial qualification when design changes affect value. Capacitance measured between designated terminal frequency 1MHz signal amplitude <50mV RMS. inputs with internal pull-ups should left floating. other inputs should tied high low.
HP/Apollo HP-UX registered trademarks Hewlett-Packard, Inc. Intel registered trademark Intel Corporation Mentor, Mentor Graphics, AutoLogic QuickSim QuickFault QuickHDL, QuickGrade FastScan, FlexTest Advisor registered trademarks Mentor Graphics Corporation registered trademark Microsystems, Inc. Verilog Leapfrog registered trademarks Cadence Design Systems, Inc. Synopsys, Design Compiler, Test Compiler Plus, VHDL Compiler, Verilog Compiler, TestSim trademarks Synopsys, Inc. Vantage trademark Viewlogic
Notes

PRODUCT DESCRIPTION FEATURES Multiple gate array sizes 600,000 usable

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