FEATURES 3,000,000 usable equivalent gates using structured array arch
|
|
|
Top Searches for this datasheet
UT0.25µCRH Commercial RadHardStructured Array
FEATURES 3,000,000 usable equivalent gates using structured array architecture Toggle rates Advanced 0.25µ silicon gate CMOS processed commercial Operating voltage 3.3V 2.5V buffers 5-volt compliant Multiple product assurance levels available, military, industrial Radiation hardened from 100Krads(Si) Megarad total dose available using Aeroflex UTMC's RadHard techniques SEU-immune less than 1.0E-10 errors/bits-day available using special library cells Robust Aeroflex UTMC Design Library cells macros Design support Mentor Graphics®, Synopsys Verilog VHDL design languages Linux workstations Full complement industry standard cores Configurable compilers Supports cold sparing power down applications Power dissipation 0.04µW/MHz/gate VDDCORE 2.5V duty cycle
PRODUCT DESCRIPTION high-performance UT0.25µ Commercial RadHardASIC structured array family features densities 3,000,000 equivalent gates available multiple quality assurance levels such MIL-PRF-38535, military industrial grades non-RadHard versions. those designs requiring stringent radiation hardness, Aeroflex UTMC's 0.25µ deep sub-micron process employs special technique that enhances total dose radiation hardness from 100Krads(Si) Megarad while maintaining circuit density reliability. addition, both greater transient radiation hardness latch-up immunity, deep submicron process built epitaxial wafers. Developed from Aeroflex UTMC's patented architectures, deep submicron ASIC family uses highly efficient structured array architecture internal cell instantiation. Combined with state-of-the-art placement routing tools, area utilization signal interconnect transistors maximized using five levels metal interconnect. UT0.25µCRH ASIC family supported extensive cell library that includes SSI, MSI, 54XX equivalent functions, well configurable cores. Aeroflex UTMC's core library includes following functions: Intel 80C31® equivalent Intel 80C196® equivalent MIL-STD-1553 functions (BRCTM, RTI, RTMP) MIL-STD-1750 microprocessor RISC microcontroller Configurable
Table Gate Densities SIZE (Mils estimate) EQUIVALENT USABLE GATES1 SIGNAL I/O2 276,890 501,760 757,350 1,024,000 1,524,122 2,007,040 2,524,058 3,029,402 POWER GROUND PADS
Notes: Based NAND2 equivalents plus routing overhead. Actual usable gate count design-dependent. Includes five pins that reserved JTAG boundary-scan, depending user requirements.
Low-noise Device Package Solutions Separate on-chip power ground buses provided internal cells output drivers which further isolate internal design circuitry from switching noise. addition, Aeroflex UTMC offers advanced low-noise package technology with multi-layer, co-fired ceramic construction featuring built-in isolated power ground planes (see Table These planes provide lower overall resistance/inductance through power ground paths which minimize voltage drops during periods heavy switching. These isolated planes also
help sustain supply voltage during dose rate events, thus preventing rail span collapse. Flatpacks available with leads; PGAs available with pins LGAs pins. Aeroflex UTMC's flatpacks feature non-conductive that helps maintain lead integrity through test handling operations. addition packages listed Table Aeroflex UTMC offers custom package development package tooling modification services individual requirements.
Table Packages Type Flatpack Package 132, 172, 196, 256, 304, 340, 281,
Notes: number device pads available restricted selected package. packages have additional non-connected index (i.e., index total package pins PGA). Contact Aeroflex UTMC specific package drawings.
Extensive Cell Library UT0.25µCRH family gate arrays supported extensive cell library that includes SSI, MSI, 54XX-equivalent functions, well other library functions. Userselectable options cell configurations include scan register elements, well output drive strength. Aeroflex UTMC's core library includes following functions: Intel® 80C31 equivalent Intel® 80C196 equivalent MIL-STD-1553 functions (BCRTM, RTI, RTMP) MIL-STD-1750 microprocessor Standard microprocessor peripheral functions Configurable (SRAM, DPsRAM) RISC Microcontroller USART (82C51) EDAC
JTAG Boundary-Scan UT0.25µCRH arrays provide test access port boundary-scan that conforms IEEE Standard 1149.1 (JTAG). Some benefits this capability are: Easy test complex assembled printed circuit boards Gain access control internal scan paths Initiation Built-In Self Test Clock Driver Distribution Aeroflex UTMC design tools provide methods balanced clock distribution that maximize drive capability minimize relative clock skew between clocked devices. Speed Performance Aeroflex UTMC specializes high-performance circuits designed operate harsh military radiation environments. Table presents sampling typical cell delays. Note that propagation delay CMOS device function fanout loading, input slew, supply voltage, operating temperature, processing radiation tolerance. radiation environment, additional performance variances must considered. UT0.25µCRH array family simulation models account these effects accurately determine circuit performance particular conditions. Power Dissipation Each internal gate driver average power consumption based switching frequency capacitive loading. Radiation-tolerant processes exhibit power dissipation that typical CMOS processes. rigorous power estimating methodology, refer Aeroflex UTMC UT0.25µCRH Design Manual consult with Aeroflex UTMC Applications Engineer. Typical Power Dissipation 0.04µW/Gate-MHz@2.5V duty cycle
Refer Aeroflex UTMC's UT0.25µCRH Design Manual complete cell listing details. Buffers UT0.25µCRH gate array family offers signal locations (note: device signal availability affected package selection pinout.) cells configured user serve input, output, bidirectional, three-state, additional power ground pads. Output drive options range from 12mA. drive larger off-chip loads, output drivers combined parallel provide additional drive 24mA. Other buffer features options include: Pull-up pull-down resistors Schmitt trigger LVDS Cold Sparing
Table Typical Cell Delays CELL Internal Gates INV1, Inverter INV4, Inverter NAND2, 2-Input NAND NOR2, 2-Input Output Buffers OC3325N4_C, CMOS OC3325N12_C, CMOS Input Buffers IC3325_C, CMOS .468 .313 4.599 6.578 3.060 3.758 OUTPUT TRANSITION PROPAGATION DELAY 2.5V .068 .090 .035 .050 .102 .103 .080 .148 .391 .394 .474 .352
Note: specifications (typical). Output load capacitance 50pF. Fanout loading input buffers gates equivalent gate input loads.
ASIC DESIGN SOFTWARE Using combination state-of-the-art third-party proprietary design tools, Aeroflex UTMC delivers support capability handle complex, high-performance ASIC designs from design concept through design verification test. Aeroflex UTMC's flexible circuit creation methodology supports high level design providing UT0.25µCRH libraries Mentor Graphics Synopsys synthesis tools. Design verification performed VHDL Verilog simulator Mentor Graphics environment, using Aeroflex UTMC's robust libraries. Aeroflex UTMC also supports Automatic Test Program Generation improve design testing. Aeroflex UTMC DESIGN SYSTEMS Aeroflex UTMC offers Hardware Description Language (HDL) design system supporting VHDL Verilog. Both VHDL Verilog libraries provide sign-off quality models robust tools. High Level Design Activities
VHDL libraries VITAL compliant, Verilog libraries compliant.With library capabilities Aeroflex UTMC provides, High Level Design methods synthesize your design simulation. Aeroflex UTMC also provides tools verify that your design will result working ASIC devices. Either Aeroflex UTMC's design system lets easily access Aeroflex UTMC's RadHard capabilities. ADVANTAGES AEROFLEX UTMC DESIGN SYSTEMS Aeroflex UTMC Design System gives freedom tools from Synopsys, Mentor Graphics, Cadence, Viewlogic, other vendors help synthesize verify design. Aeroflex UTMC's Logic Rules Checker Tester Rules Checker allow verify partial complete designs compliance with Aeroflex UTMC design rules. Aeroflex UTMC Design System accepts backannotation timing information through SDF. Your design stays entirely within language which started (VHDL Verilog) preventing conversion headaches.
XDTsm (eXternal Design Translation) Tool Supplier Mentor ModelSim Through Aeroflex UTMC's services, customers convert existing non-Aeroflex UTMC design Aeroflex UTMC's processes. tool particularly useful converting FPGA Aeroflex UTMC radiation-tolerant gate array. translation tools convert industry standard netlist formats vendor libraries Aeroflex UTMC formats libraries. Industry standard netlist formats supported Aeroflex UTMC include: VHDL Verilog HDLFPGA source files (Actel, Altera, Xilinx) EDIF Third-party netlists supported Synopsys
Synopsys VSS/VCS
Cadence Leapfrog Verilog
Viewlogic SpeedWave/
UTMC Design System
Completed ASIC Design
Aeroflex UTMC Design Flow
AEROFLEX UTMC MENTOR GRAPHICS DESIGN SYSTEM Aeroflex UTMC Mentor Graphics Design System software fully integrated into Mentor Graphics design environment, making familiar easy use. Aeroflex UTMC tools support Mentor functions such crosshighlighting, graphical menus, design navigation.
Design Idea
Convert FPGA
Schematic Entry Translate External Design
ADVANTAGES AEROFLEX UTMC MENTOR DESIGN SYSTEM Aeroflex UTMC customers have successfully used Aeroflex UTMC Mentor Graphics Design System over decade. Aeroflex UTMC's Logic Tester Rules Checker tools allow verify partial complete designs compliance with Aeroflex UTMC manufacturing practices procedures. Design System accepts pre-and post-layout timing information ensure your design results devices that meet your specifications. Design System supports Leonardo, database transfer between Synopsys Mentor. Design System supports powerful Mentor Graphics ATPG capabilities. TOOLS SUPPORTED AEROFLEX UTMC Aeroflex UTMC supports libraries for: Mentor Graphics ModelSim Synopsys Design Compiler PrimeTime Formality TetraMax VITAL-compliant VHDL Tools OVI-compliant Verilog Tools
Synthesis
UTMC Mentor Design System
Design Manufacturing Aeroflex UTMC Mentor Graphics Design After creating design Mentor Graphics environment, easily verify design electrical rules compliance with Aeroflex UTMC Logic Rules Checker. Testability verified with Aeroflex UTMC Tester Rules Checker. Both these tools fully integrated into Mentor Graphics Environment. When have completed design activities, Aeroflex UTMC's Design Transfer tool captures required files prepares them easy transfer Aeroflex UTMC. Aeroflex UTMC uses this data convert your design into packaged tested device.
TRAINING SUPPORT Aeroflex UTMC personnel conduct training classes tailored meet individual needs. These classes address wide engineering backgrounds specific customer concerns. Applications assistance also available through phases ASIC Design.
PHYSICAL DESIGN Using five layers metal interconnect, Aeroflex UTMC achieves optimized layouts that maximize speed critical nets, overall chip performance, design density 3,000,000 equivalent gates. Test Capability Aeroflex UTMC supports phases test development from test stimulus generation through high-speed production test. This support includes ATPG, fault simulation, fault grading. Scan design options available UT0.25µCRH storage elements. Automatic test program development capabilities handle large vector sets with Aeroflex UTMC's LTX/ Trillium MicroMasters, supporting high-speed testing 80MHz with multiplexing). Unparalleled Quality Reliability Aeroflex UTMC dedicated meeting stringent performance requirements aerospace defense systems suppliers. Aeroflex UTMC maintains highest level quality reliability through Quality Management Program under MIL-PRF-38535 ISO-9001. 1988, were first gate array manufacturer achieve certification qualification technology families. product assurance program kept pace with demands certification qualification. quality management plan includes following activities initiatives. Quality improvement plan Failure analysis program plan Corrective action plan Change control program Standard Evaluation Circuit (SEC) Technology Characterization Vehicle (TCV) assessment program Certification qualification program Because numerous product variations permitted with customer specific designs, much reliability testing performed using Standard Evaluation Circuit (SEC) Technology Characterization Vehicle (TCV). Aeroflex UTMC utilizes
wafer foundry's data from test structures evaluate carrier aging, electromigration, time dependent test samples reliability testing. Data from wafer-level testing provide rapid feedback fabrication process, well establish reliability performance product before packaged shipped. Radiation Tolerance Aeroflex UTMC incorporates radiation-tolerance techniques process design, design rules, array design, power distribution, library element design. radiation-tolerance process parameters controlled monitored using statistical methods in-line testing.
PARAMETER Total dose
RADIATION TOLERANCE 1.0E5 rad(SiO2) 3.0E5 rad(SiO 1.0E8 rad(Si)/sec 1.0E11 rad(Si)/sec <2.0E-10 errors cell-day 1.0E14 n/sq Latchup-immune over specified conditions
NOTES
Dose rate upset Dose rate survivability Projected neutron fluence Latchup
Notes: Total dose Co-60 testing accordance with MIL-STD-883, Method 1019. Data sheet electrical characteristics guaranteed 1.0E5 rads(Si O2). post-radiation values measured Total dose Co-60 testing accordance with MIL-STD-883, Method 1019 dose rates rad(Si )/s. Short pulse 20ns FWHM (full width, half maximum). design dependent; limit based standard evaluation circuit 4.5V worst case condition. SEU-hard flip-flop cell. Non-hard flip-flop typical 4E-8.
ABSOLUTE MAXIMUM RATINGS (Referenced SYMBOL VDDCORE DDCORE DDCORE TSTG PARAMETER Supply Voltage Core Supply Voltage Voltage Difference Voltage Difference Storage temperature Maximum junction temperature Latchup immunity input current Lead temperature (solder sec) LIMITS -0.3V 4.0V 2.8V 4.3V 3.1V +150°C +175°C
+150mA +10mA
+300°C
Note: Stresses outside listed absolute maximum ratings cause permanent damage device. This stress rating only, functional operation device these other conditions beyond limits indicated operational sections this specification recommended. Exposure absolute maximum rating conditions extended periods affect device reliability. recommended "power-on" sequence DDCORE voltage supply applied first, followed voltage supply. recommended "power-off" sequence reverse. Remove voltage supply, followed removing VDDCORE voltage supply.
RECOMMENDED OPERATING CONDITIONS SYMBOL DDCORE PARAMETER Supply Voltage Core Supply Voltage LIMITS 0.3V 0.25V
Note: must maintained voltage greater than DDCORE 0.25V.
ELECTRICAL CHARACTERISTICS (VDD 3.3V +0.3; DDCORE 2.5V +0.25; -55°C +125°C) SYMBOL PARAMETER Low-level input voltage CMOS, inputs CONDITION +125 3.3V 0.3V DDCORE 2.5V 0.25V High-level input voltage CMOS inputs +125oC 3.3V DDCORE 2.5V 0.25 Schmitt Trigger, positive going threshold1 +125 3.3V DDCORE 2.5V 0.25 TSchmitt Trigger, negative going threshold1 +125 3.3V DDCORE 2.5V 0.25 Schmitt Trigger, typical range hysterisis2 Input leakage current CMOS Schmitt inputs Inputs with pull-down resistors Inputs with pull-down resistors Inputs with pull-up resistors Inputs with pull-up resistors Cold Spare Inputs Cold Spare Inputs 3.6V -225 0.3V 0.7VDD 0.7VDD 0.3VDD UNIT
SYMBOL
PARAMETER Low-level output voltage CMOS/TTL 4.0mA buffer CMOS/TTL 8.0mA buffer CMOS/TTL 12.0mA buffer CMOS outputs (optional) CMOS outputs (optional)
CONDITION 4.0mA 8.0mA 12.0mA 1.0mA 100.0µA
UNIT
0.05 0.05
High-level output voltage3 CMOS/TTL 4.0mA buffer CMOS/TTL 8.0mA buffer CMOS/TTL 12.0mA buffer CMOS outputs (optional) CMOS outputs (cold spare) Three-state output leakage current CMOS
-3.0mA -5.0mA -7.0mA -1.0mA -100.0µA -0.05 -0.10 3.6V
Cold Spare Inputs Cold Spare Inputs COUT Short-circuit output current CMOS Input capacitance
1MHz 1MHz
Output capacitance 4.0mA buffer 8.0mA buffer 12.0mA buffer
Bidirect capacitance 4.0mA buffer 8.0mA buffer 12.0mA buffer
1MHz
IDDQ
Quiescent Supply Current6 Group subgroups
3.6V 200K gates 400K gates 600K gates 800K gates 1000K gates 1500K gates 2000K gates 2500K gates 3000K gates 3.6V 200K gates 400K gates 600K gates 800K gates 1000K gates 1500K gates 2000K gates 2500K gates 3000K gates 12.5
Group subgroup
Group subgroup Designator:
3.6V 200K gates 400K gates 600K gates 800K gates 1000K gates 1500K gates 2000K gates 2500K gates 3000K gates
Notes: Contact Aeroflex UTMC prior usage. Functional tests conducted accordance with MIL-STD-883 with following input test conditions: (min) 20%, VIL(max) 50%, specified herein, TTL, CMOS, Schmitt compatible inputs. Devices tested using input voltage within above specified range, guaranteed (min) VIL(max). Supplied design limit guaranteed tested. MIL-PRF-38535, current density 5.0E5 amps/cm maximum product load capacitance (per output buffer) times frequency should exceed 3,765pF*MHz. more than output shorted time maximum duration second. Capacitance measured initial qualification when design changes affect value. Capacitance measured between designated terminal frequency 1MHz signal amplitude <50mV RMS. inputs with internal pull-ups should left floating. other inputs should tied high low.
HP/Apollo HP-UX registered trademarks Hewlett-Packard, Inc. Intel registered trademark Intel Corporation Mentor, Mentor Graphics, AutoLogic QuickSim QuickFault QuickHDL, QuickGrade FastScan, FlexTest Advisor registered trademarks Mentor Graphics Corporation registered trademark Microsystems, Inc. Verilog Leapfrog registered trademarks Cadence Design Systems, Inc. Synopsys, Design Compiler, Test Compiler Plus, VHDL Compiler, Verilog Compiler, TestSim trademarks Synopsys, Inc.
Other recent searches
TC58512FTI - TC58512FTI TC58512FTI Datasheet
RN771V - RN771V RN771V Datasheet
QTR3600 - QTR3600 QTR3600 Datasheet
MC68302 - MC68302 MC68302 Datasheet
MB1513 - MB1513 MB1513 Datasheet
JX503 - JX503 JX503 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
