RadHard Schmitt CMOS 16-bit Bidirectional MultiPurpose Voltage Transce
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UT54ACS162245S
RadHard Schmitt CMOS 16-bit Bidirectional MultiPurpose Voltage Transceiver Datasheet
March 2003
FEATURES Voltage translation 3.3V 2.5V 2.5V 3.3V Cold sparing pins 0.25µ Commercial RadHard CMOS Total dose: 300Krad(Si) 1Mrad(Si) Single Event Latchup immune High speed, power consumption Schmitt trigger inputs filter noisy signals Cold Warm Spare outputs Available processes Standard Microcircuit Drawing 5962-02543 Package: 48-lead flatpack, pitch (.390 .640) DESCRIPTION 16-bit wide UT54ACS162245S MultiPurpose voltage transceiver built using Aeroflex UTMC's Commercial RadHard epitaxial CMOS technology ideal space applications. This high speed, power UT54ACS162245S voltage transceiver designed perform multiple functions including: asynchronous two-way communication, Schmitt input buffering, voltage translation, warm cold sparing. With equal zero volts, UT54ACS162245S outputs inputs present minimum impedance making ideal "cold spare" applications. Balanced outputs "on" output impedance make UT54ACS162245S well suited driving high capacitance loads impedance backplanes. UT54ACS162245S enables system designers interface volt CMOS compatible components with volt CMOS components. voltage translation, port interfaces with volt bus; port interfaces with volt bus. direction control (DIRx) controls direction data flow. output enable (OEx) overrides direction control disables both ports. These signals driven from either port direction output enable controls operate these devices either independent 8-bit transceivers 16-bit transceiver. LOGIC SYMBOL
(48) (25) DIR1 2EN1 (BA) 2EN2 (AB) 1EN1 (BA) 1EN2 (AB) (24) DIR2
(47) (46) (44)
(43) (41) (40) (38) (37) (36) (35) (33)
(11) (12) (13) (14) (16) (17) (19) (20)
(32) (30) (29) (27) (26)
(22) (23)
DESCRIPTION
Names DIRx Description Output Enable Input (Active Low) Direction Control Inputs Side Inputs 3-State Outputs (2.5V Port) Side Inputs 3-State Outputs (3.3V Port)
PINOUTS
POWER TABLE
Port Volts Volts Port Volts Volts Volts OPERATION Voltage Translator Translating Translating
48-Lead Flatpack View
DIR1 VDD1 VDD1 DIR2 VDD2 VDD2
Volts
When volts, either volts CMOS logic levels applied control inputs. proper operation connect power ground pins (i.e., floating input pins). unused inputs Always insure during operation part. FUNCTION TABLE
ENABLE DIRECTION DIRx OPERATION Data Data Isolation
COLD/WARM SPARE FUNCTION device will place outputs into high-impedance state either supply taken zero volts warm spare), both supplies zero volts cold spare). DEVICE POWER FUNCTION device will place outputs into high-impedance during power-up. high impedance state maintained time period approximately equal rise time
LOGIC DIAGRAM
DIR1
(48)
DIR2
(24) (25)
(47)
(36) (13)
(46)
(35) (14)
(44)
(33) (16)
PORT
2.5V PORT
2.5V PORT
(41) (40) (38) (11) (37) (12)
(17) (30) (19) (29) (20) (27) (22) (26) (23)
PORT
(43)
(32)
RADIATION HARDNESS SPECIFICATIONS PARAMETER Total Dose Latchup Neutron Fluence (Note
LIMIT 1.0E5 >113 1.0E14
UNITS rad(Si) MeV-cm2 n/cm
Notes: Logic will latchup during radiation exposure within limits defined table. tested, inherent CMOS technology.
ABSOLUTE MAXIMUM RATINGS SYMBOL (Note TSTG (Note PARAMETER Voltage Supply voltage Supply voltage Storage Temperature range Maximum junction temperature Thermal resistance junction case input current Maximum power dissipation LIMIT (Mil only) -0.3 -0.3 +150 +150 UNITS °C/W
Note: Stresses outside listed absolute maximum ratings cause permanent damage device. This stress rating only, functional operation device these other conditions beyond limits indicated operational sections recommended. Exposure absolute maxim rating conditions extended periods affect device reliability performance Cold Spare mode =VSS, =VSS), -0.3V maximum recommended operating level VDD1 +0.3V. Maximum junction temperature increased +175 during burn-in life test.
DUAL SUPPLY OPERATING CONDITIONS SYMBOL PARAMETER Supply voltage Supply voltage Input voltage Temperature range LIMIT VDD1 UNITS
ELECTRICAL CHARACTERISTICS -55°C +125°C) SYMBOL PARAMETER
CONDITION from from from from from
.7VDD
UNIT
Schmitt Trigger, positive going threshold2 Schmitt Trigger, negative going threshold2 Schmitt Trigger range hysteresis9 Schmitt Trigger range hysteresis9 Input leakage current
Three-state output leakage current9
from
Cold sparing input leakage current 3,11
Warm sparing input leakage current3,11
VDD, VDD2 VDD2
Short-circuit output current
from
-200
Short-circuit output current
from
-100
Low-level output voltage9
IOL= IOL= 100µA
Low-level output voltage9
IOL= IOL= 100µA
VOH1
High-level output voltage9
-8mA -100µA
VOH2
High-level output voltage9
-8mA -100µA
ELECTRICAL CHARACTERISTICS -55°C +125°C) SYMBOL total1 PARAMETER Power dissipation
4,6,7
CONDITION 40pF from 3.0V 3.6V
UNIT
total2
Power dissipation 4,6,7
40pF from 2.3V 2.7V
Standby Supply Current VDD2 Pre-Rad Pre-Rad -55oC +125oC Post-Rad 25oC
3.6V 1MHz from 2.3V 3.6V
Input Capacitance
Cout
Output Capacitance
1MHz from 2.3V 3.6V
VDD2 Power-On4,13
VDD1 Zero Volt Offset VDD2 Rise-Time
Notes: specifications valid radiation dose (Si) MIL-STD-883, Method 1019. Functional tests conducted accordance with MIL-STD-883 with following input test conditions: (min) 20%, (max) 50%, specified herein, TTL, CMOS, Schmitt compatible inputs. Devices tested using input voltage within above specified range, guaranteed VIH(min) VIL(max). combinations DIRx Guaranteed characterization. more than output shorted time maximum duration second. Power does include power contribution CMOS output sink current. Power dissipation specified switching output. 8.Capacitance measured initial qualification when design changes affect value. Capacitance measured between designated terminal frequency 1MHz signal amplitude 50mV maximum. 9.Guaranteed; tested sample pins device. Supplied design limit, guaranteed tested. Zero Volts defined Volts 0.25Volts. VDD2 Voltage rise monotonic. Rise time measured from Zero Volts greater than
ELECTRICAL CHARACTERISTICS1 (Port Volt, Port Volt) 3.0V 3.6V; 2.3V 2.7V, -55°C +125°C) SYMBOL tPLH tPHL tPZL tPZH tPLZ tPHZ tPZL2 tPZH tPLZ2 tPHZ tSLH tSHL PARAMETER Propagation delay Data Propagation delay Data Output enable time Output enable time Output disable time high impedance Output disable time high impedance Output enable time DIRx Output enable time DIRx Output disable time DIRx high impedance Output disable time DIRx high impedance Skew between outputs (40pF each output) Skew between outputs (40pF each output) MINIMUM MAXIMUM UNIT
Notes: specifications valid radiation dose rad(Si) MIL-STD-883, Method 1019. DIRx times guaranteed design, tested. times tested Output skew defined comparison output transitions high-to-low high-to-low low-to-high low-to-h
Propagation Delay Input Output
tPLH tPHL
Enable Disable Times Control Input 3.3V Output Normally 3.3V Output Normally High 2.5V Output Normally 2.5V Output Normally High
tPZL /2-0.2 tPZH /2+0.2 tPLZ .2VDD tPHZ .8VDD tPLZ DD/2-0.2 tPZH /2+0.2
DD/2 DD/2
tPZL
.2VDD tPHZ
ELECTRICAL CHARACTERISTICS (Port Port Volt Operation) 3.6V; 3.0V 3.6V, -55°C +125°C) SYMBOL tPLH tPHL tPZL tPZH tPLZ tPHZ tPZL tPZH2 tPLZ tPHZ2 tSLH3 tSHL3 PARAMETER Propagation delay Data Propagation delay Data Output enable time Output enable time Output disable time high impedance Output disable time high impedance Output enable time DIRx Output enable time DIRx Output disable time DIRx high impedance Output disable time DIRx high impedance Skew between outputs (40pF each output) MINIMUM MAXIMUM UNIT
Skew between outputs (40pF each output)
Notes: specifications valid radiation dose rad(Si) MIL-STD-883, Method 1019. DIRx times guaranteed design, tested. times tested Output skew defined comparison output transitions high-to-low high-to-low low-to-high low-to-high
Propagation Delay Input Output
tPLH tPHL
DD/2 DD/2
Enable Disable Times Control Input 3.3V Output Normally 3.3V Output Normally High
tPZL DD/2-0.2 tPZH DD/2+0.2 tPLZ .2VDD tPHZ .8VDD
DD/2 DD/2 DD/2
ELECTRICAL CHARACTERISTICS1 (Port Port Volt Operation) 2.3V 2.7V; VDD2 2.3V 2.7V, -55°C +125°C) SYMBOL tPLH tPHL tPZL tPZH tPLZ tPHZ tPZL2 tPZH tPLZ2 tPHZ tSLH tSHL PARAMETER Propagation delay Data Propagation delay Data Output enable time Output enable time Output disable time high impedance Output disable time high impedance Output enable time DIRx Output enable time DIRx Output disable time DIRx high impedance Output disable time DIRx high impedance Skew between outputs (40pF each output) MINIMUM MAXIMUM UNIT
Skew between outputs (40pF each output)
Notes: specifications valid radiation dose rad(Si) MIL-STD-883, Method 1019. DIRx times guaranteed design, tested. times tested Output skew defined comparison output transitions high-to-low high-to-low low-to-high low-to-h
Propagation Delay Input Output
tPLH tPHL
DD/2 DD/2
Enable Disable Times Control Input 2.5V Output Normally 2.5V Output Normally High
tPZL DD/2-0.2 tPZH DD/2+0.2 tPLZ tPHZ .7VDD DD/2 DD/2 .7VDD DD/2
PACKAGE
exposed metalized areas gold plated over electroplated nickel MIL-PRF-38535. electrically connected VSS. Lead finishes accordance with MIL-PRF-38535. Lead position colanarity measured. mark symbol vendor option. With solder, increase maximum 0.003.
Figure 48-Lead Flatpack
ORDERING INFORMATION
UT54ACS162245S:
5962
02543
Lead Finish: Gold Solder
Case Outline: lead
Class Designator: Class Class Device Type (01) 16-bit MultiPurpose Voltage ransceiver
Drawing Number: 02543 Total Dose: rad(Si) rad(Si) rad(Si) rad(Si) Federal Stock Class Designator
Notes: Total dose radiation must specified when ordering. available without radiation hardening.
UT54ACS162245S
UT54 ******
Lead Finish: Gold
Solder
Screening: Temp Prototype
Package Type: 48-lead
Part Number: (16225SLV) 16-bit MultiPurpose Voltage Transceiver
Type: (ACS)= CMOS compatible Level
UTMC Core Part Number
Notes: Military Temperature Range flow UTMC Manufacturing Flows Document. Devices tested -55C, room temp, 125C. Radiation either tested guaranteed. Prototype flow UTMC Manufacturing Flows Document Tested only. Lead finish gold only.
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