PRODUCT PRELIMINARY CMOS 2-WIRE 128K/256K ELECTRICALLY ERASABLE P

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PRODUCT PRELIMINARY CMOS 2-WIRE 128K/256K ELECTRICALLY ERASABLE P

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24C128/24C256
PRODUCT PRELIMINARY
CMOS 2-WIRE 128K/256K ELECTRICALLY ERASABLE PROGRAMMABLE 16K/32K EEPROM
FEATURES Extended Power Supply Voltage Single Read Programming (Vcc Power (Isb Extended Bus, 2-Wire Serial Interface Support Byte Write Page Write Bytes) Automatic Page write Operation (maximum Internal Control Timer Internal Data Latches Bytes Hardware Data Protection Write Protect High Reliability CMOS Technology EEPROM Cell Endurance 1,000,000 Cycles Data Retention Years JDEC wide PDIP wide SOIC packages DESCRIPTION: Turbo 24C128/24C256 serial 128K/256K EEPROM fabricated with Turbo's proprietary, high reliability, high performance CMOS technology. It's 128K/256K memory organized 16384/32768 bits. memory configured 256/512 pages with each page containing bytes. This device offers significant advantages power voltage applications. Turbo 24C128/24C256 uses extended addressing protocol 2-wire serial interface which includes bidirectional serial data synchronized clock. offers flexible byte write faster 64-byte page write. entire memory protected write protect pin. Turbo 24C128/24C256 assembled either 8pin PDIP 8-pin SOIC package. (A0), (A1), (A2) device address input pins which hardwired user. ground (Vss). serial data (SDA) used bidirectional transfer data. serial clock (SCL) input pin. write protect (WP) input pin, power supply (Vcc) pin. data serially transmitted bytes bits) bus. access Turbo 24C128/24C256 (slave) read write operation, controller (master) issues start condition pulling from high while high. master then issues device address byte which consists 1010 (A2) (A1) (A0) (R/W). most significant bits (1010) device type code signifying EEPROM device. A[2:0] bits represent input levels device address input pins. read/write determines whether read write operation. After each byte transmitted, receiver provide acknowledge pulling ninth clock cycle. acknowledge handshake signal transmitter indicating successful data transmission.
must connected from Vcc. SERIAL CLOCK (SCL) input synchronizes data bus. used conjunction with define start stop conditions. also used conjunction with transfer data from Turbo 24C128/24C256.
DESCRIPTION
SOIC
PDIP
DESCRIPTION DEVICE ADDRESSES (A2-A0) address inputs used define least significant bits 7-bit device address code 1010 (A2) (A1) (A0). These pins connected either high low. maximum eight Turbo 24C128/24C256 connected parallel, each with unique device address. When these pins left unconnected, device addresses interpreted zero.
WRITE PROTECT (WP) When write protect input connected Vcc, entire memory protected against write operations. normal write operation, write protect should grounded. When this left unconnected, interpreted zero. SERIAL DATA (SDA) bidirectional used transfer data Turbo 24C128/24C256. open-drain output. pull-up resistor
24C128/24C256
PRODUCT PRELIMINARY DESCRIPTION (Continued) write operation, master issues start condition, device address byte, memory address bytes, then data bytes. Turbo 24C128/24C256 acknowledges after each byte transmission. terminate transmission, master issues stop condition pulling from high while high.
DEVICE OPERATION: BIDIRECTIONAL PROTOCOL: Turbo 24C128/24C256 follows extended protocol. protocol defines device that sends data onto transmitter, receiving device receiver. device controlling transfer master device being controlled slave. master always initiates data transfers, provides clock both transmit receive operations. Turbo 24C128/ 24C256 acts slave device applications. Either master slave take control bus, depending requirement protocol. START/STOP CONDITION DATA TRANSITIONS: While clock high, high transition recognized START condition which precedes read write operation. While clock high, high transition recognized STOP condition which terminates communication places Turbo 24C128/24C256 into standby mode. other data transitions must occur while clock ensure proper operation.
read operation, master issues start condition device address byte. Turbo 24C128/24C256 acknowledges, then transmits data byte, which accessed from EEPROM memory. master acknowledges, indicating that requires more data bytes. Turbo 24C128/24C256 transmits more data bytes, with memory address counter automatically incrementing each data byte, until master does acknowledge, indicating that terminating transmission. master then issues stop condition. ACKNOWLEDGE: data serially transmitted bytes bits) bus. acknowledge protocol used handshake signal indicate successful transmission byte data. transmitter, either master slave (Turbo 24C128/24C256), releases after sending byte data bus. receiver pulls during ninth clock cycle acknowledge successful transmission byte data. pulled during ninth clock cycle, Turbo 24C128/24C256 terminates data transmission goes into standby mode. write operation, Turbo 24C128/24C256 acknowledges after device address byte, acknowledges after each memory address byte, acknowledges after each subsequent data byte. read operation, Turbo 24C128/24C256 acknowledges after device address byte. Then Turbo 24C128/24C256 transmits each subsequent data byte, master acknowledges after each data byte transfer, indicating that requires more data bytes. Turbo 24C128/ 24C256 monitors acknowledge. terminate transmission, master does acknowledge, then sends stop condition.
Write Cycle Timing
WORD
STOP CONDITION
START CONDITION
Note: write cycle time time from valid stop condition write sequence internal clear write cycle.
24C128/24C256
PRODUCT PRELIMINARY Data Valid
DATA STABLE DATA STABLE DATA CHANGE
Start Stop Definition
START STOP
Output Acknowledge
DATA DATA
START ACKNOWLEDGE
24C128/24C256
DEVICE ADDRESSING: Following start condition, master will issue device address byte consisting 1010 (A2) (A1) (A0) (R/W) access selected Turbo 24C128/24C256 read write operation. A[2:0] bits must match with address input pins selected Turbo 24C128/24C256. there match, selected Turbo 24C128/24C256 acknowledges during ninth clock cycle pulling low. there match, Turbo 24C128/24C256 does acknowledge during ninth clock cycle goes into standby mode. (R/W) high read write. DATA INPUT DURING WRITE OPERATION: During write operation, Turbo 24C128/24C256 latches signal rising edge clock. DATA OUTPUT DURING READ OPERATION: During read operation, Turbo 24C128/24C256 serially shifts data onto falling edge clock. MEMORY ADDRESSING: memory address sent master form memory address bytes. memory address bytes only sent part write operation. most significant address byte B(14) B(13) (B12) (B11) (B10) (B9) (B8) sent first, where B(14) "don't care" 24C128. Then least significant address byte (B7) (B6) (B5) (B4) (B3) (B2) (B1) (B0) sent last. BYTE WRITE OPERATION: master initiates byte write operation issuing start condition, followed device address byte 1010 (A2) (A1) (A0) followed memory address bytes, followed data byte, then stop condition. After each byte transfer, Turbo 24C128/24C256 acknowledges successful data transmission pulling low. stop condition starts internal EEPROM write cycle, inputs disabled until completion write cycle. high, then stop condition does start internal write cycle Turbo 24C128/24C256 immediately ready next command. PAGE WRITE OPERATION: master initiates page write operation issuing start condition, followed device address byte 1010 (A2) (A1) (A0) followed memory address bytes, followed data bytes, then stop condition. After each byte transfer, Turbo 24C128/24C256 acknowledges successful data transmission pulling low. After each data byte transfer, PRODUCT PRELIMINARY memory address counter automatically incremented one. stop condition starts internal EEPROM write cycle only stop condition occurs clock cycle immediately following acknowledge (10th clock cycle). inputs disabled until completion write cycle. high (1), then stop condition does start internal write cycle, Turbo 24C128/24C256 immediately ready next command. POLLING ACKNOWLEDGE: During internal write cycle write operation Turbo 24C128/24C256, completion write cycle detected polling acknowledge. master starts acknowledge polling issuing start condition, then followed device address byte 1010 (A2) (A1) (A0) internal write cycle finished, Turbo 24C128/24C256 acknowledges pulling low. internal write cycle still ongoing, Turbo 24C128/24C256 does acknowledge because it's inputs disabled. Therefore, device will respond command. using polling acknowledge, system delay write operations reduced. Otherwise, system needs wait maximum internal write cycle time, tWC, given spec. POWER RESET: Turbo 24C128/24C256 Power Reset circuit (POR) prevent data corruption accidental write operations during power power internal reset signal Turbo 24C128/24C256 will respond command until voltage reached threshold value.
24C128/24C256
Device Address PRODUCT PRELIMINARY
Byte Write
LINE
DEVICE ADDRESS
FIRST WORD ADDRESS
SECOND WORD ADDRESS
DATA
256K 128K
Page Write
LINE
DEVICE ADDRESS
FIRST SECOND WORD ADDRESS WORD ADDRESS 256K 128K
DATA
DATA
Don't care bits Don't care 24C128
24C128/24C256
PRODUCT PRELIMINARY CURRENT ADDRESS READ: internal memory address counter Turbo 24C128/ 24C256 contains last memory address accessed during previous read write operation, incremented one. start current address read operation, master issues start condition, followed device address byte 1010 (A2) (A1) (A0) Turbo 24C128/24C256 responds with acknowledge pulling low, then serially shifts data byte accessed from memory location corresponding memory address counter. master does acknowledge, then sends stop condition terminate read operation. noted that memory address counter incremented after data byte shifted out. RANDOM ADDRESS READ: master starts with dummy write operation (one with data bytes) load internal memory address counter first issuing start condition, followed device address byte 1010 (A2) (A1) (A0) followed memory address bytes. Following acknowledge from Turbo 24C128/24C256, master starts current read operation issuing start condition, followed device address byte 1010 (A2) (A1) (A0) Turbo 24C128/ 24C256 responds with Current Address Read
LINE
acknowledge pulling low, then serially shifts data byte accessed from memory location corresponding memory address counter. master does acknowledge, then sends stop condition terminate read operation. noted that memory address counter incremented after data byte shifted out. SEQUENTIAL READ: sequential read initiated either current address read random address read. After Turbo 24C128/ 24C256 serially shifts first data byte, master acknowledges pulling low, indicating that requires additional data bytes. After data byte shifted out, Turbo 24C128/24C256 increments memory address counter one. Then Turbo 24C128/24C256 shifts next data byte. sequential reads continues long master keeps acknowledging. When memory address counter last memory location, counter will `roll-over' when incremented first location memory (address zero). master terminates sequential read operation acknowledging, then sends stop condition.
DEVICE ADDRESS
DATA
Random Read
LINE
DEVICE ADDRESS
WORD ADDRESS
DEVICE ADDRESS
DATA
DUMMY WRITE
24C128/24C256
PRODUCT PRELIMINARY
Sequential Read
LINE
DEVICE ADDRESS
DATA
DATA
DATA
DATA
ABSOLUTE MAXIMUM RATINGS TEMPERATURE Storage: Under Bias: -65° 150° -55° 125°
RECOMMENDED OPERATING CONDITIONS Temperature Range: Supply Voltage: Endurance: Data Retention: Commercial: Volts 1,000,000 Cycles/Byte (Typical) Years
INPUT OUTPUT VOLTAGES with respect -0.3 "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operation section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
D.C. CHARACTERISTICS Symbol Icc1 Icc2 Vol2 Vol1 Parameter Active Current Active Current Standby Current Input Leakage Current Output Leakage Current Input Voltage Input High Voltage Output Output Condition READ WRITE Vin=Vcc Vcc+0.5 0.25 Units
-1.0 Vcc=3.0v Iol=2.1 Vcc=2.7v Iol=-0.15
24C128/24C256
Timing
HIGH
PRODUCT PRELIMINARY
SU.STA
HD.DAT HD.STA
SU.DAT
SU.STO
A.C. CHARACTERISTICS
Symbol
Parameter
volt
volt 1000
Units
tLOW tHIGH tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tSU.STO
Clock Frequency Clock Period Clock High Period Data Free Start Start Hold Time Start Setup Time Data-in Hold Time Data-in Set-up Time Rise Time Fall Time Stop Setup Time Data-out Hold Time Write Cycle Time
0.55 0.25 0.25 0.25
Note: This parameter characterized 100% tested.
TURBO PRODUCTS DOCUMENTS
documents subject change without notice. Please contact Turbo latest revision documents. Turbo does assume responsibility damage user that result from accidents operation under abnormal conditions. Turbo does assume responsibility circuitry other than what embodied Turbo product. other circuits, patents, licenses implied. Turbo products authorized life support systems other critical systems where component failure endanger life. System designers should design with error detection correction, redundancy backup features.
Part Numbers Order Information TU24C128/256CP3
Revision 16/32K Serial EEPROM Package -PDIP -SOIC Operating Voltage
Turbo Inc. 2365 Paragon Drive, Suite Jose, 95131 Phone: 408-392-0208 Fax: 408-392-0207 www.turbo-ic.com
Rev. 11/27/02

PRODUCT PRELIMINARY CMOS 2-WIRE 128K/256K ELECTRICALLY ERASABLE P

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