PRODUCT INTRODUCTION HIGH SPEED CMOS Megabit PROGRAMMABLE ERASABL

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PRODUCT INTRODUCTION HIGH SPEED CMOS Megabit PROGRAMMABLE ERASABL

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29C512
PRODUCT INTRODUCTION
HIGH SPEED CMOS Megabit PROGRAMMABLE ERASABLE FLASH PEROM
FEATURES: Access Time Volt Only Reprogramming Sector Program Operation Single Cycle Reprogram (Erase Program) Sectors (128 bytes/sector) Internal Address Data Latches Bytes Automatic Sector Programming Operation Internal Control Timer Fast Program Times Page Program Cycles: Typical Time Rewrite Complete Memory: Typical Byte Program Cycle Time: Software Data Protection Power Dissipation Active Current CMOS Standby Current Direct Microprocessor Program Detection Data Polling High Reliability CMOS Technology Endurance: 10,000 Cycles Data Retention: years CMOS Compatible Inputs Outputs Single Power Supply Read Programming Operations JEDEC Approved Byte Pinout DESCRIPTION: Turbo 29C512 Flash programmable erasable read only memory (PEROM) fabricated with Turbo IC's proprietary, high reliability, high performance CMOS technology. 512K bits memory organized bits. device offers access time with power dissipation below 29C512 bytes sector program operation enabling entire memory programmed typically less than seconds. During program operation, address complete sector (128 bytes) data internally latched, freeing address data other microprocessor operations. programming process automatically controlled device using internal control timer. Data polling I/O7 Toggle used detect programming cycle. addition, 29C512 includes user-optional software data write mode offering additional protection against unwanted (false) write. 29C512 does require separate high voltage program device. volts that required.
CONFIGURATIONS:
3029 I/O7 I/O0 I/O1 I/O4 I/O6 I/O0 I/O1 I/O2 I/O7 I/O6 I/O5 I/O4 I/O3
I/O6 I/O4 I/O1
I/O7 I/O5 I/O3 I/O2 I/O0
I/O2
I/O3
I/O5
pins TSOP
pins PLCC
pins PDIP
29C512
PRODUCT INTRODUCTION
DESCRIPTION
ADDRESSES A15) Addresses used select bits memory location during program read operation. CHIP ENABLE (CE) Chip Enable input must enable read/program operations device. setting high, device disabled power consumption extremely with standby current below
OUTPUT ENABLE (OE) Output Enable input activates output buffers during read operations. WRITE ENABLE (WE) Write Enable input initiates programming data into memory. DATA INPUT/OUTPUT (I/O0-I/O7) Data Input/Output pins used read data memory program Data into memory.
DEVICE OPERATION
READ 29C512 accessed like static RAM. Read operations initiated both terminated either returning high. outputs high impedance state whenever returns high. line control architecture gives designers flexibility preventing contention. PROGRAM HARDWARE DATA PROTECTION program cycle initiated when high. address latched internally falling edge whichever occurs last. data latched rising edge whichever occurs first. Once programming cycle been started, internal timer automatically generates program sequence completion program operation. SECTOR PROGRAM OPERATION device reprogrammed sector basis. When byte data within sector changed, data entire sector must loaded into device. byte that loaded during programming sector will erased read FFh. programming operation 29C512 allows bytes data serially loaded into device then simultaneously written into memory during internally generated program cycle. After first byte been loaded, successive bytes data must loaded until full sector bytes loaded. Each byte written must loaded within previously loaded byte. sector address defined addresses latched first falling edge which initiates program cycle they stay latched until completion program cycle. changes sector addresses during load-program cycle will affect initially latched sector address. Addresses used define which bytes will loaded within bytes sector. bytes loaded order that convenient user. content loaded byte altered time during loading cycle maximum allowed byte-load time (300 exceeded. bytes page serially loaded programmed single program cycle DATA POLLING 29C512 features DATA Polling indicate completion program cycle host system. During program cycle, attempted read last byte loaded into page will result complement loaded byte I/O7, i.e., loaded would read Once program cycle been completed, true data valid outputs next cycle started. DATA Polling begin time during programming cycle. 29C512 three hardware features protect written content memory against inadvertent programming: threshold detector below program capabilities chip inhibited whatever input conditions. Noise protection pulse less than width able initiate program cycle. Write inhibit Holding low, high, high inhibits program cycle. SOFTWARE DATA PROTECTION 29C512 offers software controlled data program protection feature. device delivered user with software data protection DISABLED, i.e., device will program operation long exceeds inputs program mode levels. 29C512 automatically protected against accidental write operation during power-up power-down without external circuitry enabling software data protection feature. This feature enable after first program cycle which includes software algorithm. After this operation done program function device performed only every program cycle preceded software algorithm. device will maintain software protect feature rest life, unless software algorithm disabling protection implemented. TOGGLE addition DATA Polling 29C512 provides another method determining programming erase cycle. During program erase operation, successive attempts read data from device will result I/O6 toggling between zero. Once program cycle completed, I/O6 will stop toggling valid data will read. Examining toggle begin time during program cycle.
29C512
SOFTWARE ALGORITHM 29C512 internal register software algorithm which enables memory provide user with additional features: Software Data Protect Enable sequence three dummy data writes memory will activate internal EEPROM fuses during first page write cycle. These EEPROM fuses will reject write attempts pages data, unless three dummy data writes repeated beginning page writes. timing dummy data addresses must same normal program operation. violation three steps program protect sequence data address timing content will abort procedure reset device starting point condition. Note: Software data protect enable procedure must performed part standard program cycle. additional page data added three dummy data writes, software data protect enable procedure will aborted. data protect state will activated program cycle. bytes data must loaded during Software Data Protection Enable cycle. Table shows required procedure enabling software data protect: TABLE ADD.A14-A0 5555 2AAA 5555 Address STEP MODE Page Write Page Write Page Write Page Write Page Write Page Write TABLE ADD.A14-A0 5555 2AAA 5555 5555 2AAA 5555 DATA Software Chip Clear (optional) software algorithm 29C512 includes sequence step dummy data writing perform chip clear operation. Table shows step write sequence perform software chip clear operation:
step program sequence shown Table device automatically activates internal timer control chip erase cycle; typically takes msec. After software chip clear operation been completed, 512K locations memory show high level read operation mode.
STEP 4-131
MODE Page Write Page Write Page Write Page Write
DATA Sector Data (128 Bytes)
Software Data Protect Disable software algorithm 29C512 includes step sequence dummy data programming sequence disable software data protect feature described step sequence shown Table must performed beginning program cycle. violation step program sequence data address timing content will abort procedure reset chip starting point condition. After software data protect disable cycle including step sequence been performed, 29C512 does require three dummy loads described following program cycle. device software data protect disabled state. Note: When step sequence software data protect disable procedure performed, additional bytes data added after six-step write sequence, software data protect disable procedure will aborted. data protect state will deactivated program period. bytes data must loaded during Software Data Protection disable cycle. Table shows required procedure disabling software data protect: TABLE ADD.A14-A0 5555 2AAA 5555 5555 2AAA 5555 Address
STEP 7-134
MODE Page Write Page Write Page Write Page Write Page Write Page Write Page Write
DATA Sector Data (128 Bytes)
29C512
PRODUCT INTRODUCTION
COMMERCIAL INDUSTRIAL MILITARY
ABSOLUTE MAXIMUM STRESS RANGES TEMPERATURE Storage: Under Bias: -65° 150° -55° 125°
D.C. CHARACTERISTICS Symbol Parameter Condition Active Current
Units
INPUT OUTPUT VOLTAGES with respect -0.3 "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operation section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Range: Commercial: Industrial: -40°
Isb1
Isb2
CMOS Standby Current Standby CE=Vih, OE=Vil, Current Open, Other Inputs=Vcc Input Leakage Current Output Leakage Current Input Voltage Input High Voltage Output Voltage Output High Voltage Vin=Vcc
CE=OE=Vil; Open, Read Write Cycle Time CE=Vcc-0.3 Vcc+1
Supply Voltage: Endurance: Data Retention: 10,000 Cycles/Byte (Typical) Years A.C. CHARACTERISTICS READ OPERATION
29C5121 29C512-2 29C512-3
-0.1
-0.8
Vcc+0.3 Iol=2.1 Ioh=-0.45 0.45
Symbol tacc
Parameters Address Output Delay Output Delay Output Output High Output Hold from Address Changes, Chip Enable Output Enable Whichever Occurs First
Unit A.C. TEST CONDITIONS Output Load Load Cl=100 Input Rise Fall Times Input Pulse Level 0.45 2.4V
A.C. Read Wave Forms
ADDRESS ADDRESS VALID tacc OUTPUT HIGH-Z OUTPUT VALID HIGH-Z
29C512
A.C. WRITE CHARACTERISTICS Symbol toes toeh tblc Parameter Address Set-up Time Address Hold Time Write Set-up Time Write Hold Time Pulse Width Pulse Width Set-up Time Hold Time Data Set-up Time Data Hold Time Byte Load Cycle Last Byte Loaded Data Polling Output Write Cycle Time Units
A.C. Write Wave Forms WE-Controlled
toes
toeh
ADDRESS
VALID
DATA HIGH-Z tblc HIGH-Z
DATA VALID
A.C. Write Wave Forms CE-Controlled
toes ADDRESS VALID toeh
DATA HIGH-Z tblc HIGH-Z
DATA VALID
29C512
PRODUCT INTRODUCTION
PAGE MODE WRITE CHARACTERISTICS Symbol tblc twph Parameter Write Cycle Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Write Pulse Width Byte Load Cycle Time Write Pulse Width High Unit
Page Mode Write Wave Forms (1,2,3)
twph A0-A6
BYTE ADDRESS
A7-A15
SECTOR ADDRESS
DATA BYTE-0 BYTE-1 BYTE-2 BYTE- BYTE-127
Note: through must specify sector address during each high transition must high when both low. bytes that loaded within sector being programmed will erased
29C512
DATA Polling Characteristics Symbol toeh Parameter Data Hold Time Hold Time Output Delay Write Recovery Time Unit
Note: Specification Characteristics Read Operation
DATA Polling Wave Forms
toeh I/O7 HIGH A0-A15
Toggle Characteristics Symbol toeh toeh Parameter Data Hold Time Hold Time Output Delay High Pulse Unit
Note: Specification Characteristics Read Operation
Toggle Wave Forms (1,2,3)
I/O6 toeh HIGH
Note: Toggling either both will operate toggle bit. Beginning ending state I/O6 will vary. address location used address should vary.
29C512
PRODUCT INTRODUCTION
TURBO PRODUCTS DOCUMENTS
documents subject change without notice. Please contact Turbo latest revision documents. Turbo does assume responsibility damage user that result from accidents operation under abnormal conditions. Turbo does assume responsibility circuitry other than what embodied Turbo product. other circuits, patents, licenses implied. Turbo products authorized life support systems other critical systems where component failure endanger life. System designers should design with error detection correction, redundancy back-up features.
Part Numbers Order Information 29C512PC-2
PEROM
Package -PLCC -PDIP -TSOP
Temperature -Commercial -Industrial
Speed
Turbo Inc. 2153 O'Toole Ave., Suite Jose, 95131 Phone: 408-324-0288 Fax: 408-324-0289 www.turbo-ic.com
Rev. 2.0-8/8/97

PRODUCT INTRODUCTION HIGH SPEED CMOS Megabit PROGRAMMABLE ERASABL

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