Literature Number: SPRS231B December 2003 Revised March 2004 PROD

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OMAP5912 Applications Processor
Literature Number: SPRS231B December 2003 Revised March 2004
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
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Revision History
REVISION HISTORY
This data sheet revision history highlights technical changes made SPRS231A generate SPRS231B. Scope: SPRS231B only revision this document that been released.
PAGE(S)
ADDITIONS/CHANGES/DELETIONS Updated Table 3-56, Initiator Registers Table 3-57, Interface (MPUI) Registers: updated RESET VALUE column FFFE:C91C changed REGISTER NAME DESCRIPTION added DSP_MISC_CONFIG (FFFE:C920) added ENHANCED_CTL (FFFE:C924) Table 3-65, Registers: changed ACCESS WIDTH registers from bits bits Table 3-71, Timer1 Registers: updated WORD ADDRESS column Table 3-72, Timer2 Registers: updated WORD ADDRESS column Table 3-73, Timer3 Registers: updated WORD ADDRESS column Updated Table 3-74, Watchdog Timer Registers Updated Table 3-78, TIPB Bridge Configuration Registers Updated Table 3-81, Clock Mode Registers Updated Table 3-82, TIPB Switch Registers
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SPRS231B
Revision History
SPRS231B
December 2003 Revised March 2004
Contents
Contents
Section OMAP5912 Features Page
Introduction Description 2.1.1 TMS320C55x Core 2.1.2 ARM926EJ-S RISC Processor Terminal Assignments Terminal Characteristics Multiplexing Signal Description
Functional Overview Functional Block Diagram Features Memory Maps 3.2.1 Global Memory 3.2.2 Subsystem Registers Memory Memory Maps 3.3.1 Global Memory 3.3.2 On-Chip Dual-Access (DARAM) 3.3.3 On-Chip Single-Access (SARAM) 3.3.4 Space Memory External Memory (Managed MMU) Private Peripherals 3.5.1 Timers 3.5.2 Watchdog Timer 3.5.3 Interrupt Handlers 3.5.4 CompactFlash Controller (MPU Only) 3.5.5 Controller (MPU Only) 3.5.6 LCDCONV (MPU Only) 3.5.7 Random Number Generator (RNG) 3.5.8 DES/3DES 3.5.9 SHA1/MD5 Public Peripherals 3.6.1 Interface 3.6.2 Display Interface SoSSI 3.6.3 Camera Interface 3.6.4 Compact Camera Port (CCP) 3.6.5 MICROWIRE Serial Interface 3.6.6 Real-Time Clock (RTC) 3.6.7 Pulse-Width Tone (PWT) 3.6.8 Pulse-Width Light (PWL) 3.6.9 Keyboard Interface 3.6.10 HDQ/1-Wire Interface 3.6.11 Multimedia Card/Secure Digital (MMC/SDIO1) Interface 3.6.12 MPUIO Interface
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SPRS231B
Contents
Section 3.6.13 Pulse Generators (LPG) 3.6.14 Frame Adjustment Counter (FAC) 3.6.15 Operating System (OS) Timer Public Peripherals 3.7.1 Multichannel Buffered Serial Ports (McBSP1 3.7.2 Multichannel Serial Interfaces (MCSI1 Shared Peripherals 3.8.1 Mailboxes 3.8.2 General-Purpose Timers 3.8.3 Serial Port Interface (SPI) 3.8.4 Universal Asynchronous Receiver/Transmitter (UART) 3.8.5 Master/Slave Interface 3.8.6 Multichannel Buffered Serial Port (McBSP2) 3.8.7 Multimedia Card/Secure Digital (MMC/SDIO2) Interface 3.8.8 General-Purpose (GPIO) 3.8.9 32-kHz Synchro Counter 3.8.10 VLYNQ Interface System Controller Controller Traffic Controller (Memory Interfaces) Interprocessor Communication 3.12.1 MPU/DSP Mailbox Registers 3.12.2 Interface (MPUI) 3.12.3 MPU/DSP Shared Memory Hardware Accelerators 3.13.1 DCT/iDCT Accelerator 3.13.2 Motion Estimation Accelerator 3.13.3 Pixel Interpolation Accelerator Power Supply Connection Examples 3.14.1 Core Voltage Supply Connections 3.14.2 Core Voltage Noise Isolation
Page
3.10 3.11 3.12
3.13
3.14
Documentation Support Device Development-Support Tool Nomenclature
Electrical Specifications Absolute Maximum Ratings Recommended Operating Conditions Electrical Characteristics Over Recommended Operating Ambient Temperature Range Package Thermal Resistance Characteristics Timing Parameter Symbology Clock Specifications 5.6.1 32-kHz Oscillator Input Clock 5.6.2 Base Oscillator (12, 19.2 MHz) Input Clock
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Contents
Section Reset Timings 5.7.1 OMAP5912 Device Reset 5.7.2 OMAP5912 Core Reset External Memory Interface Timing 5.8.1 EMIFS/Flash Interface Timing 5.8.2 EMIFS/Multiplexed Flash Interface Timings 5.8.3 EMIFS/NAND Flash Timings CompactFlash Interface Timings EMIFF/SDR SDRAM Interface Timing EMIFF/DDR SDRAM Interface Timing Multichannel Buffered Serial Port (McBSP) Timings 5.12.1 McBSP Transmit Receive Timings 5.12.2 McBSP Master Slave Timings Multichannel Serial Interface (MCSI) Serial Port Interface (SPI) Timings VLYNQ Interface Timings 5.15.1 VLYNQ Slave Mode (External Clock Source) 5.15.2 VLYNQ Master Mode (Internal Clock Source) Parallel Camera Interface Timings Compact Serial Camera Port (CCP) Timings Controller LCDCONV Interface Timings SoSSI Display Interface Timings Multimedia Card/Secure Digital (MMC/SD) Timings Timings Universal Serial (USB) Timings MICROWIRE Interface Timings HDQ/1-Wire Interface Timings Embedded Trace Macrocell (ETM) Interface
Page
5.10 5.11 5.12
5.13 5.14 5.15
5.16 5.17 5.18 5.19 5.20 5.21 5.22 5.23 5.24 5.25
Glossary
Mechanical Data Ball Grid Array Mechanical Data
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SPRS231B
Figures
List Figures
Figure OMAP5912 289-Ball Plastic Ball Grid Array (Bottom View) OMAP5912 289-Ball Plastic Ball Grid Array (Bottom View) Page
OMAP5912 Functional Block Diagram Supply Connections Typical System External Circuits Noise Isolation
5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 5-28 5-29
3.3-V Test Load Circuit 32-kHz Oscillator External Crystal 32-kHz Oscillator External Crystal With PI-Network 32-kHz Input Clock Internal System Oscillator External Crystal Device Reset Timings Core Reset Timings EMIFS/NOR Flash Asynchronous Memory Read Timing EMIFS/NOR Flash Asynchronous 32-Bit Read EMIFS/NOR Flash Asynchronous Read Page Mode EMIFS/NOR Flash Asynchronous Memory Write Timing EMIFS/NOR Flash Synchronous Burst Read EMIFS/MUX Flash Single Word Asynchronous Read EMIFS/MUX Flash Single Word Asynchronous Write EMIFS/MUX Flash Synchronous Four-Word Burst Read EMIFS/NAND Flash Command Latch Timing EMIFS/NAND Flash Address Latch Timing EMIFS/NAND Flash Memory Write Timing EMIFS/NAND Flash Memory Read Timing CompactFlash Attribute Memory Mode Read Timing CompactFlash Attribute Memory Mode Write Timing CompactFlash Common Memory Mode Read Timing CompactFlash Common Memory Mode Write Timing CompactFlash Mode Read Timing CompactFlash Mode Write Timing EMIFF/SDR SDRAM (Read) Commands (Active Row) EMIFF/SDR SDRAM (Write) Commands (Active Row) EMIFF/SDR SDRAM ACTV (Active Row) Command EMIFF/SDR SDRAM DCAB (Precharge/Deactivate Row) Command
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Figures
Figure 5-30 5-31 5-32 5-33 5-34 5-35 5-36 5-37 5-38 5-39 5-40 5-41 5-42 5-43 5-44 5-45 5-46 5-47 5-48 5-49 5-50 5-51 5-52 5-53 5-54 5-55 5-56 5-57 5-58 5-59 5-60 5-61 5-62 5-63 5-64 5-65 EMIFF/SDR SDRAM REFR (Refresh) Command EMIFF/SDR SDRAM (Mode Register Set) Command EMIFF/DDR SDRAM Command Address Output Timing Definition EMIFF/DDR SDRAM Memory Read Timing EMIFF/DDR SDRAM Memory Write Timing McBSP Receive Timings McBSP Transmit Timings McBSP Timings Master Slave: CLKSTP 10b, CLKXP McBSP Timings Master Slave: CLKSTP 11b, CLKXP McBSP Timings Master Slave: CLKSTP 10b, CLKXP McBSP Timings Master Slave: CLKSTP 11b, CLKXP MCSI Master Mode Timings MCSI Slave Mode Timings Interface Transmit Receive Master Slave Timings VLYNQ Transmit Receive Timings, Slave Master Mode Camera Interface Timings Interface Timing Mode (LCD.HS/LCD.VS Falling LCD.Px Rising LCD.PCLK) Mode (LCD.HS/LCD.VS Rising LCD.Px Falling LCD.PCLK) SoSSI Display Interface Read Mode Operation SoSSI Display Interface Write Mode Operation MMC/SD Host Command Timings MMC/SD Card Response Timings MMC/SD Host Write Timings MMC/SD Host Read Card Status Timings Timings Integrated Transceiver Interface Timings MICROWIRE Timings Interface Reading From Slave Device Interface Writing Slave Device Typical Communications Between OMAP5912 Slave HDQ/1-Wire Break (Reset) Timings 1-Wire Interface Reading From 1-Wire Slave Device 1-Wire Interface Writing 1-Wire Slave Device Normal Mode Half Rate Clock Rising Falling Clock Edge Demultiplexed Mode Full Rate Clock Rising Clock Edge
Page
OMAP5912 289-Ball Plastic Ball Grid Array Package (ZDY) OMAP5912 289-Ball MicroStar Plastic Ball Grid Array Package (ZZG)
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Tables
List Tables
Table 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 3-20 3-21 3-22 3-23 3-24 3-25 3-26 3-27 3-28 3-29 3-30 3-31 3-32 3-33 3-34 Package Terminal Assignments Package Terminal Assignments Package Terminal Characteristics Package Terminal Characteristics Signal Description OMAP5912 Global Memory Level Interrupt Handler Registers LCDCONV Registers Controller Registers Timer1 Registers Timer2 Registers Timer3 Registers Watchdog Timer Registers Level Interrupt Handler Registers System Controller Registers On-the-Go (OTG) Registers MICROWIRE Registers Client Registers Real-Time Clock (RTC) Registers MPUIO (Keyboard) Registers Pulse Width Light (PWL) Registers Pulse Width Tone (PWT) Registers MMC/SDIO1 Registers Timer 32-kHz Registers Host Registers Frame Adjustment Counter (FAC) Registers Specially Optimized Screen Interface (SoSSI) Registers HDQ/1-Wire Interface Registers Pulse Generator (LPG1) Registers Pulse Generator (LPG2) Registers UART1 Registers UART2 Registers SPI1 Registers McBSP2 Registers General-Purpose Timer1 Registers General-Purpose Timer2 Registers General-Purpose Timer3 Registers General-Purpose Timer4 Registers General-Purpose Timer5 Registers Page
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Tables
Table 3-35 3-36 3-37 3-38 3-39 3-40 3-41 3-42 3-43 3-44 3-45 3-46 3-47 3-48 3-49 3-50 3-51 3-52 3-53 3-54 3-55 3-56 3-57 3-58 3-59 3-60 3-61 3-62 3-63 3-64 3-65 3-66 3-67 3-68 3-69 3-70 3-71 3-72 3-73 3-74 I2C1 Registers
Page
General-Purpose Timer6 Registers General-Purpose Timer7 Registers MMC/SDIO2 Registers UART3 Registers
GPIO3 Registers GPIO4 Registers 32-kHz Synchro Count Registers General-Purpose Timer8 Registers GPIO1 Registers GPIO2 Registers MPU/DSP Shared Mailbox Registers McBSP1 Registers
MCSI1 Registers MCSI2 Registers McBSP3 Registers UART TIPB Switch Registers OMAP5912 Configuration Registers
Ultra Low-Power Device Peripheral Registers
Device Identification Registers Production Identification Registers Initiator Registers Interface (MPUI) Registers TIPB (Private) Bridge Configuration Registers
Traffic Controller EMIFS Registers Traffic Controller OCP-T1/OCP-T2 Registers Traffic Controller OCPI Registers Traffic Controller EMIFF Registers Clock/Reset/Power Mode Control Registers DPLL1 Configuration Register Registers
TIPB (Public) Bridge Configuration Registers Global Memory DARAM Blocks SARAM Blocks Controller Registers Timer1 Registers Timer2 Registers Timer3 Registers
Watchdog Timer Registers
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Tables
Table 3-75 3-76 3-77 3-78 3-79 3-80 3-81 3-82 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 5-28 5-29 5-30 5-31 5-32 Level Interrupt Handler Registers Interrupt Interface Registers Level Interrupt Handler Registers TIPB Bridge Configuration Registers EMIF Configuration Registers I-Cache Registers Clock Mode Registers TIPB Switch Registers Thermal Resistance Characteristics 32-kHz Oscillator Switching Characteristics 32-kHz Input Clock Timing Requirements Base Oscillator Switching Characteristics OMAP5912 Device Reset Timing Requirements OMAP5912 Device Reset Switching Characteristics MPU_RST Timing Requirements MPU_RST Switching Characteristics EMIFS/Flash Interface Timing Requirements EMIFS/NOR Flash Interface Switching Characteristics EMIFS/Mux Flash Interface Timing Requirements EMIFS/MUX Flash Interface Switching Characteristics EMIFS/NAND Flash Timing Requirements EMIFS/NAND Flash Switching Characteristics CompactFlash Interface Timing Requirements CompactFlash Interface Switching Characteristics EMIFF/SDR SDRAM Interface Timing Requirements EMIFF/SDR SDRAM Interface Switching Characteristics EMIFF/DDR SDRAM Interface Timing Requirements EMIFF/DDR SDRAM Interface Switching Characteristics McBSP Timing Requirements McBSP Switching Characteristics McBSP McBSP McBSP McBSP Master Slave Timing Requirements (CLKSTP 10b, CLKXP Master Slave Switching Characteristics (CLKSTP 10b, CLKXP Master Slave Timing Requirements (CLKSTP 11b, CLKXP Master Slave Switching Characteristics (CLKSTP 11b, CLKXP
Page
McBSP Master Slave Timing Requirements (CLKSTP 10b, CLKXP McBSP Master Slave Switching Characteristics (CLKSTP 10b, CLKXP McBSP Master Slave Timing Requirements (CLKSTP 11b, CLKXP McBSP Master Slave Switching Characteristics (CLKSTP 11b, CLKXP MCSI Timing Requirements MCSI Switching Characteristics
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Tables
Table 5-33 5-34 5-35 5-36 5-37 5-38 5-39 5-40 5-41 5-42 5-43 5-44 5-45 5-46 5-47 5-48 5-49 5-50 5-51 5-52 Interface Timing Requirements Interface Switching Characteristics VLYNQ Slave Timing Requirements VLYNQ Slave Switching Characteristics VLYNQ Master Timing Requirements VLYNQ Master Switching Characteristics Camera Interface Timing Requirements Interface Timing Requirements Controller LCDCONV Switching Characteristics SoSSI Display Interface Timing Requirements SoSSI Display Interface Switching Characteristics MMC/SD Timing Requirements MMC/SD Switching Characteristics Signals (I2C.SDA I2C.SCL) Switching Characteristics Integrated Transceiver Interface Switching Characteristics MICROWIRE Timing Requirements MICROWIRE Switching Characteristics HDQ/1-Wire Timing Requirements HDQ/1-Wire Switching Characteristics EInterface Switching Characteristics
Page
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Tables
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Features
OMAP5912 Features
Low-Power, High-Performance CMOS
Technology 0.13-µm Technology 1.6-V Core Voltage ARM926EJ-S (MPU) Core Support 32-Bit 16-Bit (Thumb Mode) Instruction Sets 16K-Byte Instruction Cache 8K-Byte Data Cache Data Program Memory Management Unit (MMU) 17-Word Write Buffer 64-Entry Translation Look-Aside Buffers (TLBs) MMUs TMS320C55x (C55x) Core One/Two Instructions Executed Cycle Dual Multipliers (Two Multiply-Accumulates Cycle) Arithmetic/Logic Units Five Internal Data/Operand Buses Read Buses Write Buses) 16-Bit On-Chip Dual-Access (DARAM) (64K Bytes) 16-Bit On-Chip Single-Access (SARAM) (96K Bytes) Instruction Cache (24K Bytes) Video Hardware Accelerators DCT, iDCT, Pixel Interpolation, Motion Estimation Video Compression 250K Bytes Shared Internal SRAM Memory Traffic Controller (TC) 16-Bit EMIFS Access 256M Bytes Flash (for Burst, Programmable Flash) 16-Bit EMIFF Access 128M Bytes SDRAM, Mobile SDRAM, Mobile Memory Management Unit Digital Phase-Locked Loop (DPLL) MPU/DSP/TC Clocking Control Peripherals Three 32-Bit Timers Watchdog Timer Six-Channel Controller Multichannel Buffered Serial Ports Multichannel Serial Interfaces Three 32-Bit Timers Watchdog Timer Host Client Controllers On-the-Go (OTG) Controller Ports, With Integrated Transceiver Specially Optimized Screen Interface (SoSSI) Compact Camera Port Interface Parallel CMOS Sensors Real-Time Clock (RTC) Pulse-Width Tone (PWT) Interface Pulse-Width Light (PWL) Interface Keyboard Matrix Interface HDQ/1-Wire Interface Multimedia Card (MMC) Secure Digital (SD) Interface CompactFlash Controller General-Purpose I/Os Pulse Generators (LPGs) ETM9 Trace Module ARM926EJ-S Debug 16-/18-Bit Controller With Dedicated System Channel 32-kHz Operating System (OS) Timer Shared Peripherals General-Purpose Timers Serial Port Interface (SPI) VLYNQ Interface (WLAN 802.11x) Three Universal Asynchronous Receiver/Transmitters (UARTs) (Two Supporting mode IrDA) Inter-Integrated Circuit (I2C) Master Slave Interface Multimedia Card (MMC) Secure Digital (SD) Interface Multichannel Buffered Serial Port (McBSP) Shared General-Purpose I/Os 32-kHz Synchro Counter Hardware Accelerators Cryptographic Functions Random Number Generation 3DES SHA-1 Individual Power-Saving Modes MPU/DSP/TC On-Chip Scan-Based Emulation Logic IEEE 1149.1 (JTAG) Boundary Scan Logic 289-Ball Lead-Free (Ball Grid Array) Packages (ZDY ZZG)
Peripherals
trademarks property their respective owners. IEEE Standard 1149.1-1990 Standard Test-Access Port Boundary Scan Architecture.
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SPRS231B
PRODUCT PREVIEW
Introduction
Introduction
This section describes main features OMAP5912 device, lists terminal assignments, describes function each terminal. This data manual also provides detailed description section, electrical specifications, parameter measurement information, mechanical data about available packaging.
Description
OMAP5912 highly integrated hardware software platform, designed meet application processing needs next-generation embedded devices. OMAP platform enables OEMs ODMs quickly bring market devices featuring rich user interfaces, high processing performance, long battery life through maximum flexibility fully integrated mixed processor solution. dual-core architecture provides benefits both reduced instruction computer (RISC) technologies, incorporating TMS320C55x core high-performance ARM926EJ-S core. OMAP5912 device designed leading open embedded RISC-based operating systems, well Texas Instruments (TI) DSP/BIOS software kernel foundation, available 289-ball lead-free ball grid array (BGA) packages (ZDY ZZG). OMAP5912 device targeted following applications: Applications Processing Devices Mobile Communications 802.11X Bluetooth GSM, GPRS, EDGE CDMA
PRODUCT PREVIEW
Video Image Processing (MPEG4, JPEG, Windows Media Video, etc.) Advanced Speech Applications (text-to-speech, speech recognition) Audio Processing (MPEG-1 Audio Layer3 [MP3], AMR, WMA, AAC, Other Speech Codecs) Graphics Video Acceleration Generalized Access Data Processing
TMS320C55x, C55x, VLYNQ, OMAP, DSP/BIOS trademarks Texas Instruments. ARM926EJ-S ETM9 trademarks Limited other countries. Thumb registered trademarks Limited other countries. 1-Wire registered trademark Dallas Semiconductor Corporation. CompactFlash trademark CompactFlash Association. Bluetooth trademark owned Bluetooth SIG, Inc. Windows registered trademark Microsoft Corporation United States and/or other countries.
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Introduction
2.1.1 TMS320C55x Core
core OMAP5912 device based TMS320C55x generation processor core. C55x architecture achieves high performance power through increased parallelism total focus reduction power dissipation. supports internal structure composed program bus, three data read buses, data write buses, additional buses dedicated peripheral activity. These buses provide ability perform three data reads data writes single cycle. parallel, controller perform data transfers cycle independent activity. C55x provides multiply-accumulate (MAC) units, each capable 17-bit 17-bit multiplication single cycle. central 40-bit arithmetic/logic unit (ALU) supported additional 16-bit ALU. ALUs under instruction control, providing ability optimize parallel activity power consumption. These resources managed address unit (AU) data unit (DU) C55x CPU. C55x DSPs support variable byte width instruction improved code density. instruction unit (IU) performs 32-bit program fetches from internal external memory queues instructions program unit (PU). program unit decodes instructions, directs tasks resources, manages fully protected pipeline. Predictive branching capability avoids pipeline flushes execution conditional instructions. OMAP5912 core also includes 24K-byte instruction cache minimize external memory accesses, improving data throughput conserving system power.
2.1.1.1
Tools Support
core supported industry's leading eXpressDSP software environment including Code Composer Studio Integrated Development Environment (IDE), DSP/BIOS software kernel foundation, TMS320 Algorithm Standard, industry's largest third-party network. Code Composer Studio features code generation tools including C-Compiler, Visual Linker, simulator, Real-Time Data Exchange (RTDX), XDS510 emulation device drivers, Chip Support Libraries (CSL). DSP/BIOS scalable real-time software foundation available cost users Texas Instruments' products, providing preemptive task scheduler real-time analysis capabilities with very memory megahertz overhead. TMS320 Algorithm Standard specification coding conventions allowing fast integration algorithms from different teams, sites, third parties into application framework. Texas Instruments' extensive third-party network over providers brings focused competencies complete solutions customers.
2.1.1.2
Software Support
Texas Instruments also developed foundation software available core. C55x Library (DSPLIB) features over C-callable software routines (FIR/IIR filters, Fast Fourier Transforms (FFTs), various computational functions). Image/Video Processing Library (IMGLIB) contains over software routines highly optimized C55x DSPs compiled with latest revision C55x code generation tools. These imaging functions support wide range applications that include compression, video processing, machine vision, medical imaging.
eXpressDSP, Code Composer Studio, TMS320, RTDX, XDS510 trademarks Texas Instruments.
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SPRS231B
PRODUCT PREVIEW
Introduction
2.1.2 ARM926EJ-S RISC Processor
core ARM926EJ-S reduced instruction computer (RISC) processor. ARM926EJ-S 32-bit processor core that performs 32-bit 16-bit instructions processes 32-bit, 16-bit, 8-bit data. core uses pipelining that parts processor memory system operate continuously. core incorporates: coprocessor (CP15) protection module Data program Memory Management Units (MMUs) with table look-aside buffers. Separate 16K-byte instruction 8K-byte data caches. Both four-way associative with virtual index virtual (VIVT).
OMAP5912 device uses ARM926EJ-S core little-endian mode only. minimize external memory access time, ARM926EJ-S includes instruction cache, data cache, write buffer. general, these transparent program execution.
Terminal Assignments
Figure illustrates ball locations 289-ball package Figure illustrates ball locations 289-ball package. Figure Figure used conjunction with Table Table 2-2, respectively, locate signal names ball grid numbers. ball numbers Table Table read from left-to-right, top-to-bottom.
PRODUCT PREVIEW
Bottom View
Figure 2-1. OMAP5912 289-Ball Plastic Ball Grid Array (Bottom View)
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Introduction
Bottom View
Figure 2-2. OMAP5912 289-Ball Plastic Ball Grid Array (Bottom View) Table Table 2-2, signals with multiplexed functions highlighted gray. Signals within multiplexed name separated with forward slashes follows: signal1/signal2/signal3 (e.g., MPUIO1/RTCK/SPIF.SCK)
Signals which associated with specific peripherals denoted using peripheral name, followed period, then signal name; follows: peripheral1.signal1 (i.e., MCSI1.DOUT)
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SPRS231B
PRODUCT PREVIEW
Introduction
Table 2-1. Package Terminal Assignments
BALL SIGNAL SDRAM.A[1] SDRAM.D[3] CVDDDLL LCD.P[12](0)/ Z_STATE(1)/ SOSSI.D[12](6)/ GPIO33(7) LCD.P[0](0)/ Z_STATE(1)/ SOSSI.D[0](6) SDRAM.D[0] SDRAM.D[10] BALL SIGNAL SDRAM.DQSL SDRAM.CLKX SDRAM.A[7] LCD.PCLK(0)/ Z_STATE(1)/ SOSSI.WR(6) BALL SIGNAL SDRAM.D[6] SDRAM.CLK SDRAM.D[11] LCD.P[10](0)/ Z_STATE(1)/ SOSSI.D[10](6)/ GPIO31(7) SDRAM.A[0] SDRAM.D[5] SDRAM.D[15] LCD.P[11](0)/ Z_STATE(1)/ SOSSI.D[11](6)/ GPIO32(7) BALL SIGNAL SDRAM.D[2] SDRAM.DQMU SDRAM.DQSH LCD.P[6](0)/ Z_STATE(1)/ SOSSI.D[6](6)
DVDD5 SDRAM.D[1] SDRAM.D[12]
SDRAM.D[4] SDRAM.D[7] SDRAM.D[13] LCD.VS(0)/ Z_STATE(1)/ SOSSI.RD(6)
PRODUCT PREVIEW
SDRAM.D[9]
SDRAM.CKE
LCD.P[1](0)/ Z_STATE(1)/ SOSSI.D[1](6) SDRAM.A[3] SDRAM.DQML
KB.C[2](0)/ GPIO61(7) SDRAM.BA[1] SDRAM.A[5] LCD.P[15](0)/ Z_STATE(1)/ SOSSI.D[15](6)/ GPIO2(7) LCD.P[2](0)/ Z_STATE(1)/ SOSSI.D[2](6) FLASH.A[1](0) DVDD4
FLASH.A[6](0) SDRAM.BA[0] SDRAM.D[8] LCD.P[8](0)/ Z_STATE(1)/ SOSSI.D[8](6)/ GPIO29(7) KB.C[1](0)/ MPUIO6(1) SDRAM.RAS DVDD4 LCD.P[14](0)/ Z_STATE(1)/ SOSSI.D[14](6)/ GPIO35(7) KB.C[4](0)/ GPIO27(7) FLASH.A[4](0) SDRAM.CS
FLASH.A[2](0) SDRAM.A[8] SDRAM.D[14]
CVDD
DVDD1
LCD.P[5](0)/ Z_STATE(1)/ SOSSI.D[5](6) FLASH.A[5](0) DVDD4
FLASH.A[8](0) SDRAM.CAS SDRAM.A[4] LCD.P[7](0)/ Z_STATE(1)/ SOSSI.D[7](6) KB.R[3](0)/ MPUIO13(1)/ VLYNQ.TX0(2) FLASH.A[3](0) SDRAM.A[12]
SDRAM.A[13]
DVDD4
LCD.P[3](0)/ Z_STATE(1)/ SOSSI.D[3](6) FLASH.A[9](0)
LCD.HS(0)/ Z_STATE(1)/ SOSSI.CS(6) FLASH.A[7](0) SDRAM.WE
Z_STATE high-impedance "NC" denotes Connect". LOW_STATE NOTES: Shading denotes signals with multiplexed functions. number within parenthesis signal name denotes setting (see CTRL SETTING column Table Table 2-4).
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Introduction
Table 2-1. Package Terminal Assignments (Continued)
BALL SIGNAL BALL SIGNAL BALL SIGNAL LCD.P[13](0)/ Z_STATE(1)/ SOSSI.D[13](6)/ GPIO34(7) KB.C[3](0)/ GPIO63(6) BALL SIGNAL
SDRAM.A[11]
SDRAM.A[6]
LCD.P[4](0)/ Z_STATE(1)/ SOSSI.D[4](6) KB.R[2[(0)/ MPUIO10(1)/ VLYNQ.CLK(2) FLASH.A[25] SDRAM.A[2] LCD.P[9](0)/ Z_STATE(1)/ SOSSI.D[9](6)/ GPIO30(7) KB.R[0](0)/ MPUIO8(1)/ VLYNQ.RX1(2) FLASH.A[15](0) FLASH.A[17] CVDD3 MCBSP1.DX(0)/ MCBSP1.FSX(1)/ MCBSP1.DXZ(2)/ GPIO52(7)
KB.R[1](0)/ MPUIO9(1)/ VLYNQ.RX0(2) FLASH.A[20]
FLASH.A[11](0) FLASH.A[12](0)
FLASH.A[10](0) LCD.AC(0)/ SYS_CLK_OUT(1)/ Z_STATE(2)/ SOSSI.CMD(6) KB.C[0](0)/ MPUIO0(1) DVDD5 FLASH.A[16](0) CVDD2 MCBSP1.CLKS(0)/ SOSSI.TE(6)/ GPIO62(7)
SDRAM.A[10]
SDRAM.A[9]
MCBSP1.CLKX(0)/ GPIO54(7) FLASH.A[13](0)
KB.R[4](0)/ MPUIO15(1)/ VLYNQ.TX1(2) KB.C[5](0)/ GPIO28(7) FLASH.A[14](0) CVDD2
DVDD1
MCBSP1.FSX(0)/ MCBSP1.DX(1)/ MCBSP1.DXZ(2) GPIO53(7) FLASH.A[22] FLASH.ADV
CAM.LCLK(0)/ ETM.CLK(1)/ UWIRE.SCLK(2)/ GPIO39(7) FLASH.A[18] CVDD2
MCBSP1.DR(0)/ GPIO51(7) FLASH.A[19] CAM.EXCLK(0)/ ETM.SYNC[0](1)/ UWIRE.SDO(2)/ (6)/ GPIO57(7)
LDO.FILTER
FLASH.A[21] CAM.D[3](0)/ ETM.D[3](1)/ UART3.RX(2)/ GPIO31(7)
CVDD3
Z_STATE high-impedance "NC" denotes Connect". LOW_STATE NOTES: Shading denotes signals with multiplexed functions. number within parenthesis signal name denotes setting (see CTRL SETTING column Table Table 2-4).
December 2003 Revised March 2004
SPRS231B
PRODUCT PREVIEW
Introduction
Table 2-1. Package Terminal Assignments (Continued)
BALL SIGNAL BALL SIGNAL CAM.D[6](0)/ ETM.D[6](1)/ UWIRE.CS3(2)/ MMC2.CMD/ SPI.DO(3)/ GPIO34(7) FLASH.A[23] BALL SIGNAL BALL SIGNAL
MPU_BOOT(0)/ USB1.SUSP(2)
CAM.D[7](0)/ ETM.D[7](1)/ UWIRE.CS0(2)/ MMC2.DAT2(3)/ GPIO35(7) FLASH.CS1(0)/ FLASH.CS1L(1)
CAM.D[5](0)/ ETM.D[5](1)/ UWIRE.SDI(2)/ GPIO33(7)
FLASH.BE[0](0)/ FLASH.CS2UOE(1)/ GPIO59(7) GPIO62(0)/ FLASH.CS0(1)
FLASH.A[24] FLASH.CS2(0)/ FLASH.BAA(1)/ FLASH.CS2L(2) CAM.HS(0)/ ETM.PSTAT[1](1)/ UART2.CTS(2)/ MMC2.DAT0/ SPI.DI(3)/ GPIO38(7) CAM.D[1](0)/ ETM.D[1](1)/ UART3.RTS(2)/ GPIO29(7)
FLASH.CS3(0)/ GPIO3(7)
FLASH.D[3]
PRODUCT PREVIEW
CVDD3
CAM.D[4](0)/ ETM.D[4](1)/ UART3.TX(2)/ GPIO32(7)
CAM.VS(0)/ ETM.PSTAT[2](1)/ MPUIO14(2)/ MMC2.DAT1(3) CAM.D[0](0)/ ETM.D[0](1)/ MPUIO12(2)/ MMC2.DAT3(3) CAM.RSTZ(0)/ ETM.PSTAT[0](1)/ UART2.RTS(2)/ MMC2.CLK(3)/ GPIO37(7) GPIO15(0)/ KB.R[7](1)/ TIMER.PWM2(2)/ VLYNQ.TX1(4)
CAM.D[2](0)/ ETM.D[2](1)/ UART3.CTS(2)/ GPIO30(7)
DVDD8
FLASH.CLK(0)/ FLASH.CS2UOE(1)
FLASH.BE[1](0)/ FLASH.CS2UWE(1)/ GPIO60(7) FLASH.D[6] GPIO14(0)/ KB.R[6](1)/ LCD.RED0(2)/ Z_STATE(3)/ VLYNQ.TX0(4)
FLASH.CS2U(0)/ GPIO5(1)
CVDD GPIO11(0)/ HDQ(1)/ VLYNQ.RX1(4)/ ETM.PSTAT[5](5)/ RTDX.D[3](7) UART3.TX(1)/ PWT(2)/ UART2.TX(4) TIMER.PWM0(5)/ GPIO50(7) FLASH.D[5]
FLASH.D[12] CVDD3 UART3.RX(0)/ PWL(1)/ UART2.RX(3)/ TIMER.PWM1(4)/ GPIO49(7)
FLASH.D[0]
FLASH.D[2]
DVDD5
FLASH.D[8]
FLASH.RDY(0)/ GPIO10(1)
Z_STATE high-impedance "NC" denotes Connect". LOW_STATE NOTES: Shading denotes signals with multiplexed functions. number within parenthesis signal name denotes setting (see CTRL SETTING column Table Table 2-4).
SPRS231B
December 2003 Revised March 2004
Introduction
Table 2-1. Package Terminal Assignments (Continued)
BALL SIGNAL BALL SIGNAL MCBSP2.DR(0)/ MCBSP2.DX(1)/ MCBSP2.DXZ(2)/ GPIO22(7) MPUIO2(0)/ EXT_DMA_REQ0(1)/ UWIRE.CS1(2)/ SPIF.CS1(6) BALL SIGNAL BALL SIGNAL BCLK(0)/ UART3.RTS(1)/ CAM.OUTCLK(6)/ GPIO17(7) GPIO6(0)/ SPI.CS1(1)/ MCBSP3.FSX(2)/ TIMER.EVENT3(3)/ MCSI1.DIN(4)/ TMS(5)
CVDDRTC
GPIO3(0)/ SPI.CS3(1)/ MCBSP3.FSX(2)/ LED1(3)/ ETM.PSTAT[3](5)/ RTDX.D[1](7) GPIO13(0)/ KB.R[5](1)/ LCD.BLUE0(2)/ Z_STATE(3)/ VLYNQ.CLK(4) FLASH.D[10] MMC.CLK(0)/ SSI.CARDY(6)/ GPIO57(7)
FLASH.D[4]
FLASH.D[11] CVDD I2C.SDA(0)/ GPIO48(7)
FLASH.OE UART1.CTS(0)/ UART1.IRSEL(2)/ GPIO38(7) DVDD9 GPIO4(0)/ SPI.CS2(1)/ MCBSP3.FSX(2)/ TIMER.EVENT4(3)/ SPIF.DIN(4) FLASH.D[15]
MPUIO4(0)/ EXT_DMA_REQ1(1)/ LED2(2)/ UWIRE.CS2(3)/ SPIF.CS2(4)/ MCBSP3.DR(6) FLASH.D[7]
GPIO1(0)/ UART3.RTS(1)
GPIO2(0)/ SPI.CLK(1)/ ETM.PSTAT[4](5)/ RTDX.D[0] FLASH.RP(0)/ FLASH.CS2UWE(1) MMC.CMD/SPI.DO(0)/ CFLASH.CD2(3)/ SSI.CADATA(6)/ GPIO55(7)
FLASH.D[9] MCBSP2.FSX(0)/ VLYNQ.RX1(3)/ GPIO21(7) MCSI1.SYNC(0)/ MCBSP3.DR(1)/ USB1.VP(2)/ MCBSP3.FSX(4)
PWRON_RESET
RTC_WAKE_INT(0)/ USB1.SE0(4)/ RST_HOST_OUT(5)/ CCP.CLKM(6)/ GPIO55(7)
EMU1
RST_OUT(0)/ GPIO41(7)
MPU_RST(0)/ MPUIO14(6)
MPUIO1(0)/ RTCK(1)/ SPIF.SCK(6)
MPUIO5(0)/ LOW_PWR(1)/ UART3.RTS(3)/ UART1.DTR(4)
Z_STATE high-impedance "NC" denotes Connect". LOW_STATE NOTES: Shading denotes signals with multiplexed functions. number within parenthesis signal name denotes setting (see CTRL SETTING column Table Table 2-4).
December 2003 Revised March 2004
SPRS231B
PRODUCT PREVIEW
GPIO7(0)/ MMC.DAT2(1)/ TCK(3)/ MCSI1.CLK(4)/ ETM.SYNC[1](5)/ RTDX.D[2](7)
GPIO12(0)/ MCBSP3.FSX(1)/ TIMER.EXTCLK(3)/ VLYNQ.RX0[4]
FLASH.D[1]
Introduction
Table 2-1. Package Terminal Assignments (Continued)
BALL SIGNAL GPIO0(0)/ SPI.RDY(1)/ USB.VBUS(2)/ SPIF.DOUT(3)/ MMC2.CLKIN(6) USB.PUEN(0)/ USB.CLKO(1)/ USB.PUDIS(3)/ Z_STATE(4)/ LOW_POWER(6)/ GPIO58(7) MCSI2.CLK(0)/ USB2.SUSP(1)/ USB0.SUSP(5)/ MMC2.CLK(6)/ GPIO27(7) MCSI1.DIN(0)/ USB1.RCV(1)/ EMU1(3)/ MCBSP3.DR(4)/ SSI.ACWAKE(6)/ GPIO56(7) I2C.SCL BALL SIGNAL BALL SIGNAL BALL SIGNAL
FLASH.D[13]
OSC1_OUT
FLASH.WE
UART2.BCLK(0)/ SYS_CLK_IN(6)
UART2.CTS(0)/ USB2.RCV(1)/ GPIO7(2)/ USB0.RCV(5)
GPIO8(0)/ TRST(3)/ MCSI1.DOUT(4)/ MMC2.CMD/SPI.DO(6) MCSI1.DOUT(0)/ USB1.TXD(1)/ TDO(3)/ MCBSP3.DX(4)/ CCP.DATAP(6)/ GPIO18(7)/ MCBSP3.DOUT_HIZ UWIRE.SCLK(0)/ KB.C[7](1)/ MPUIO1(2)/ UART3.CTS(4) OSC1_IN
PRODUCT PREVIEW
MMC.DAT3(0)/ MPUIO9(1)/ MPUIO6(2)/ CFLASH.CD1(3)/ SSI.ACFLAG(6)
RTC_ON_NOFF(0)/ CCP.CLKP(6)
UWIRE.SDI(0)/ UART3.DSR(1)/ UART1.DSR(2)/ MCBSP3.DR(3)/ SPIF.DIN(6)/ GPIO47(7) FLASH.D[14]
CVDDA UART2.TX(1)/ USB2.TXD(2)/ USB0.TXD(5)/ Z_STATE(6)/ GPIO17(7) MMC.DAT0/SPI.DI(0)/ Z_STATE(1)/ CFLASH.IOIS16(3)/ SSI.ACRDY(6)/ GPIO58(7) BCLKREQ(0)/ UART3.CTS(1)/ MMC2.DAT2(6)/ GPIO40(7)
FLASH.WP
MCBSP2.FSR(0)/ GPIO12(1)/ VLYNQ.RX0(3)
MPUIO3(0)/ MMC2.DAT1(6)
MCSI2.DIN(0)/ USB2.VP(1)/ USB0.VP(5)/ GPIO26(7) UART1.RTS(1)/ UART1.IRSHDN(2)/ VLYNQ.TX0(3)/ Z_STATE(6)/ GPIO39(7)
DVDDRTC
TRST
CONF
Z_STATE high-impedance "NC" denotes Connect". LOW_STATE NOTES: Shading denotes signals with multiplexed functions. number within parenthesis signal name denotes setting (see CTRL SETTING column Table Table 2-4).
SPRS231B
December 2003 Revised March 2004
Introduction
Table 2-1. Package Terminal Assignments (Continued)
BALL SIGNAL UWIRE.SDO(0)/ UART3.DTR(1)/ UART1.DTR(2)/ MCBSP3.DX(3)/ UART3.RTS(4)/ MCBSP3.DXZ(5)/ SPIF.DOUT(6)/ GPIO46(7) BALL SIGNAL BALL SIGNAL BALL SIGNAL
Z_STATE(0)/ UWIRE.CS3(1)/ KB.C[6](2)/ SPIF.CS3(3)/ UART3.RX(4)/ Z_STATE(6)/ GPIO44(7)
Z_STATE(0)/ UWIRE.CS0(1)/ MCBSP3.CLKX(2)/ UART3.TX(4)/ SPIF.CS0(6)/ GPIO45(7)
FLASH.CS1U(0)/ GPIO16(7)
USB.DP(0)/ I2C.SDA(4) UART1.RX(5)/ USB.PUEN(7)
CVDD1
UART2.RTS(1)/ USB2.SE0(2)/ MPUIO5(3)/ MPUIO12(4)/ USB0.SE0(5)/ MCSI2.DOUT(0)/ USB2.TXEN(1)/ USB0.TXEN(5)/ Z_STATE(6)/ GPIO25(7) UART1.TX(1)/ UART1.IRTX(2)/ CCP.DATAM
MCBSP2.DX(0)/ MCBSP2.DR(1)/ MCBSP2.DXZ(2)/ GPIO19(7)
DVDD3
MCLKREQ(0)/ EXT_MASTER_REQ(1)/ UART2.RX(2)/ MMC2.DAT3(6)/ GPIO23(7)
MMC.DAT2(0)/ Z_STATE(1)/ MPUIO11(2)/ CFLASH.RESET(3)/ SSI.CAFLAG(6)
DVDD6
CLK32K_IN
DVDD7
RTCK
TDO/ VLYNQ.TX0
CVDD
BFAIL/EXT_FIQ(0)/ UART3.CTS(1)/ UART1.DSR(2)/ MMC.DATDIR1(6) UART2.RX(0)/ USB2.VM(1)/ USB0.VM(5)/ GPIO18(7) MCSI2.SYNC(0)/ GIOP7(1)/ USB2.SPEED(2)/ USB0.SPEED(5)/ MMC2.CMDDIR(6) CLK32K_OUT(0)/ MPUIO0(4)/ USB1.SPEED(5)/ UART1.TX(6)/ GPIO36(7)
USB.DM(0)/ I2C.SCL(4)/ UART1.TX(5)/ Z_STATE(7)
DVDD2
MCLK(0)/ MMC2.DATDIR0(6)/ GPIO24(7)
MCBSP2.CLKX(0)/ VLYNQ.TX1(3)/ GPIO20(7)
MCBSP2.CLKR(0)/ GPIO11(1)/ VLYNQ.CLK(3)
GPIO9(0)/ EMU0(3)/ MCSI1.SYNC(4)/ MMC2.DAT0/SPI.DI(6)
MMC.DAT1(0)/ MPUIO10(1)/ MPUIO7(2)/ CFLASH.IREQ(3)/ SSI.ACDATA(6)
OSC32K_OUT
OSC32K_IN
Z_STATE high-impedance "NC" denotes Connect". LOW_STATE NOTES: Shading denotes signals with multiplexed functions. number within parenthesis signal name denotes setting (see CTRL SETTING column Table Table 2-4).
December 2003 Revised March 2004
SPRS231B
PRODUCT PREVIEW
Introduction
Table 2-1. Package Terminal Assignments (Continued)
BALL SIGNAL BALL SIGNAL Z_STATE(0)/ MCBSP3.CLKX(1)/ USB1.TXEN(2)/ MCSI1.DIN(4)/ Z_STATE(6)/ GPIO42(7) BALL SIGNAL MCSI1.CLK(0)/ MCBSP3.DX(1)/ USB1.VM(2)/ TDI(3)/ MCBSP3.CLKX(4)/ GPIO43(7) BALL SIGNAL
UART1.RX(0)/ UART1.IRRX(2)/ GPIO37(7)
EMU0
Z_STATE high-impedance "NC" denotes Connect". LOW_STATE NOTES: Shading denotes signals with multiplexed functions. number within parenthesis signal name denotes setting (see CTRL SETTING column Table Table 2-4).
PRODUCT PREVIEW
SPRS231B
December 2003 Revised March 2004
Introduction
Table 2-2. Package Terminal Assignments
BALL SIGNAL SDRAM.A[3] DVDD4 BALL SIGNAL SDRAM.A[0] CVDD2 LCD.P[13](0)/ Z_STATE(1)/ SOSSI.D[13](6)/ GPIO34(7) SDRAM.A[5] BALL SIGNAL CVDD2 CVDDDLL BALL SIGNAL DVDD4 LCD.P[5](0)/ Z_STATE(1)/ SOSSI.D[5](6) SDRAM.BA[0] SDRAM.A[9]
CVDD
DVDD1
SDRAM.CAS SDRAM.A[10]
SDRAM.A[1] SDRAM.A[2] DVDD4 LCD.AC(0)/ SYS_CLK_OUT(1)/ Z_STATE(2)/ SOSSI.CMD(6) LCD.P[6](0)/ Z_STATE(1)/ SOSSI.D[6](6)
CVDD3
DVDD4
LCD.VS(0)/ Z_STATE(1)/ SOSSI.RD(6)
CVDD3
LCD.P[1](0)/ Z_STATE(1)/ SOSSI.D[1](6) SDRAM.D[6] SDRAM.DQML SDRAM.D[15] LCD.P[14](0)/ Z_STATE(1)/ SOSSI.D[14](6)/ GPIO35(7) LCD.HS(0)/ Z_STATE(1)/ SOSSI.CS(6) SDRAM.DQSL SDRAM.D[7]
FLASH.A[3](0) SDRAM.D[2] SDRAM.CLK SDRAM.D[11] LCD.P[10](0)/ Z_STATE(1)/ SOSSI.D[10](6)/ GPIO31(7) KB.C[4](0)/ GPIO27(7) SDRAM.D[4] SDRAM.CLKX
DVDD5 SDRAM.D[1] SDRAM.D[8] SDRAM.DQSH
SDRAM.BA[1] SDRAM.D[5] SDRAM.D[12] LCD.PCLK(0)/ Z_STATE(1)/ SOSSI.WR(6) LCD.P[2](0)/ Z_STATE(1)/ SOSSI.D[2](6)
LCD.P[7](0)/ Z_STATE(1)/ SOSSI.D[7](6)
FLASH.A[5](0) SDRAM.D[0] SDRAM.DQMU
FLASH.A[2](0) SDRAM.D[3] SDRAM.D[10] LCD.P[15](0)/ Z_STATE(1)/ SOSSI.D[15](6)/ GPIO2(7)
SDRAM.D[14]
SDRAM.D[13]
SDRAM.D[9]
Z_STATE high-impedance "NC" denotes Connect". LOW_STATE NOTES: Shading denotes signals with multiplexed functions. number within parenthesis signal name denotes setting (see CTRL SETTING column Table Table 2-4).
December 2003 Revised March 2004
SPRS231B
PRODUCT PREVIEW
LCD.P[11](0)/ Z_STATE(1)/ SOSSI.D[11](6)/ GPIO32(7)
Introduction
Table 2-2. Package Terminal Assignments (Continued)
BALL SIGNAL LCD.P[9](0)/ Z_STATE(1)/ SOSSI.D[9](6)/ GPIO30(7) KB.C[1](0)/ MPUIO6(1) FLASH.A[4](0) KB.R[3](0)/ MPUIO13(1)/ VLYNQ.TX0(2) BALL SIGNAL LCD.P[8](0)/ Z_STATE(1)/ SOSSI.D[8](6)/ GPIO29(7) FLASH.A[25] BALL SIGNAL BALL SIGNAL
LCD.P[0](0)/ Z_STATE(1)/ SOSSI.D[0](6) CVDD2 KB.C[3](0)/ GPIO63(6)
KB.C[2](0)/ GPIO61(7)
FLASH.A[7](0) KB.R[4](0)/ MPUIO15(1)/ VLYNQ.TX1(2) FLASH.A[9](0)
DVDD1
FLASH.A[20] KB.R[1](0)/ MPUIO9(1)/ VLYNQ.RX0(2) FLASH.A[11](0) SDRAM.A[4] LCD.P[3](0)/ Z_STATE(1)/ SOSSI.D[3](6) MCBSP1.CLKX(0)/ GPIO54(7) SDRAM.RAS SDRAM.A[13] MCBSP1.FSX(0)/ MCBSP1.DX(1)/ MCBSP1.DXZ(2) GPIO53(7)
FLASH.A[6](0) SDRAM.CS
KB.C[0](0)/ MPUIO0(1) FLASH.A[12](0) SDRAM.A[8] LCD.P[12](0)/ Z_STATE(1)/ SOSSI.D[12](6)/ GPIO33(7) MCBSP1.CLKS(0)/ SOSSI.TE(6)/ GPIO62(7) FLASH.A[14](0) SDRAM.A[11] KB.R[2[(0)/ MPUIO10(1)/ VLYNQ.CLK(2)
FLASH.A[10](0) SDRAM.A[7] KB.R[0](0)/ MPUIO8(1)/ VLYNQ.RX1(2)
PRODUCT PREVIEW
SDRAM.A[6]
KB.C[5](0)/ GPIO28(7) FLASH.A[15](0) SDRAM.A[12] LCD.P[4](0)/ Z_STATE(1)/ SOSSI.D[4](6) CAM.EXCLK(0)/ ETM.SYNC[0](1)/ UWIRE.SDO(2)/ GPIO57(7) FLASH.A[19] CAM.D[5](0)/ ETM.D[5](1)/ UWIRE.SDI(2)/ GPIO33(7)
DVDD5 SDRAM.WE SDRAM.CKE MCBSP1.DX(0)/ MCBSP1.FSX(1)/ MCBSP1.DXZ(2)/ GPIO52(7)
MCBSP1.DR(0)/ GPIO51(7)
LDO.FILTER
FLASH.A[17]
FLASH.A[18] CAM.LCLK(0)/ ETM.CLK(1)/ UWIRE.SCLK(2)/ GPIO39(7)
FLASH.A[8](0) CAM.D[7](0)/ ETM.D[7](1)/ UWIRE.CS0(2)/ MMC2.DAT2(3)/ GPIO35(7)
FLASH.A[1](0) CAM.D[6](0)/ ETM.D[6](1)/ UWIRE.CS3(2)/ MMC2.CMD SPI.DO(3)/ GPIO34(7)
Z_STATE high-impedance "NC" denotes Connect". LOW_STATE NOTES: Shading denotes signals with multiplexed functions. number within parenthesis signal name denotes setting (see CTRL SETTING column Table Table 2-4).
SPRS231B
December 2003 Revised March 2004
Introduction
Table 2-2. Package Terminal Assignments (Continued)
BALL SIGNAL MPU_BOOT(0)/ USB1.SUSP(2) BALL SIGNAL BALL SIGNAL BALL SIGNAL
CVDD3
FLASH.A[23] CAM.D[1](0)/ ETM.D[1](1)/ UART3.RTS(2)/ GPIO29(7)
FLASH.A[22]
FLASH.A[16](0)
FLASH.A[13](0)
CAM.D[2](0)/ ETM.D[2](1)/ UART3.CTS(2)/ GPIO30(7)
CAM.D[4](0)/ ETM.D[4](1)/ UART3.TX(2)/ GPIO32(7) FLASH.BE[0](0)/ FLASH.CS2UOE(1)/ GPIO59(7) UART3.RX(0)/ PWL(1)/ UART2.RX(3)/ TIMER.PWM1(4)/ GPIO49(7)
CAM.D[3](0)/ ETM.D[3](1)/ UART3.RX(2)/ GPIO31(7) FLASH.ADV CAM.HS(0)/ ETM.PSTAT[1](1)/ UART2.CTS(2)/ MMC2.DAT0/ SPI.DI(3)/ GPIO38(7)
FLASH.A[24]
FLASH.A[21]
CAM.D[0](0)/ ETM.D[0](1)/ MPUIO12(2)/ MMC2.DAT3(3) FLASH.CS2(0)/ FLASH.BAA(1)/ FLASH.CS2L(2) GPIO7(0)/ MMC.DAT2(1)/ TCK(3)/ MCSI1.CLK(4)/ ETM.SYNC[1](5)/ RTDX.D[2](7)
DVDD8
CVDD
FLASH.CS1(0)/ FLASH.CS1L(1) GPIO2(0)/ SPI.CLK(1)/ ETM.PSTAT[4](5)/ RTDX.D[0] GPIO15(0)/ KB.R[7](1)/ TIMER.PWM2(2)/ VLYNQ.TX1(4)
GPIO62(0)/ FLASH.CS0(1) UART3.TX(1)/ PWT(2)/ UART2.TX(4) TIMER.PWM0(5)/ GPIO50(7) FLASH.D[1]
FLASH.BE[1](0)/ FLASH.CS2UWE(1)/ GPIO60(7) CAM.RSTZ(0)/ ETM.PSTAT[0](1)/ UART2.RTS(2)/ MMC2.CLK(3)/ GPIO37(7) FLASH.CLK(0)/ FLASH.CS2UOE(1) Z_STATE(0)/ UWIRE.CS0(1)/ MCBSP3.CLKX(2)/ UART3.TX(4)/ SPIF.CS0(6)/ GPIO45(7)
FLASH.D[0]
FLASH.D[2]
FLASH.CS3(0)/ GPIO3(7)
MPUIO2(0)/ EXT_DMA_REQ0(1)/ UWIRE.CS1(2)/ SPIF.CS1(6)
Z_STATE high-impedance "NC" denotes Connect". LOW_STATE NOTES: Shading denotes signals with multiplexed functions. number within parenthesis signal name denotes setting (see CTRL SETTING column Table Table 2-4).
December 2003 Revised March 2004
SPRS231B
PRODUCT PREVIEW
CAM.VS(0)/ ETM.PSTAT[2](1)/ MPUIO14(2)/ MMC2.DAT1(3)
Introduction
Table 2-2. Package Terminal Assignments (Continued)
BALL SIGNAL BALL SIGNAL GPIO13(0)/ KB.R[5](1)/ LCD.BLUE0(2)/ Z_STATE(3)/ VLYNQ.CLK(4) FLASH.CS2U(0)/ GPIO5(1) USB.DP(0)/ I2C.SDA(4) UART1.RX(5)/ USB.PUEN(7) BALL SIGNAL GPIO11(0)/ HDQ(1)/ VLYNQ.RX1(4)/ ETM.PSTAT[5](5)/ RTDX.D[3](7) FLASH.D[4] MCBSP2.DR(0)/ MCBSP2.DX(1)/ MCBSP2.DXZ(2)/ GPIO22(7) MCSI1.CLK(0)/ MCBSP3.DX(1)/ USB1.VM(2)/ TDI(3)/ MCBSP3.CLKX(4)/ GPIO43(7) GPIO4(0)/ SPI.CS2(1)/ MCBSP3.FSX(2)/ TIMER.EVENT4(3)/ SPIF.DIN(4) BALL SIGNAL GPIO14(0)/ KB.R[6](1)/ LCD.RED0(2)/ Z_STATE(3)/ VLYNQ.TX0(4) FLASH.D[5] MMC.CMD/SPI.DO(0)/ CFLASH.CD2(3)/ SSI.CADATA(6)/ GPIO55(7) Z_STATE(0)/ UWIRE.CS3(1)/ KB.C[6](2)/ SPIF.CS3(3)/ UART3.RX(4)/ Z_STATE(6)/ GPIO44(7)
GPIO12(0)/ MCBSP3.FSX(1)/ TIMER.EXTCLK(3)/ VLYNQ.RX0[4] FLASH.D[3]
FLASH.D[11]
PRODUCT PREVIEW
CLK32K_IN
GPIO3(0)/ SPI.CS3(1)/ MCBSP3.FSX(2)/ LED1(3)/ ETM.PSTAT[3](5)/ RTDX.D[1](7)
GPIO6(0)/ SPI.CS1(1)/ MCBSP3.FSX(2)/ TIMER.EVENT3(3)/ MCSI1.DIN(4)/ TMS(5)
DVDD5
FLASH.D[6]
FLASH.D[7]
FLASH.D[8]
USB.DM(0)/ I2C.SCL(4)/ UART1.TX(5)/ Z_STATE(7)
UART2.RX(0)/ USB2.VM(1)/ USB0.VM(5)/ GPIO18(7) CLK32K_OUT(0)/ MPUIO0(4)/ USB1.SPEED(5)/ UART1.TX(6)/ GPIO36(7) CVDD3
MCLKREQ(0)/ EXT_MASTER_REQ(1)/ UART2.RX(2)/ MMC2.DAT3(6)/ GPIO23(7) UART1.CTS(0)/ UART1.IRSEL(2)/ GPIO38(7)
MMC.DAT0/SPI.DI(0)/ Z_STATE(1)/ CFLASH.IOIS16(3)/ SSI.ACRDY(6)/ GPIO58(7) GPIO0(0)/ SPI.RDY(1)/ USB.VBUS(2)/ SPIF.DOUT(3)/ MMC2.CLKIN(6) FLASH.D[9]
PWRON_RESET
GPIO1(0)/ UART3.RTS(1)
FLASH.D[10]
Z_STATE high-impedance "NC" denotes Connect". LOW_STATE NOTES: Shading denotes signals with multiplexed functions. number within parenthesis signal name denotes setting (see CTRL SETTING column Table Table 2-4).
SPRS231B
December 2003 Revised March 2004
Introduction
Table 2-2. Package Terminal Assignments (Continued)
BALL SIGNAL BALL SIGNAL BALL SIGNAL MPUIO4(0)/ EXT_DMA_REQ1(1)/ LED2(2)/ UWIRE.CS2(3)/ SPIF.CS2(4)/ MCBSP3.DR(6) FLASH.D[13] BALL SIGNAL
FLASH.D[14]
I2C.SCL
MPUIO5(0)/ LOW_PWR(1)/ UART3.RTS(3)/ UART1.DTR(4) FLASH.OE
FLASH.D[12] UWIRE.SDI(0)/ UART3.DSR(1)/ UART1.DSR(2)/ MCBSP3.DR(3)/ SPIF.DIN(6)/ GPIO47(7) FLASH.RDY(0)/ GPIO10(1) UART2.TX(1)/ USB2.TXD(2)/ USB0.TXD(5)/ Z_STATE(6)/ GPIO17(7) MMC.DAT1(0)/ MPUIO10(1)/ MPUIO7(2)/ CFLASH.IREQ(3)/ SSI.ACDATA(6)
MPUIO1(0)/ RTCK(1)/ SPIF.SCK(6)
MPU_RST(0)/ MPUIO14(6)
DVDD9
MCBSP2.CLKR(0)/ GPIO11(1)/ VLYNQ.CLK(3)
MPUIO3(0)/ MMC2.DAT1(6)
MCSI2.SYNC(0)/ GIOP7(1)/ USB2.SPEED(2)/ USB0.SPEED(5)/ MMC2.CMDDIR(6)
MMC.CLK(0)/ SSI.CARDY(6)/ GPIO57(7) MCSI1.DIN(0)/ USB1.RCV(1)/ EMU1(3)/ MCBSP3.DR(4)/ SSI.ACWAKE(6)/ GPIO56(7) UWIRE.SCLK(0)/ KB.C[7](1)/ MPUIO1(2)/ UART3.CTS(4)
DVDDRTC
OSC32K_IN
UART1.RX(0)/ UART1.IRRX(2)/ GPIO37(7)
EMU0
CONF
I2C.SDA(0)/ GPIO48(7)
FLASH.RP(0)/ FLASH.CS2UWE(1) UART2.RTS(1)/ USB2.SE0(2)/ MPUIO5(3)/ MPUIO12(4)/ USB0.SE0(5)/
FLASH.WE
OSC1_OUT
USB.PUEN(0)/ USB.CLKO(1)/ USB.PUDIS(3)/ Z_STATE(4)/ LOW_POWER(6)/ GPIO58(7)
Z_STATE high-impedance "NC" denotes Connect". LOW_STATE NOTES: Shading denotes signals with multiplexed functions. number within parenthesis signal name denotes setting (see CTRL SETTING column Table Table 2-4).
December 2003 Revised March 2004
SPRS231B
PRODUCT PREVIEW
FLASH.D[15]
FLASH.WP
MCLK(0)/ MMC2.DATDIR0(6)/ GPIO24(7)
Introduction
Table 2-2. Package Terminal Assignments (Continued)
BALL SIGNAL BALL SIGNAL BALL SIGNAL BALL SIGNAL MCSI2.DOUT(0)/ USB2.TXEN(1)/ USB0.TXEN(5)/ Z_STATE(6)/ GPIO25(7) RTC_WAKE_INT(0)/ USB1.SE0(4)/ RST_HOST_OUT(5)/ CCP.CLKM(6)/ GPIO55(7)
MCBSP2.FSR(0)/ GPIO12(1)/ VLYNQ.RX0(3) MMC.DAT2(0)/ Z_STATE(1)/ MPUIO11(2)/ CFLASH.RESET(3)/ SSI.CAFLAG(6) MCSI1.DOUT(0)/ USB1.TXD(1)/ TDO(3)/ MCBSP3.DX(4)/ CCP.DATAP(6)/ GPIO18(7)/ MCBSP3.DOUT_HIZ
MCBSP2.FSX(0)/ VLYNQ.RX1(3)/ GPIO21(7) MMC.DAT3(0)/ MPUIO9(1)/ MPUIO6(2)/ CFLASH.CD1(3)/ SSI.ACFLAG(6)
GPIO9(0)/ EMU0(3)/ MCSI1.SYNC(4)/ MMC2.DAT0/SPI.DI(6)
CVDDRTC
PRODUCT PREVIEW
BCLKREQ(0)/ UART3.CTS(1)/ MMC2.DAT2(6)/ GPIO40(7)
Z_STATE(0)/ MCBSP3.CLKX(1)/ USB1.TXEN(2)/ MCSI1.DIN(4)/ Z_STATE(6)/ GPIO42(7)
EMU1
BFAIL/EXT_FIQ(0)/ UART3.CTS(1)/ UART1.DSR(2)/ MMC.DATDIR1(6)
UWIRE.SDO(0)/ UART3.DTR(1)/ UART1.DTR(2)/ MCBSP3.DX(3)/ UART3.RTS(4)/ MCBSP3.DXZ(5)/ SPIF.DOUT(6)/ GPIO46(7) UART2.BCLK(0)/ SYS_CLK_IN(6) GPIO8(0)/ TRST(3)/ MCSI1.DOUT(4)/ MMC2.CMD/SPI.DO(6)
FLASH.CS1U(0)/ GPIO16(7) UART2.CTS(0)/ USB2.RCV(1)/ GPIO7(2)/ USB0.RCV(5)
OSC1_IN MCBSP2.CLKX(0)/ VLYNQ.TX1(3)/ GPIO20(7) MCSI2.CLK(0)/ USB2.SUSP(1)/ USB0.SUSP(5)/ MMC2.CLK(6)/ GPIO27(7) BCLK(0)/ UART3.RTS(1)/ CAM.OUTCLK(6)/ GPIO17(7)
DVDD3
CVDD
RTC_ON_NOFF(0)/ CCP.CLKP(6)
UART1.TX(1)/ UART1.IRTX(2)/ CCP.DATAM TRST
DVDD7
RTCK
CVDD
CVDDA
Z_STATE high-impedance "NC" denotes Connect". LOW_STATE NOTES: Shading denotes signals with multiplexed functions. number within parenthesis signal name denotes setting (see CTRL SETTING column Table Table 2-4).
SPRS231B
December 2003 Revised March 2004
Introduction
Table 2-2. Package Terminal Assignments (Continued)
BALL SIGNAL BALL SIGNAL BALL SIGNAL BALL SIGNAL MCBSP2.DX(0)/ MCBSP2.DR(1)/ MCBSP2.DXZ(2)/ GPIO19(7)
DVDD2
CVDD1
MCSI2.DIN(0)/ USB2.VP(1)/ USB0.VP(5)/ GPIO26(7) MCSI1.SYNC(0)/ MCBSP3.DR(1)/ USB1.VP(2)/ MCBSP3.FSX(4)
AA11
DVDD6
AA13
OSC32K_OUT
AA15
UART1.RTS(1)/ UART1.IRSHDN(2)/ VLYNQ.TX0(3)/ Z_STATE(6)/ GPIO39(7)
AA17
AA19
TDO/ VLYNQ.TX0
AA20
RST_OUT(0)/ GPIO41(7)
Z_STATE high-impedance "NC" denotes Connect". LOW_STATE NOTES: Shading denotes signals with multiplexed functions. number within parenthesis signal name denotes setting (see CTRL SETTING column Table Table 2-4).
December 2003 Revised March 2004
SPRS231B
PRODUCT PREVIEW
AA21
Introduction
Terminal Characteristics Multiplexing
Table describes terminal characteristics signals multiplexed each ball package. Table describes terminal characteristics signals multiplexed each ball package. table column headers explained below: BALL NO.: package ball number. SIGNAL NAME: names signals that multiplexed each ball. TYPE: signal direction. CTRL SETTING: Shows control multiplexing modes. PULLUP/PULLDN: Denotes presence internal pullup pulldown. Pullups pulldowns enabled disabled software. BUFFER STRENGTH: Drive strength associated output buffer. OTHER: Contains various terminal information, such buffer type, boundary scan capability, gating/inhibit functionality. RESET STATE: state terminal reset. SUPPLY: voltage supply which powers terminal's buffers. NOTE: Care must taken avoid assigning multiple balls same signal. Violations cause unexpected results. Table 2-3. Package Terminal Characteristics
PRODUCT PREVIEW
BALL
SIGNAL NAME SDRAM.CS SDRAM.DQSH SDRAM.DQSL SDRAM.CAS SDRAM.RAS SDRAM.DQML SDRAM.DQMU
TYPE
CTRL SETTING
PULLUP/ PULLDN
BUFFER (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv)
RESET STATE#
SUPPLY DVDD4 DVDD4 DVDD4 DVDD4 DVDD4 DVDD4 DVDD4
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
SPRS231B
December 2003 Revised March 2004
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SDRAM.CLK SDRAM.CLKX SDRAM.CKE LCD.AC SYS_CLK_OUT Z_STATE SOSSI.CMD LCD.PCLK Z_STATE SOSSI.WR
SIGNAL NAME SDRAM.WE SDRAM.A[13:0]
TYPE
CTRL SETTING
PULLUP/ PULLDN
BUFFER (Lv) (Hv) (Lv) (Hv)
RESET STATE#
SUPPLY DVDD4 DVDD4
SDRAM.BA[1:0] SDRAM.D[15:0]
(Lv) (Hv) (Lv) (Hv)
DVDD4 DVDD4
RegD[11:9] RegD[11:9] RegD[11:9] RegD[11:9] RegD[17:15] RegD[17:15] RegD[17:15]
(Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv)
DVDD4 DVDD4 DVDD4 DVDD1
(Lv) (Hv)
DVDD1
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
December 2003 Revised March 2004
SPRS231B
PRODUCT PREVIEW
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME LCD.P[15] Z_STATE SOSSI.D[15] GPIO2 LCD.P[14] Z_STATE SOSSI.D[14] GPIO35 LCD.P[13] Z_STATE SOSSI.D[13] GPIO34 LCD.P[12] Z_STATE SOSSI.D[12] GPIO33 LCD.P[11] Z_STATE SOSSI.D[11] GPIO32 LCD.P[10] Z_STATE SOSSI.D[10] GPIO31 LCD.P[9] Z_STATE SOSSI.D[9] GPIO30 LCD.VS Z_STATE SOSSI.RD
TYPE
CTRL SETTING RegD[20:18] RegD[20:18] RegD[20:18] RegD[20:18] RegD[23:21] RegD[23:21] RegD[23:21] RegD[23:21] RegD[26:24] RegD[26:24] RegD[26:24] RegD[26:24] RegD[29:27] RegD[29:27] RegD[29:27] RegD[29:27] RegE[2:0] RegE[2:0] RegE[2:0] RegE[2:0] RegE[5:3] RegE[5:3] RegE[5:3] RegE[5:3] RegE[8:6] RegE[8:6] RegE[8:6] RegE[8:6] RegE[11:9] RegE[11:9] RegE[11:9]
PULLUP/ PULLDN PU20, PD20
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD1
PU20, PD20
(Lv) (Hv)
DVDD1
PU20, PD20
(Lv) (Hv)
DVDD1
PRODUCT PREVIEW
PU20, PD20
(Lv) (Hv)
DVDD1
PU20, PD20
(Lv) (Hv)
DVDD1
PU20, PD20
(Lv) (Hv)
DVDD1
PU20, PD20
(Lv) (Hv)
DVDD1
(Lv) (Hv)
DVDD1
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
SPRS231B
December 2003 Revised March 2004
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME LCD.P[8] Z_STATE SOSSI.D[8] GPIO29 LCD.P[7] Z_STATE SOSSI.D[7] LCD.P[6] Z_STATE SOSSI.D[6] LCD.P[5] Z_STATE SOSSI.D[5] LCD.P[4] Z_STATE SOSSI.D[4] LCD.P[3] Z_STATE SOSSI.D[3] LCD.P[2] Z_STATE SOSSI.D[2] LCD.P[1] Z_STATE SOSSI.D[1] LCD.P[0] Z_STATE SOSSI.D[0] LCD.HS Z_STATE SOSSI.CS
TYPE
CTRL SETTING RegE[14:12] RegE[14:12] RegE[14:12] RegE[14:12] RegE[17:15] RegE[17:15] RegE[17:15] RegE[20:18] RegE[20:18] RegE[20:18] RegE[23:21] RegE[23:21] RegE[23:21] RegE[26:24] RegE[26:24] RegE[26:24] RegE[29:27] RegE[29:27] RegE[29:27] RegF[2:0] RegF[2:0] RegF[2:0] RegF[5:3] RegF[5:3] RegF[5:3] RegF[8:6] RegF[8:6] RegF[8:6] RegD[14:12] RegD[14:12] RegD[14:12]
PULLUP/ PULLDN PU20, PD20
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD1
PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20
(Lv) (Hv)
DVDD1
(Lv) (Hv)
DVDD1
(Lv) (Hv)
DVDD1
(Lv) (Hv)
DVDD1
(Lv) (Hv)
DVDD1
(Lv) (Hv)
DVDD1
(Lv) (Hv)
DVDD1
(Lv) (Hv)
DVDD1
(Lv) (Hv)
DVDD1
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
December 2003 Revised March 2004
SPRS231B
PRODUCT PREVIEW
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME KB.C[4] GPIO27 KB.C[3] GPIO63 KB.C[2] GPIO61 KB.C[1] MPUIO6 KB.C[0] MPUIO0 KB.R[4] MPUIO15 VLYNQ.TX1 KB.R[3] MPUIO13 VLYNQ.TX0 KB.R[2] MPUIO10 VLYNQ.CLK KB.R[1] MPUIO9 VLYNQ.RX0 KB.R[0] MPUIO8 VLYNQ.RX1 KB.C[5] GPIO28 MCBSP1.CLKS SOSSI.TE GPIO62
TYPE
CTRL SETTING Reg3[5:3] Reg3[5:3] Reg3[8:6] Reg3[8:6] Reg3[11:9] Reg3[11:9] Reg3[14:12] Reg3[14:12] Reg3[17:15] Reg3[17:15] Reg3[20:18] Reg3[20:18] Reg3[20:18] Reg3[23:21] Reg3[23:21] Reg3[23:21] Reg3[26:24] Reg3[26:24] Reg3[26:24] Reg3[29:27] Reg3[29:27] Reg3[29:27] Reg4[2:0] Reg4[2:0] Reg4[2:0] Reg3[2:0] Reg3[2:0] Reg4[8:6] Reg4[8:6] Reg4[8:6] Reg4[11:9] Reg4[11:9]
PULLUP/ PULLDN PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU100, PD20
BUFFER (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv)
RESET STATE#
SUPPLY DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1
PRODUCT PREVIEW
PU100, PD20
(Lv) (Hv)
DVDD1
PU100, PD20
(Lv) (Hv)
DVDD1
PU100, PD20
(Lv) (Hv)
DVDD1
PU100, PD20
(Lv) (Hv)
DVDD1
PU20, PD20 PU20, PD20
(Lv) (Hv) (Lv) (Hv)
DVDD1 DVDD1
MCBSP1.CLKX GPIO54
PU20, PD20
(Lv) (Hv)
DVDD1
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
SPRS231B
December 2003 Revised March 2004
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME MCBSP1.FSX MCBSP1.DX MCBSP1.DXZ GPIO53 MCBSP1.DX MCBSP1.ESX MCBSP1.DXZ GPIO52 MCBSP1.DR GPIO51 CAM.EXCLK ETM.SYNC[0] UWIRE.SDO LOW_STATE GPIO57 CAM.LCLK ETM.CLK UWIRE.SCLK GPIO39 MPU_BOOT USB1.SUSP CAM.D[7] ETM.D[7] UWIRE.CS0 MMC2.DAT2 GPIO35 CAM.D[6] ETM.D[6] UWIRE.CS3 MMC2.CMD/SPI.DO GPIO34
TYPE
CTRL SETTING Reg4[14:12] Reg4[14:12] Reg4[14:12] Reg4[14:12] Reg4[17:15] Reg4[17:15] Reg4[17:15] Reg4[17:15] Reg4[20:18] Reg4[20:18] Reg4[23:21] Reg4[23:21] Reg4[23:21] Reg4[23:21] Reg4[23:21] Reg4[26:24] Reg4[26:24] Reg4[26:24] Reg4[26:24] Reg8[29:27] Reg8[29:27] Reg4[29:27] Reg4[29:27] Reg4[29:27] Reg4[29:27] Reg4[29:27] Reg5[2:0] Reg5[2:0] Reg5[2:0] Reg5[2:0] Reg5[2:0]
PULLUP/ PULLDN PU20, PD20
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD1
PU20, PD20
(Lv) (Hv)
DVDD1
PU20, PD20 PU20, PD20
(Lv) (Hv) (Lv) (Hv)
DVDD1 DVDD8
PU20, PD20
(Lv) (Hv)
DVDD8
(Lv) (Hv) PU20, PD20 (Lv) (Hv)
DVDD8
PU20, PD20
(Lv) (Hv)
DVDD8
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
December 2003 Revised March 2004
SPRS231B
PRODUCT PREVIEW
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME CAM.D[5] ETM.D[5] UWIRE.SDI GPIO33 CAM.D[4] ETM.D[4] UART3.TX GPIO32 CAM.D[3] ETM.D[3] UART3.RX GPIO31 CAM.D[2] ETM.D[2] UART3.CTS GPIO30 CAM.D[1] ETM.D[1] UART3.RTS GPIO29 CAM.D[0] ETM.D[0] MPUIO12 MMC2.DAT3 CAM.VS ETM.PSTAT[2] MPUIO14 MMC2.DAT1
TYPE
CTRL SETTING Reg5[5:3] Reg5[5:3] Reg5[5:3] Reg5[5:3] Reg5[8:6] Reg5[8:6] Reg5[8:6] Reg5[8:6] Reg5[11:9] Reg5[11:9] Reg5[11:9] Reg5[11:9] Reg5[14:12] Reg5[14:12] Reg5[14:12] Reg5[14:12] Reg5[17:15] Reg5[17:15] Reg5[17:15] Reg5[17:15] Reg5[20:18] Reg5[20:18] Reg5[20:18] Reg5[20:18] Reg5[23:21] Reg5[23:21] Reg5[23:21] Reg5[23:21]
PULLUP/ PULLDN PU20, PD20
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD8
PU20, PD20
(Lv) (Hv)
DVDD8
PU20, PD20
(Lv) (Hv)
DVDD8
PRODUCT PREVIEW
PU20, PD20
(Lv) (Hv)
DVDD8
PU20, PD20
(Lv) (Hv)
DVDD8
PU20, PD20
(Lv) (Hv)
DVDD8
PU20, PD20
(Lv) (Hv)
DVDD8
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
SPRS231B
December 2003 Revised March 2004
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME CAM.HS ETM.PSTAT[1] UART2.CTS MMC2.DAT0/SPI.DI GPIO38 CAM.RSTZ ETM.PSTAT[0] UART2.RTS MMC2.CLK LOW_STATE GPIO37 LOW_STATE UART3.TX UART2.TX TIMER.PWM0 GPIO50 UART3.RX UART2.RX TIMER.PWM1 GPIO49 GPIO15 KB.R[7] TIMER.PWM2 VLYNQ.TX1 GPIO14 KB.R[6] LCD.RED0 Z_STATE VLYNQ.TX0
TYPE
CTRL SETTING Reg5[26:24] Reg5[26:24] Reg5[26:24] Reg5[26:24] Reg5[26:24] Reg5[29:27] Reg5[29:27] Reg5[29:27] Reg5[29:27] Reg5[29:27] Reg5[29:27] Reg6[2:0] Reg6[2:0] Reg6[2:0] Reg6[2:0] Reg6[2:0] Reg6[2:0] Reg6[5:3] Reg6[5:3] Reg6[5:3] Reg6[5:3] Reg6[5:3] Reg6[8:6] Reg6[8:6] Reg6[8:6] Reg6[8:6] Reg6[11:9] Reg6[11:9] Reg6[11:9] Reg6[11:9] Reg6[11:9]
PULLUP/ PULLDN PU20, PD20
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD8
PU20, PD20
(Lv) (Hv)
DVDD8
PU20, PD20
(Lv) (Hv)
DVDD9
PU20, PD20
(Lv) (Hv)
DVDD9
PU100, PD20
(Lv) (Hv)
DVDD9
PU100, PD20
(Lv) (Hv)
DVDD9
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
December 2003 Revised March 2004
SPRS231B
PRODUCT PREVIEW
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME GPIO13 KB.R[5] LCD.BLUE0 Z_STATE VLYNQ.CLK GPIO12 MCBSP3.FSX TIMER.EXTCLK VLYNQ.RX0 GPIO11 VLYNQ.RX1 ETM.PSTAT[5] GPIO7 MMC.DAT2 MCSI1.CLK ETM.SYNC[1] GPIO6 SPI.CS1 MCBSP3.ESX TIMER.EVENT3 MCSI1.DIN GPIO4 SPI.CS2 MCBSP3.FSX TIMER.EVENT4
TYPE
CTRL SETTING Reg6[14:12] Reg6[14:12] Reg6[14:12] Reg6[14:12] Reg6[14:12] Reg6[17:15] Reg6[17:15] Reg6[17:15] Reg6[17:15] Reg6[20:18] Reg6[20:18] Reg6[20:18] Reg6[20:18] Reg6[23:21] Reg6[23:21] Reg6[23:21] Reg6[23:21] Reg6[23:21] Reg6[26:24] Reg6[26:24] Reg6[26:24] Reg6[26:24] Reg6[26:24] Reg6[26:24] Reg6[29:27] Reg6[29:27] Reg6[29:27] Reg6[29:27]
PULLUP/ PULLDN PU100, PD20
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD9
PU20, PD20
(Lv) (Hv)
DVDD9
PU20, PD20
(Lv) (Hv)
DVDD9
PRODUCT PREVIEW
PU20, PD20
(Lv) (Hv)
DVDD9
PD100, PU20
(Lv) (Hv)
DVDD9
PD100, PU20
(Lv) (Hv)
DVDD9
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
SPRS231B
December 2003 Revised March 2004
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME GPIO3 SPI.CS3 MCBSP3.FSX LED1 ETM.PSTAT[3] GPIO2 SPI.CLK ETM.PSTAT[4] GPIO1 UART3.RTS GPIO0 SPI.RDY USB.VBUS SPIF.DOUT MMC2.CLKIN MPUIO5 LOW_PWR UART3.RTS UART1.DTR MPUIO4 EXT_DMA_REQ1 LED2 UWIRE.CS2 SPIF.CS2 MCBSP3.DR MPUIO2 EXT_DMA_REQ0 UWIRE.CS1 SPIF.CS1
TYPE
CTRL SETTING Reg7[2:0] Reg7[2:0] Reg7[2:0] Reg7[2:0] Reg7[2:0] Reg7[5:3] Reg7[5:3] Reg7[5:3] Reg7[8:6] Reg7[8:6] Reg7[11:9] Reg7[11:9] Reg7[11:9] Reg7[11:9] Reg7[11:9] Reg7[14:12] Reg7[14:12] Reg7[14:12] Reg7[14:12] Reg7[17:15] Reg7[17:15] Reg7[17:15] Reg7[17:15] Reg7[17:15] Reg7[17:15] Reg7[20:18] Reg7[20:18] Reg7[20:18] Reg7[20:18] Reg9[8:6] Reg9[8:6]
PULLUP/ PULLDN PU100, PD20
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD9
PU100, PD20
(Lv) (Hv)
DVDD9
PU100, PD20 PU20, PD20
(Lv) (Hv) (Lv) (Hv)
DVDD9 DVDD9
PU20, PD20
(Lv) (Hv)
DVDD9
PU20, PD20
(Lv) (Hv)
DVDD9
PU100, PD20
(Lv) (Hv)
DVDD9
MPU_RST MPUIO14
(Lv) (Hv)
DVDD9
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
December 2003 Revised March 2004
SPRS231B
PRODUCT PREVIEW
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME MPUIO1 RTCK SPIF.SCK I2C.SCL I2C.SDA GPIO48 UWIRE.SDI UART3.DSR UART1.DSR MCBSP3.DR SPIF.DIN GPIO47 TYPE I/O/Z I/O/Z CTRL SETTING Reg7[23:21] Reg7[23:21] Reg7[23:21] Reg7[26:24] Reg7[29:27] Reg7[29:27] Reg8[2:0] Reg8[2:0] Reg8[2:0] Reg8[2:0] Reg8[2:0] Reg8[2:0] Reg8[5:3] Reg8[5:3] Reg8[5:3] Reg8[5:3] Reg8[5:3] Reg8[5:3] Reg8[5:3] Reg8[5:3] Reg8[8:6] Reg8[8:6] Reg8[8:6] Reg8[8:6] Reg8[11:9] Reg8[11:9] Reg8[11:9] Reg8[11:9] Reg8[11:9] Reg8[11:9] PU100, PD20 (Lv) (Hv) DVDD9 PU20, PD20 (Lv) (Hv) DVDD9 PU20, PD20 (Lv) (Hv) DVDD9 PU20, PD20 (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) DVDD9 DVDD9 DVDD9 PULLUP/ PULLDN PU100, PD20 BUFFER (Lv) (Hv) RESET STATE# SUPPLY DVDD9
PRODUCT PREVIEW
UWIRE.SDO UART3.DTR UART1.DTR MCBSP3.DX UART3.RTS MCBSP3.DXZ SPIF.DOUT GPIO46
UWIRE.SCLK KB.C[7] MPUIO1 UART3.CTS
Z_STATE UWIRE.CS0 MCBSP3.CLKX UART3.TX SPIF.CS0 GPIO45
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
SPRS231B
December 2003 Revised March 2004
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME Z_STATE UWIRE.CS3 KB.C[6] SPIF.CS3 UART3.RX Z_STATE GPIO44 BFAIL/EXT_FIQ UART3.CTS UART1.DSR MMC2.DATDIR1
TYPE
CTRL SETTING Reg8[14:12] Reg8[14:12] Reg8[14:12] Reg8[14:12] Reg8[14:12] Reg8[14:12] Reg8[14:12] Reg8[17:15] Reg8[17:15] Reg8[17:15] Reg8[17:15] Reg9[11:9] Reg9[11:9]
PULLUP/ PULLDN PU20, PD20
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD9
PU20, PD20
(Lv) (Hv)
DVDD9
RST_OUT GPIO41 CONF VLYNQ.TX0 TRST EMU0 EMU1 RTCK
PU20, PD20 PU20, PD20 PD100, PU20
(Lv) (Hv)
DVDD9 DVDD9 DVDD9 DVDD9 DVDD9 DVDD9 DVDD9 DVDD9 DVDD9 DVDD9
(Lv) (Hv) PD100, PU20 PD100, PU20 PU20, PD20 PU100, PD20 PU100, PD20 (Lv) (Hv) (Lv) (Hv) (Lv) (Hv)
Input Input
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
December 2003 Revised March 2004
SPRS231B
PRODUCT PREVIEW
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME MCSI1.SYNC MCBSP3.DR USB1.VP MCBSP3.FSX MCSI1.CLK MCBSP3.DX USB1.VM MCBSP3.CLKX GPIO43 Z_STATE MCBSP3.CLKX USB1.TXEN MCSI1.DIN Z_STATE GPIO42 MCSI1.DIN USB1.RCV EMU1 MCBSP3.DR SSI.ACWAKE GPIO56 BCLKREQ UART3.CTS MMC2.DAT2 GPIO40 BCLK UART3.RTS CAM.OUTCLK GPIO17
TYPE
CTRL SETTING RegA[5:3] RegA[5:3] RegA[5:3] RegA[5:3] RegA[8:6] RegA[5:3] RegA[5:3] RegA[5:3] RegA[5:3] RegA[5:3] Reg9[5:3] Reg9[5:3] Reg9[5:3] Reg9[5:3] Reg9[5:3] Reg9[5:3] RegA[11:9] RegA[11:9] RegA[11:9] RegA[11:9] RegA[11:9] RegA[11:9] Reg9[29:27] Reg9[29:27] Reg9[29:27] Reg9[29:27] RegA[2:0] RegA[2:0] RegA[2:0] RegA[2:0]
PULLUP/ PULLDN PU20, PD20
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD7
PU20, PD20
(Lv) (Hv)
DVDD7
PU20, PD20
(Lv) (Hv)
DVDD7
PRODUCT PREVIEW
PU20, PD20
(Lv) (Hv)
DVDD7
PU20, PD20
(Lv) (Hv)
DVDD7
PU20, PD20
(Lv) (Hv)
DVDD7
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
SPRS231B
December 2003 Revised March 2004
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME LOW_STATE UART1.RTS UART1.IRSHDN Z_STATE GPIO39 UART1.CTS UART1.IRSEL GPIO38 UART1.RX UART1.IRRX GPIO37 LOW_STATE UART1.TX UART1.IRTX CCP.DATAM MCSI1.DOUT USB1.TXD MCBSP3.DX CCP.DATAP GPIO18 CLK32K_OUT MPUIO0 USB1.SPEED UART1.TX GPIO36
TYPE
CTRL SETTING Reg9[14:12] Reg9[14:12] Reg9[14:12] Reg9[14:12] Reg9[14:12] Reg9[17:15] Reg9[17:15] Reg9[17:15] Reg9[20:18] Reg9[20:18] Reg9[20:18] Reg9[23:21] Reg9[23:21] Reg9[23:21] Reg9[23:21] Reg9[26:24] Reg9[26:24] Reg9[26:24] Reg9[26:24] Reg9[26:24] Reg9[26:24] RegA[14:12] RegA[14:12] RegA[14:12] RegA[14:12] RegA[14:12]
PULLUP/ PULLDN PU20, PD20
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD7
PU20, PD20
(Lv) (Hv)
DVDD7
PU20, PD20
(Lv) (Hv)
DVDD7
(Lv) (Hv)
DVDD7
(Lv) (Hv)
DVDD7
PU20, PD20
(Lv) (Hv)
DVDDRTC
OSC32K_IN OSC32K_OUT
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
December 2003 Revised March 2004
SPRS231B
PRODUCT PREVIEW
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME RTC_WAKE_INT USB1.SE0 RST_HOST_OUT CCP.CLKM GPIO55 RTC_ON_NOFF CCP.CLKP CLK32K_IN PWRON_RESET MMC.DAT3 MPUIO9 MPUIO6 CFLASH.CD1 SSI.ACFLAG MMC.CLK SSI.CARDY GPIO57 MMC.DAT0/SPI.DI Z_STATE CFLASH.IOIS16 SSI.ACRDY GPIO58 MMC.DAT2 Z_STATE MPUIO11 CFLASH.RFSFT SSI.CAFLAG MMC.DAT1 MPUIO10 MPUIO7 CFLASH.IRFQ SSI.ACDATA
TYPE
CTRL SETTING Reg9[2:0] Reg9[2:0] Reg9[2:0] Reg9[2:0] Reg9[2:0] Reg8[20:18] Reg8[20:18] RegA[17:15] Reg10[17:15] Reg10[17:15] Reg10[17:15] Reg10[17:15] Reg10[17:15] RegA[23:21] RegA[23:21] RegA[23:21] RegB[2:0] RegB[2:0] RegB[2:0] RegB[2:0] RegB[2:0] RegA[20:18] RegA[20:18] RegA[20:18] RegA[20:18] RegA[20:18] RegA[26:24] RegA[26:24] RegA[26:24] RegA[26:24] RegA[26:24]
PULLUP/ PULLDN
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDDRTC
(Lv) (Hv)
DVDDRTC DVDDRTC DVDDRTC DVDD6
PU20, PD20 (Lv) (Hv)
Input Input
PRODUCT PREVIEW
PD100, PU20
(Lv) (Hv)
DVDD6
PU20, PD20
(Lv) (Hv)
DVDD6
PD100, PU20
(Lv) (Hv)
DVDD6
PU20, PD20
(Lv) (Hv)
DVDD6
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
SPRS231B
December 2003 Revised March 2004
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME MMC.CMD/SPI.DO CFLASH.CD2 SSI.CADATA GPIO55 MCSI2.CLK USB2.SUSP USB0.SUSP MMC2.CLK GPIO27 MCSI2.DIN USB2.VP USB0.VP GPIO26 MCSI2.DOUT USB2.TXEN USB0.TXEN Z_STATE GPIO25 MCSI2.SYNC GPIO7 USB2.SPEED USB0.SPEED MMC2.CMDDIR MCLKREQ EXT_MASTER_REQ UART2.RX MMC2.DAT3 GPIO23 GPIO9 EMU0 MCSI1.SYNC MMC2.DAT0/SPI.DI
TYPE
CTRL SETTING RegA[29:27] RegA[29:27] RegA[29:27] RegA[29:27] RegB[5:3] RegB[5:3] RegB[5:3] RegB[5:3] RegB[5:3] RegB[8:6] RegB[8:6] RegB[8:6] RegB[8:6] RegB[11:9] RegB[11:9] RegB[11:9] RegB[11:9] RegB[11:9] RegB[14:12] RegB[14:12] RegB[14:12] RegB[14:12] RegB[14:12] RegB[20:18] RegB[20:18] RegB[20:18] RegB[20:18] RegB[20:18] RegB[23:21] RegB[23:21] RegB[23:21] RegB[23:21]
PULLUP/ PULLDN PD100, PU20
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD6
PU20, PD20
(Lv) (Hv)
DVDD3
PU20, PD20
(Lv) (Hv)
DVDD3
PU20, PD20
(Lv) (Hv)
DVDD3
PU20, PD20
(Lv) (Hv)
DVDD3
PU20, PD20
(Lv) (Hv)
DVDD3
PU20, PD20
(Lv) (Hv)
DVDD3
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
December 2003 Revised March 2004
SPRS231B
PRODUCT PREVIEW
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME GPIO8 TRST MCSI1.DOUT MMC2.CMD/SPI.DO MPUIO3 MMC2.DAT1 MCBSP2.DR MCBSP2.DX MCBSP2.DXZ GPIO22 MCBSP2.FSX VLYNQ.RX1 GPIO21 MCBSP2.CLKR GPIO11 VLYNQ.CLK MCBSP2.CLKX VLYNQ.TX1 GPIO20 MCBSP2.FSR GPIO12 VLYNQ.RX0 MCBSP2.DX MCBSP2.DR MCBSP2.DXZ VLYNQ.TX0 GPIO19 UART2.RX USB2.VM USB0.VM GPIO18
TYPE
CTRL SETTING RegB[26:24] RegB[26:24] RegB[26:24] RegB[26:24] RegB[29:27] RegB[29:27] RegC[2:0] RegC[2:0] RegC[2:0] RegC[2:0] RegC[5:3] RegC[5:3] RegC[5:3] RegC[8:6] RegC[8:6] RegC[8:6] RegC[11:9] RegC[11:9] RegC[11:9] RegC[14:12] RegC[14:12] RegC[14:12] RegC[17:15] RegC[17:15] RegC[17:15] RegC[17:15] RegC[17:15] RegC[20:18] RegC[20:18] RegC[20:18] RegC[20:18]
PULLUP/ PULLDN PU20, PD20
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD3
PU20, PD20 PU20, PD20
(Lv) (Hv) (Lv) (Hv)
DVDD3 DVDD3
PU20, PD20
(Lv) (Hv)
DVDD3
PRODUCT PREVIEW
PU20, PD20
(Lv) (Hv)
DVDD3
PU20, PD20
(Lv) (Hv)
DVDD3
PU20, PD20
(Lv) (Hv)
DVDD3
PU20, PD20
(Lv) (Hv)
DVDD3
PU20, PD20
(Lv) (Hv)
DVDD3
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
SPRS231B
December 2003 Revised March 2004
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME UART2.CTS USB2.RCV GPIO7 USB0.RCV LOW_STATE UART2.RTS USB2.SE0 MPUIO5 MPUIO12 USB0.SE0 LOW_STATE LOW_STATE UART2.TX USB2.TXD USB0.TXD Z_STATE GPIO17 UART2.BCLK SYS_CLK_IN MCLK MMC2.DATDIR0 GPIO24 USB.PUEN USB.CLKO USB.PUDIS Z_STATE LOW_POWER GPIO58 USB.DP I2C.SDA UART1.RX USB.PUEN
TYPE I/O/Z
CTRL SETTING RegC[23:21] RegC[23:21] RegC[23:21] RegC[23:21] RegC[26:24] RegC[26:24] RegC[26:24] RegC[26:24] RegC[26:24] RegC[26:24] RegC[26:24] RegC[29:27] RegC[29:27] RegC[29:27] RegC[29:27] RegC[29:27] RegC[29:27] RegD[2:0] RegD[2:0] RegB[17:15] RegB[17:15] RegB[17:15] RegD[5:3] RegD[5:3] RegD[5:3] RegD[5:3] RegD[5:3] RegD[5:3] USBTCTL[6:4] USBTCTL[6:4] USBTCTL[6:4] USBTCTL[6:4]
PULLUP/ PULLDN PU20, PD20
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD3
(Lv) (Hv)
DVDD3
(Lv) (Hv) PU20, PD20 (Lv) (Hv)
DVDD3 DVDD3
PU20, PD20
(Lv) (Hv)
DVDD2
18.3 mode)
DVDD2
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
December 2003 Revised March 2004
SPRS231B
PRODUCT PREVIEW
PU20, PD20
(Lv) (Hv)
DVDD3
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME USB.DM I2C.SCL UART1.TX Z_STATE OSC1_IN OSC1_OUT FLASH.CS1U GPIO16 FLASH.WP FLASH.WE FLASH.RP FLASH.CS2UWE FLASH.OE FLASH.A[25:17]
TYPE I/O/Z
CTRL SETTING
PULLUP/ PULLDN
BUFFER 18.3 mode)
RESET STATE#
SUPPLY DVDD2
USBTCTL[6:4] USBTCTL[6:4] USBTCTL[6:4] RegA[2:0] RegA[2:0] RegF[23:21] RegF[23:21]
(Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv)
DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5
PRODUCT PREVIEW
FLASH.A[16] FLASH.A[15] FLASH.A[14] FLASH.A[13] FLASH.A[12] FLASH.A[11]
Reg11[5:3] Reg11[8:6] Reg11[11:9] Reg11[14:12] Reg11[17:15] Reg11[20:18]
PU20, PD20
(Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv)
DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5
PU20, PD20
(Lv) (Hv) (Lv) (Hv)
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
SPRS231B
December 2003 Revised March 2004
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL FLASH.CLK FLASH.CS2UOE FLASH.RDY GPIO10
SIGNAL NAME FLASH.A[10] FLASH.A[9] FLASH.A[8] FLASH.A[7] FLASH.A[6] FLASH.A[5] FLASH.A[4] FLASH.A[3] FLASH.A[2] FLASH.A[1] FLASH.D[15:0]
TYPE
CTRL SETTING Reg11[23:21] Reg11[26:24] Reg12[5:3] Reg12[8:6] Reg12[11:9] Reg12[14:12] Reg12[17:15] Reg12[20:18] Reg12[23:21] Reg12[26:24]
PULLUP/ PULLDN
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5 DVDD5
PU20, PD20
(Lv) (Hv) (Lv) (Hv)
PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20
(Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv)
Reg10[23:21] Reg10[23:21] RegF[29:27] RegF[29:27] PU100, PD20
(Lv) (Hv) (Lv) (Hv) (Lv) (Hv)
DVDD5 DVDD5 DVDD5
Input
FLASH.ADV
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
December 2003 Revised March 2004
SPRS231B
PRODUCT PREVIEW
Introduction
Table 2-3. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME FLASH.CS2 FLASH.BAA FLASH.CS2L GPIO62 FLASH.CS0 FLASH.CS1 FLASH.CS1L FLASH.CS2U GPIO5 FLASH.BE[0] FLASH.CS2UOE GPIO59 FLASH.BE[1] FLASH.CS2UWE GPIO60
TYPE
CTRL SETTING RegD[8:6] RegD[8:6] RegD[8:6] Reg10[2:0] Reg10[2:0] Reg10[29:27] Reg10[29:27] Reg10[20:18] Reg10[20:18] Reg10[8:6] Reg10[8:6] Reg10[8:6] Reg10[5:3] Reg10[5:3] Reg10[5:3] Reg10[26:24] Reg10[26:24]
PULLUP/ PULLDN
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD5
(Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv)
Input
DVDD5 DVDD5 DVDD5 DVDD5
PRODUCT PREVIEW
(Lv) (Hv)
DVDD5
FLASH.CS3 GPIO3
(Lv) (Hv)
DVDD5
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
SPRS231B
December 2003 Revised March 2004
Introduction
Table 2-4. Package Terminal Characteristics
BALL
SIGNAL NAME
TYPE
CTRL SETTING
PULLUP/ PULLDN
BUFFER (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv)
RESET STATE#
SUPPLY
SDRAM.CS SDRAM.DQSH SDRAM.DQSL SDRAM.CAS SDRAM.RAS SDRAM.DQML SDRAM.DQMU SDRAM.WE SDRAM.A[13:0]
DVDD4 DVDD4 DVDD4 DVDD4 DVDD4 DVDD4 DVDD4 DVDD4 DVDD4
SDRAM.BA[1:0] SDRAM.D[15:0]
(Lv) (Hv) (Lv) (Hv)
DVDD4 DVDD4
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
December 2003 Revised March 2004
SPRS231B
PRODUCT PREVIEW
Introduction
Table 2-4. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME SDRAM.CLK SDRAM.CLKX SDRAM.CKE LCD.AC SYS_CLK_OUT Z_STATE SOSSI.CMD LCD.PCLK Z_STATE SOSSI.WR TYPE CTRL SETTING RegD[11:9] RegD[11:9] RegD[11:9] RegD[11:9] RegD[17:15] RegD[17:15] RegD[17:15] RegD[20:18] RegD[20:18] RegD[20:18] RegD[20:18] RegD[23:21] RegD[23:21] RegD[23:21] RegD[23:21] RegD[26:24] RegD[26:24] RegD[26:24] RegD[26:24] RegD[29:27] RegD[29:27] RegD[29:27] RegD[29:27] RegE[2:0] RegE[2:0] RegE[2:0] RegE[2:0] PU20, PD20 (Lv) (Hv) DVDD1 PU20, PD20 (Lv) (Hv) DVDD1 PU20, PD20 (Lv) (Hv) DVDD1 PU20, PD20 (Lv) (Hv) DVDD1 PU20, PD20 (Lv) (Hv) DVDD1 (Lv) (Hv) DVDD1 PULLUP/ PULLDN BUFFER (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) RESET STATE# SUPPLY DVDD4 DVDD4 DVDD4 DVDD1
PRODUCT PREVIEW
LCD.P[15] Z_STATE SOSSI.D[15] GPIO2
LCD.P[14] Z_STATE SOSSI.D[14] GPIO35
LCD.P[13] Z_STATE SOSSI.D[13] GPIO34
LCD.P[12] Z_STATE SOSSI.D[12] GPIO33
LCD.P[11] Z_STATE SOSSI.D[11] GPIO32
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
SPRS231B
December 2003 Revised March 2004
Introduction
Table 2-4. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME LCD.P[10] Z_STATE SOSSI.D[10] GPIO31 LCD.P[9] Z_STATE SOSSI.D[9] GPIO30 LCD.VS Z_STATE SOSSI.RD LCD.P[8] Z_STATE SOSSI.D[8] GPIO29 LCD.P[7] Z_STATE SOSSI.D[7] LCD.P[6] Z_STATE SOSSI.D[6] LCD.P[5] Z_STATE SOSSI.D[5] LCD.P[4] Z_STATE SOSSI.D[4] LCD.P[3] Z_STATE SOSSI.D[3]
TYPE
CTRL SETTING RegE[5:3] RegE[5:3] RegE[5:3] RegE[5:3] RegE[8:6] RegE[8:6] RegE[8:6] RegE[8:6] RegE[11:9] RegE[11:9] RegE[11:9] RegE[14:12] RegE[14:12] RegE[14:12] RegE[14:12] RegE[17:15] RegE[17:15] RegE[17:15] RegE[20:18] RegE[20:18] RegE[20:18] RegE[23:21] RegE[23:21] RegE[23:21] RegE[26:24] RegE[26:24] RegE[26:24] RegE[29:27] RegE[29:27] RegE[29:27]
PULLUP/ PULLDN PU20, PD20
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD1
PU20, PD20
(Lv) (Hv)
DVDD1
(Lv) (Hv)
DVDD1
PU20, PD20
(Lv) (Hv)
DVDD1
PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20
(Lv) (Hv)
DVDD1
(Lv) (Hv)
DVDD1
(Lv) (Hv)
DVDD1
(Lv) (Hv)
DVDD1
(Lv) (Hv)
DVDD1
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
December 2003 Revised March 2004
SPRS231B
PRODUCT PREVIEW
Introduction
Table 2-4. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME LCD.P[2] Z_STATE SOSSI.D[2] LCD.P[1] Z_STATE SOSSI.D[1] LCD.P[0] Z_STATE SOSSI.D[0] LCD.HS Z_STATE SOSSI.CS KB.C[4] GPIO27 KB.C[3] GPIO63 KB.C[2] GPIO61 KB.C[1] MPUIO6 KB.C[0] MPUIO0 KB.R[4] MPUIO15 VLYNQ.TX1 KB.R[3] MPUIO13 VLYNQ.TX0 KB.R[2] MPUIO10 VLYNQ.CLK
TYPE
CTRL SETTING RegF[2:0] RegF[2:0] RegF[2:0] RegF[5:3] RegF[5:3] RegF[5:3] RegF[8:6] RegF[8:6] RegF[8:6] RegD[14:12] RegD[14:12] RegD[14:12] Reg3[5:3] Reg3[5:3] Reg3[8:6] Reg3[8:6] Reg3[11:9] Reg3[11:9] Reg3[14:12] Reg3[14:12] Reg3[17:15] Reg3[17:15] Reg3[20:18] Reg3[20:18] Reg3[20:18] Reg3[23:21] Reg3[23:21] Reg3[23:21] Reg3[26:24] Reg3[26:24] Reg3[26:24]
PULLUP/ PULLDN PU20, PD20 PU20, PD20 PU20, PD20
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD1
(Lv) (Hv)
DVDD1
(Lv) (Hv)
DVDD1
(Lv) (Hv)
DVDD1
PRODUCT PREVIEW
PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU20, PD20 PU100, PD20
(Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv) (Lv) (Hv)
DVDD1 DVDD1 DVDD1 DVDD1 DVDD1 DVDD1
PU100, PD20
(Lv) (Hv)
DVDD1
PU100, PD20
(Lv) (Hv)
DVDD1
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
SPRS231B
December 2003 Revised March 2004
Introduction
Table 2-4. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME KB.R[1] MPUIO9 VLYNQ.RX0 KB.R[0] MPUIO8 VLYNQ.RX1 KB.C[5] GPIO28 MCBSP1.CLKS SOSSI.TE GPIO62 MCBSP1.CLKX GPIO54 MCBSP1.FSX MCBSP1.DX MCBSP1.DXZ GPIO53 MCBSP1.DX MCBSP1.ESX MCBSP1.DXZ GPIO52 MCBSP1.DR GPIO51 CAM.EXCLK ETM.SYNC[0] UWIRE.SDO LOW_STATE GPIO57 CAM.LCLK ETM.CLK UWIRE.SCLK GPIO39
TYPE
CTRL SETTING Reg3[29:27] Reg3[29:27] Reg3[29:27] Reg4[2:0] Reg4[2:0] Reg4[2:0] Reg3[2:0] Reg3[2:0] Reg4[8:6] Reg4[8:6] Reg4[8:6] Reg4[11:9] Reg4[11:9] Reg4[14:12] Reg4[14:12] Reg4[14:12] Reg4[14:12] Reg4[17:15] Reg4[17:15] Reg4[17:15] Reg4[17:15] Reg4[20:18] Reg4[20:18] Reg4[23:21] Reg4[23:21] Reg4[23:21] Reg4[23:21] Reg4[23:21] Reg4[26:24] Reg4[26:24] Reg4[26:24] Reg4[26:24]
PULLUP/ PULLDN PU100, PD20
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD1
PU100, PD20
(Lv) (Hv)
DVDD1
PU20, PD20 PU20, PD20
(Lv) (Hv) (Lv) (Hv)
DVDD1 DVDD1
PU20, PD20
(Lv) (Hv)
DVDD1
PU20, PD20
(Lv) (Hv)
DVDD1
PU20, PD20 PU20, PD20
(Lv) (Hv) (Lv) (Hv)
DVDD1 DVDD8
PU20, PD20
(Lv) (Hv)
DVDD8
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
December 2003 Revised March 2004
SPRS231B
PRODUCT PREVIEW
PU20, PD20
(Lv) (Hv)
DVDD1
Introduction
Table 2-4. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME MPU_BOOT USB1.SUSP CAM.D[7] ETM.D[7] UWIRE.CS0 MMC2.DAT2 GPIO35 CAM.D[6] ETM.D[6] UWIRE.CS3 MMC2.CMD/SPI.DO GPIO34 TYPE CTRL SETTING Reg8[29:27] Reg8[29:27] Reg4[29:27] Reg4[29:27] Reg4[29:27] Reg4[29:27] Reg4[29:27] Reg5[2:0] Reg5[2:0] Reg5[2:0] Reg5[2:0] Reg5[2:0] Reg5[5:3] Reg5[5:3] Reg5[5:3] Reg5[5:3] Reg5[8:6] Reg5[8:6] Reg5[8:6] Reg5[8:6] Reg5[11:9] Reg5[11:9] Reg5[11:9] Reg5[11:9] Reg5[14:12] Reg5[14:12] Reg5[14:12] Reg5[14:12] Reg5[17:15] Reg5[17:15] Reg5[17:15] Reg5[17:15] PU20, PD20 (Lv) (Hv) DVDD8 PU20, PD20 (Lv) (Hv) DVDD8 PU20, PD20 (Lv) (Hv) DVDD8 PU20, PD20 (Lv) (Hv) DVDD8 PU20, PD20 (Lv) (Hv) DVDD8 PU20, PD20 (Lv) (Hv) DVDD8 PU20, PD20 PULLUP/ PULLDN BUFFER (Lv) (Hv) (Lv) (Hv) RESET STATE# SUPPLY
DVDD8
PRODUCT PREVIEW
CAM.D[5] ETM.D[5] UWIRE.SDI GPIO33
CAM.D[4] ETM.D[4] UART3.TX GPIO32
CAM.D[3] ETM.D[3] UART3.RX GPIO31
CAM.D[2] ETM.D[2] UART3.CTS GPIO30
CAM.D[1] ETM.D[1] UART3.RTS GPIO29
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
SPRS231B
December 2003 Revised March 2004
Introduction
Table 2-4. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME CAM.D[0] ETM.D[0] MPUIO12 MMC2.DAT3 CAM.VS ETM.PSTAT[2] MPUIO14 MMC2.DAT1 CAM.HS ETM.PSTAT[1] UART2.CTS MMC2.DAT0/SPI.DI GPIO38 CAM.RSTZ ETM.PSTAT[0] UART2.RTS MMC2.CLK LOW_STATE GPIO37 LOW_STATE UART3.TX UART2.TX TIMER.PWM0 GPIO50 UART3.RX UART2.RX TIMER.PWM1 GPIO49
TYPE
CTRL SETTING Reg5[20:18] Reg5[20:18] Reg5[20:18] Reg5[20:18] Reg5[23:21] Reg5[23:21] Reg5[23:21] Reg5[23:21] Reg5[26:24] Reg5[26:24] Reg5[26:24] Reg5[26:24] Reg5[29:27] Reg5[29:27] Reg5[29:27] Reg5[29:27] Reg5[29:27] Reg5[29:27] Reg6[2:0] Reg6[2:0] Reg6[2:0] Reg6[2:0] Reg6[2:0] Reg6[2:0] Reg6[5:3] Reg6[5:3] Reg6[5:3] Reg6[5:3] Reg6[5:3] Reg5[26:24]
PULLUP/ PULLDN PU20, PD20
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD8
PU20, PD20
(Lv) (Hv)
DVDD8
PU20, PD20
(Lv) (Hv)
DVDD8
PU20, PD20
(Lv) (Hv)
DVDD8
PU20, PD20
(Lv) (Hv)
DVDD9
PU20, PD20
(Lv) (Hv)
DVDD9
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
December 2003 Revised March 2004
SPRS231B
PRODUCT PREVIEW
Introduction
Table 2-4. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME GPIO15 KB.R[7] TIMER.PWM2 VLYNQ.TX1 GPIO14 KB.R[6] LCD.RED0 Z_STATE VLYNQ.TX0 GPIO13 KB.R[5] LCD.BLUE0 Z_STATE VLYNQ.CLK GPIO12 MCBSP3.FSX TIMER.EXTCLK VLYNQ.RX0 GPIO11 VLYNQ.RX1 ETM.PSTAT[5] GPIO7 MMC.DAT2 MCSI1.CLK ETM.SYNC[1]
TYPE
CTRL SETTING Reg6[8:6] Reg6[8:6] Reg6[8:6] Reg6[8:6] Reg6[11:9] Reg6[11:9] Reg6[11:9] Reg6[11:9] Reg6[11:9] Reg6[14:12] Reg6[14:12] Reg6[14:12] Reg6[14:12] Reg6[14:12] Reg6[17:15] Reg6[17:15] Reg6[17:15] Reg6[17:15] Reg6[20:18] Reg6[20:18] Reg6[20:18] Reg6[20:18] Reg6[23:21] Reg6[23:21] Reg6[23:21] Reg6[23:21] Reg6[23:21]
PULLUP/ PULLDN PU100, PD20
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD9
PU100, PD20
(Lv) (Hv)
DVDD9
PU100, PD20
(Lv) (Hv)
DVDD9
PRODUCT PREVIEW
PU20, PD20
(Lv) (Hv)
DVDD9
PU20, PD20
(Lv) (Hv)
DVDD9
PU20, PD20
(Lv) (Hv)
DVDD9
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
SPRS231B
December 2003 Revised March 2004
Introduction
Table 2-4. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME GPIO6 SPI.CS1 MCBSP3.ESX TIMER.EVENT3 MCSI1.DIN GPIO4 SPI.CS2 MCBSP3.FSX TIMER.EVENT4 GPIO3 SPI.CS3 MCBSP3.FSX LED1 ETM.PSTAT[3] GPIO2 SPI.CLK ETM.PSTAT[4] GPIO1 UART3.RTS GPIO0 SPI.RDY USB.VBUS SPIF.DOUT MMC2.CLKIN MPUIO5 LOW_PWR UART3.RTS UART1.DTR
TYPE
CTRL SETTING Reg6[26:24] Reg6[26:24] Reg6[26:24] Reg6[26:24] Reg6[26:24] Reg6[26:24] Reg6[29:27] Reg6[29:27] Reg6[29:27] Reg6[29:27] Reg7[2:0] Reg7[2:0] Reg7[2:0] Reg7[2:0] Reg7[2:0] Reg7[5:3] Reg7[5:3] Reg7[5:3] Reg7[8:6] Reg7[8:6] Reg7[11:9] Reg7[11:9] Reg7[11:9] Reg7[11:9] Reg7[11:9] Reg7[14:12] Reg7[14:12] Reg7[14:12] Reg7[14:12]
PULLUP/ PULLDN PD100, PU20
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD9
PD100, PU20
(Lv) (Hv)
DVDD9
PU100, PD20
(Lv) (Hv)
DVDD9
PU100, PD20
(Lv) (Hv)
DVDD9
PU100, PD20 PU20, PD20
(Lv) (Hv) (Lv) (Hv)
DVDD9 DVDD9
PU20, PD20
(Lv) (Hv)
DVDD9
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
December 2003 Revised March 2004
SPRS231B
PRODUCT PREVIEW
Introduction
Table 2-4. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME MPUIO4 EXT_DMA_REQ1 LED2 UWIRE.CS2 SPIF.CS2 MCBSP3.DR MPUIO2 EXT_DMA_REQ0 UWIRE.CS1 SPIF.CS1 MPU_RST MPUIO14 MPUIO1 RTCK SPIF.SCK I2C.SCL I2C.SDA GPIO48 UWIRE.SDI UART3.DSR UART1.DSR MCBSP3.DR SPIF.DIN GPIO47
TYPE I/O/Z I/O/Z
CTRL SETTING Reg7[17:15] Reg7[17:15] Reg7[17:15] Reg7[17:15] Reg7[17:15] Reg7[17:15] Reg7[20:18] Reg7[20:18] Reg7[20:18] Reg7[20:18] Reg9[8:6] Reg9[8:6] Reg7[23:21] Reg7[23:21] Reg7[23:21] Reg7[26:24] Reg7[29:27] Reg7[29:27] Reg8[2:0] Reg8[2:0] Reg8[2:0] Reg8[2:0] Reg8[2:0] Reg8[2:0]
PULLUP/ PULLDN PU20, PD20
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD9
PU100, PD20
(Lv) (Hv)
DVDD9
(Lv) (Hv) PU100, PD20 (Lv) (Hv)
DVDD9 DVDD9
PRODUCT PREVIEW
(Lv) (Hv) (Lv) (Hv) PU20, PD20 (Lv) (Hv)
DVDD9 DVDD9 DVDD9
Input, Output, High-Impedance PD20 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 20-µA internal pullup, PU100 100-µA internal pullup voltage (1.65 High voltage (2.5 Standard LVCMOS input/output Terminal gated BFAIL SUBLVDS input/ouput Terminal gated GPIO9 MPUIO3 transceiver input/ouput Terminal gated BFAIL OMAP5912 Internal Reset input/output buffers Terminal 3-stated BFAIL input Analog oscillator terminals MCSI1.DOUT forced into high-impedance Boundary-scannable terminal state OMAP5912 HIGH_IMP3 control Output buffer includes serial resistor match with line impedance ensure proper signal integrity High-Impedance, Low-Impedance (pin driven), Output driven high, Output driven NOTES: denotes multiplexing ball `Regx' denotes terminal multiplexing register that controls specified terminal where Regx FUNC_MUX_CTRL_x
SPRS231B
December 2003 Revised March 2004
Introduction
Table 2-4. Package Terminal Characteristics (Continued)
BALL SIGNAL NAME UWIRE.SDO UART3.DTR UART1.DTR MCBSP3.DX UART3.RTS MCBSP3.DXZ SPIF.DOUT GPIO46 UWIRE.SCLK KB.C[7] MPUIO1 UART3.CTS Z_STATE UWIRE.CS0 MCBSP3.CLKX UART3.TX SPIF.CS0 GPIO45 Z_STATE UWIRE.CS3 KB.C[6] SPIF.CS3 UART3.RX Z_STATE GPIO44 BFAIL/EXT_FIQ UART3.CTS UART1.DSR MMC2.DATDIR1 AA20
TYPE
CTRL SETTING Reg8[5:3] Reg8[5:3] Reg8[5:3] Reg8[5:3] Reg8[5:3] Reg8[5:3] Reg8[5:3] Reg8[5:3] Reg8[8:6] Reg8[8:6] Reg8[8:6] Reg8[8:6] Reg8[11:9] Reg8[11:9] Reg8[11:9] Reg8[11:9] Reg8[11:9] Reg8[14:12] Reg8[14:12] Reg8[14:12] Reg8[14:12] Reg8[14:12] Reg8[14:12] Reg8[14:12] Reg8[17:15] Reg8[17:15] Reg8[17:15] Reg8[17:15] Reg9[11:9] Reg9[11:9] Reg8[11:9]
PULLUP/ PULLDN PU20, PD20
BUFFER (Lv) (Hv)
RESET STATE#
SUPPLY DVDD9
PU20, PD20
(Lv) (Hv)
DVDD9
PU20, PD20
(Lv) (Hv)
DVDD9
PU20, PD20
(Lv) (Hv)
DVDD9
RST_OUT GPIO41
PU20, PD20
(Lv) (Hv)
DVDD9
Input, Output, High-Impedanc

Literature Number: SPRS231B December 2003 Revised March 2004 PROD

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