REALTEK SINGLE CHIP OCTAL 10/100 MBPS FAST ETHERNET TRANSCEIVER RTL820

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REALTEK SINGLE CHIP OCTAL 10/100 MBPS FAST ETHERNET TRANSCEIVER RTL820

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RTL8208
REALTEK SINGLE CHIP OCTAL 10/100 MBPS FAST ETHERNET TRANSCEIVER RTL8208
Features. General Description Block Diagram. Assignments Description Media Connection Pins Power Ground Pins. Miscellaneous Pins. RMII/SMII/SS-SMII Pins (Serial Management Interface) Pins Pins Mode Control Pins Reserved Pins Register Descriptions Register Control Register1: Status. Register2: Identifier Register Register3: Identifier Register Register4: Auto-Negotiation Advertisement. Register5: Auto-Negotiation Link Partner Ability. Register6: Auto-Negotiation Expansion. Functional Description General 7.1.1 (Serial Management Interface) 7.1.2 Port Pair Loop Back Mode (PP-LPBK). 7.1.3 Address 7.1.4 Auto-Negotiation 7.1.5 Full-Duplex Flow Control Initialization Setup. 7.2.1 Reset 7.2.2 Setup configuration. 10Base-T 7.3.1 Transmit Function. 7.3.2 Receive Function 7.3.3 Link Monitor. 7.3.4 Jabber. 7.3.5 Loopback 100Base-TX 7.4.1 Transmit Function. 7.4.2 Receive Function 7.4.3 Link Monitor 7.4.4 Baseline Wander Compensation 100Base-FX 7.5.1 Transmit Function. 7.5.2 Receive Function 7.5.3 Link Monitor 7.5.4 Far-End-Fault-Indication (FEFI) RMII/SMII/SS-SMII 7.6.1 RMII (Reduced MII) 7.6.2 SMII (Serial MII) 7.5.3 SS-SMII (Source Synchronous -Serial MII). Power Saving Power Down Mode 7.7.1 Power Saving Mode 7.7.2 Power Down Mode. Configuration 7.8.1 Blinking Time 7.8.2 Serial Stream Order 7.8.3 Bi-Color 2.5V Power Generation. Design Layout Guide General Guidelines. Differential Signal Layout Guidelines Clock Circuit 2.5V power. Power Planes Ground Planes Transformer Options Application information 10Base-T/100Base-TX Application. 100Base-FX Application. Electrical Characteristics 10.1 Absolute Maximum Ratings 10.2 Operating Range 10.3 Characteristics 10.4 Characteristics 10.5 Digital Timing Characteristics 10.6 Thermal Data. Mechanical Dimensions
2001/01/07
Rev.1.923
RTL8208
Features
Supports 8-port integrated physical layer transceiver 10Base-T 100Base-TX ports support 100Base-FX Reduced 100Base-FX interface (patented) Robust baseline wander correction improved 100BASE-TX performance Fully compliant with IEEE 802.3/802.3u IEEE 802.3u compliant Auto-negotiation 10/100 Mbps control Hardware controlled Flow control advertisement ability Supports RMII/SMII/SS-SMII interfaces Multiple driving capabilities RMII/SMII/SS-SMII Supports 25MHz crystal clock source RMII with 50MHz REFCLK output Very power consumption Supports port-pair loop mode (PP-LPBK mode) Supports Power reduction methods: Power saving mode (cable detection) Power down mode Power-on auto reset function eliminates need external reset circuits Flexible display modes through 2-wire serial control interface 128-pin PQFP 2.5V/3.3V power supply 0.25µm, CMOS technology
General Description
RTL8208 highly integrated port, 10Base-T/100Base-TX/FX, Ethernet transceiver implemented 0.25µm CMOS technology. currently world's smallest Octal-PHY chip package with many special patented features. Traditional pins 100Base-FX omitted Realtek patent obtain fewer pin-count. Flexible hardware settings provided configure various operating modes chip. RTL8208 consists separate independent channels. Each channel consists RMII/SMII/SS-SMII interface controller, hardware pins used configure interface RMII, SMII, SS-SMII mode. RMII mode, another hardware used port-pair loop mode (PP-LPBK mode), which extend physical transmission length perform physical media transport operations without switch controller. addition, RTL8208 features very power consumption, (max.). Additionally, pin-outs designed provide optimized direct routing implemented, which simplifies layout work reduces noise issues.
2001/01/07
Rev.1.923
RTL8208
Block Diagram
nput
EESCRAM ADAPTI EQUALI
E[1:
CLOCK RECOVERY
SERI TOAL- PARALLE
nput
enabl
ENCODER
SCAM
PARALLEL- SERI
P-SC
ITTER
2001/01/07
Rev.1.923
2001/01/07
CRS_DV[0] TX_EN[0] TXON[1] RXD0[0] RXD1[0] TXD0[0] TXD1[0] TXON[0] TXOP[0] VDDAH VDDAH VCTRL VDDAL RXIN[0] RXIP[0] MDIO IBREF VSSA VDDAH TXOP[1] TXD0[1] TXD1[1] CRS_DV[1] RXD0[1] RXD1[1] TX_EN[2] TXD0[2] TXD1[2] CRS_DV[2] RXD0[2] RXD1[2] TX_EN[3] TXD0[3] TXD1[3] CRS_DV[3] RXD0[3] RXD1[3] RX_SYNC TX_SYNC TX_EN[4] TXD0[4] TXD1[4] CRS_DV[4] RXD0[4] RXD1[4] TX_EN[5] TXD0[5] TXD1[5] CRS_DV[5] RXD0[5] RXD1[5] VSSA RXIP[1] RXIN[1] VDDAL VDDAL RXIN[2] RXIP[2] VSSA TXOP[2] TXON[2] VDDAH VDDAH TXON[3] TXOP[3] VSSA RXIP[3] RXIN[3] VDDAL VDDAL RXIN[4] RXIP[4] VSSA TXOP[4] TXON[4] VDDAH VDDAH TXON[5] TXOP[5] VSSA RXIP[5] RXIN[5] VDDAL VDDAL RXIN[6] RXIP[6] VSSA TXOP[6] TXON[6] TX_EN[1]
Assignments
RTL8208
08042T1
050A TAIWAN
VSSA VDDAL RXIP[7] RXIN[7] VDDAH VDDAH TXD1[7] RXD1[7] RXD0[7] TXOP[7] TXON[7] RESET# REFCLK LED_CLK LED_DATA CRS_DV[7]
TXD0[7] TX_EN[7]
TXD1[6]
TXD0[6]
RXD1[6]
RXD0[6]
TX_EN[6]
CRS_DV[6]
RTL8208
Rev.1.923
RTL8208
stands input; stands output; stands analog; stands digital Name
VSSA RXIP[1] RXIN[1] VDDAL VDDAL RXIN[2] RXIP[2] VSSA TXOP[2] TXON[2] VDDAH VDDAH TXON[3] TXOP[3] VSSA RXIP[3] RXIN[3] VDDAL VDDAL RXIN[4] RXIP[4] VSSA TXOP[4] TXON[4] VDDAH VDDAH TXON[5] TXOP[5] VSSA RXIP[5] RXIN[5] VDDAL VDDAL RXIN[6] RXIP[6] VSSA TXOP[6] TXON[6] VDDAH VDDAH TXON[7] TXOP[7] VSSA RXIP[7] RXIN[7] VDDAL RESET# REFCLK LED_DATA/LEDMODE[1] LED_CLK/LEDMODE[0] RXD1[7] RXD0[7]/DRIVE[0] CRS_DV[7]/MODE[0] TXD1[7] TXD0[7] TX_EN[7] RXD1[6]/DISBLINK RXD0[6]/DRIVE[1] CRS_DV[6]/MODE[1] TXD1[6] TXD0[6] TX_EN[6]
Pin#
Type
AGND AVDD AVDD AGND AVDD AVDD AGND AVDD AVDD AGND AVDD AVDD AGND AVDD AVDD AGND AVDD AVDD AGND AVDD DVDD DGND
Name
RXD1[5]/LED_BLNK_TIME RXD0[5] CRS_DV[5]/TP_PAUSE TXD1[5] TXD0[5] TX_EN[5] RXD1[4]/PHY_ADDR[4] RXD0[4] CRS_DV[4]/RX_CLK TXD1[4] TXD0[4] TX_EN[4]/TX_CLK SYNC/TX_SYNC RX_SYNC/RPT_MODE RXD1[3]/PHY_ADDR[3] RXD0[3] CRS_DV[3]/FX_PAUSE TXD1[3] TXD0[3] TX_EN[3] RXD1[2]/TEST RXD0[2] CRS_DV[2]/FX_DUPLEX TXD1[2] TXD0[2] TX_EN[2] RXD1[1] RXD0[1] CRS_DV[1]/SEL_TXFX[1] TXD1[1] TXD0[1] TX_EN[1] RXD1[0] RXD0[0] CRS_DV[0]/SEL_TXFX[0] TXD1[0] TXD0[0] TX_EN[0] MDIO VCTRL VDDAH IBREF VDDAL RXIN[0] RXIP[0] VSSA TXOP[0] TXON[0] VDDAH VDDAH TXON[1] TXOP[1]
Pin#
Type
DVDD DGND DVDD DGND DVDD DGND DVDD DGND DGND AVDD AVDD AGND AVDD AVDD
2001/01/07
Rev.1.923
RTL8208
Description
order reduce count, therefore size cost, some pins have multiple functions. those cases, functions separated with symbol. Refer Assignment diagram graphical representation. stands input stands output stands analog signal stands digital signal stands power stands ground 'Pu' stand internal pull (75K ohm) 'Pd' stand internal pull down (75K ohm)
Media Connection Pins
Name RXIP[7:0] RXIN[7:0] TXOP[7:0] TXON[7:0] 44,35,30,21,16, 7,2,121 45,34,31,20,17, 6,3,120 42,37,28,23,14, 9,128,123 41,38,27,24, 13,10,127,124 Type Description Receiver Input: Differential positive signal shared 100Base-TX, 100Base-FX, 10Base-T. Receiver Input: Differential negative signal shared 100Base-TX, 100Base-FX, 10Base-T. Transmitter Output: Differential positive signal shared 100Base-TX, 100Base-FX, 10Base-T. Transmitter Output: Differential negative signal shared 100Base-TX, 100Base-FX, 10Base-T.
Power Ground Pins
Name VDDAH VDDAH VDDAL VSSA 11,12,25,26,39, 40,125,126 119,4,5,18,19,3 2,33,46 122,18,15,22,2 9,36,43 57,71,79,89, 58,72,82,90, 104,111 Type Description Power IBREF 3.3V Power analog: Used transmitters equalizers. 2.5V Power analog: Used circuits. Analog ground Digital 2.5V power supply Digital ground
2001/01/07
Rev.1.923
RTL8208
Miscellaneous Pins
Name RESET# REFCLK Type (Pu) Description Reset: This active input. complete reset function, this must asserted least 10ms. 25MHz Crystal 25MHz Oscillator clock input: When pulled low, must floating. REFCLK will then chip clock input. 25MHz Crystal Reference clock: 25MHz active, REFCLK 50MHz output. pulled-low (disabled), REFCLK clock input below: 50MHz 100ppm clock input RMII mode. 125MHz 100ppm clock input SMII/SS-SMII mode. Reference Bias Resistor: This must tied analog ground through external 1.96K resistor when using transformer Tx/Rx. Voltage control: This controls transistor generate 2.5V power supply VDDAL pins.
IBREF VCTRL
2001/01/07
Rev.1.923
RTL8208
RMII/SMII/SS-SMII Pins
Name TXD0[7:0] 55,63,69,77, 87,95,101,109 Type Description Transmit Data Input (bit RMII, TXD0 TXD1 di-bits input transmitted driven synchronously REFCLK from MAC. SMII, TXD0 inputs data that transmitted driven synchronously REFCLK. 100Mbps, TXD0 inputs 10-bit segment starting with SYNC. 10Mbps, TXD0 must repeat each 10-bit segment times. SS-SMII, TXD0 behaves SMII except synchronous TX_CLK instead REFCLK 10-bit segment starting with TX_SYNC instead SYNC. Transmit Data Input (bit RMII, TXD1 TXD0 input di-bits synchronously REFCLK. SMII/SS-SMII, TXD1 used should tied either high low. Transmit Enable: RMII TX_EN indicates di-bits valid synchronous REFCLK. SMII/SS-SMII, TX_EN[7:0] used. Receive Data Input (bit RMII, RXD0 RXD1 output di-bits synchronously REFCLK. SMII, RXD0 outputs data inband management information synchronously REFCLK. 100Mbps, RXD0 outputs 10-bit segment starting with SYNC. 10Mbps, RXD0 must repeat each 10-bit segment times. SS-SMII, RXD0 behaves SMII except synchronous RX_CLK instead REFCLK 10-bit segment starting with RX_SYNC instead SYNC. Receive Data Input (bit RMII, RXD1 RXD0 output di-bits synchronously REFCLK. SMII/SS-SMII, RXD1is used they driven low. Carrier Sense Data Valid: RMII, CRS_DV asynchronous REFCLK asserts when medium non-idle. SMII/SS-SMII, CRS_DV[7:0] used driven low. Receive Clock: SS-SMII, CRS_DV[4] RMII used RX_CLK, which 125MHz clock output. Receive Synchronous SS-SMII, RX_SYNC sync signal used delimit 10-bit segment RXD0 ports. Sync/Transmit Synchronous: SMII, SYNC sync signal used delimit 10-bit segment RXD0 TXD0 ports. SS-SMII, TX_SYNC sync signal used delimit 10-bit segment TXD0 ports. Transmit Clock/Transmit Enable: SS-SMII, TX_EN[4] RMII used TX_CLK, which 125MHz clock input from MAC.
TXD1[7:0]
54,62,68,76, 86,94,100,108
TX_EN [7:0]
56,64,70,78, 88,96,102,110 52,60,66,74, 84,92,98,106
RXD0[7:0]
RXD1[7:0] CRS_DV[7:0]
51,59,65,73, 83,91,97,105 53,61,67,75, 85,93,99,107
RX_CLK/ CRS_DV[4] RX_SYNC
SYNC/ TX_SYNC TX_CLK/ TX_EN[4]
2001/01/07
Rev.1.923
RTL8208
(Serial Management Interface) Pins
Name MDIO Type I/O, (Pu) Description Management Data I/O. Bi-directional data interface. 1.5K pull-up resistor required specified IEEE802.3u). controller access registers should delayed least 700us after completion reset because internal reset operation RTL8208 Management Data Clock. 25MHz clock sourced sample MDIO. controller access registers should delayed least 700us after completion reset because internal reset operation RTL8208
(Pd)
Pins
Name LED_DATA/ LEDMODE[1] Type Description LED_DATA outputs serial status bits that shifted into shift register displayed LEDs. LED_DATA output synchronously LED_CLK. This latched upon reset LEDMODE[1] LEDMODE[1:0] controls forms serial statuses. operation mode section. LED_CLK outputs reference clock serial signals. This latched upon reset LEDMODE[0]
LED_CLK/ LEDMODE[0]
2001/01/07
Rev.1.923
RTL8208
Mode Control Pins
Name SEL_TXFX[1:0]/ CRS_DV[1:0] 99,107 Type Description I/O, Select 10/100BaseTX 100BaseFX: (default 2'b00) (Pd,Pd) RPT_MODE 2'b00: ports (port0~port7) 10Base-T/100Base-TX. 2'b01: Port 100FX, other ports 10Base-T/100Base-TX. 2'b10: Ports 100FX, other ports 10Base-T/100Base-TX. 2'b11: ports 100Base-FX. RPT_MODE 2'b00: ports (port0~port7) 10Base-T/100Base-TX. 2'b01: Port 100FX, others 10Base-T/100Base-TX. 2'b10: Ports 1,3,5&7 100FX, others 10Base-T/100Base-TX. 2'b11: ports 100Base-FX. I/O, Port Pair Loop Back mode: (default (Pd) Upon power-on reset, this input assert PP-LPBK mode. When set, eight ports port-pair looped back, acting like signal regeneration/transformation repeater. Refer section covering PP-LPBK mode. I/O, Address: (default 2'b01) These 2bits determine highest (Pd,Pu) 2bits 5-bit address upon reset. I/O, Select RMII/SMII/SS-SMII mode: (default 2'b11) (Pu,Pu) 2'b1x: RMII 2'b00: SMII 2'b01: SS-SMII I/O, Twisted Pair Pause capability: (default Sets Flow control (Pu) ability Reg.4.10 ports upon power-on reset. With flow control ability. Without flow control ability I/O, 100Base-FX Flow control capability: (default Forces flow (Pu) control capability Reg.4.10 Reg.5.10 upon power-on reset. With flow control ability 100Base-FX. Without flow control ability 100Base-FX. I/O, FX_DUPLEX: Force 100Base-FX Full Duplex Mode: (default (Pu) This sets 100Base-FX duplex affects those ports 100Base-FX mode. 1=full duplex, 0=half duplex. Upon reset, this sets default values Reg.0.8 those ports 100Base-FX. I/O, Disable power-on reset LEDs blinking: (default (Pd) 1=Disable power-on blinking 0=blink. I/O, blink time: (default Used control blinking speed (Pu) activity collision LEDs. 43ms 120ms LEDMODE[1:0]: (default Controls forms serial status. (Pd,Pd) LEDMODE Mode Output 2'b00 3-bit serial stream Col/Fulldup, Link/Act, 2'b01 2-bit serial stream Spd, Link/Act 2'b10 3-bit Bi-color Col/Fulldup, Link/Act, operation mode section more information.
PP-LPBK mode RX_SYNC
PHY_ADDR[4:3]/ RXD1[4:3] MODE[1:0]/ CRS_DV[6:7] TP_PAUSE/ CRS_DV[5] FX_PAUSE/ CRS_DV[3] FX_DUPLEX/ CRS_DV[2]
73,83 61,53
DISBLINK/ RXD1[6] LED_BLNK_TIME/ RXD1[5] LEDMODE[1:0]
49,50
2001/01/07
Rev.1.923
RTL8208
Name DRIVE[0]/ RXD0[7] DRIVE[1]/ RXD0[6] Description DRIVE[0]: Controls output driving ability SSMII RX_CLK. 1'b0: 12mA (default) 1'b1: 16mA I/O, DRIVE[1]: Controls output driving abilities (Pd,Pd) RMII/SMII/SS-SMII signals other than RX_CLK. Drive [1:0] 2'b00 2'b01 2'b10 2'b11 Output driving ability (default) 12mA 16mA Type I/O, (Pd)
Reserved Pins
Name ENANAPAR/ RXD1[1] TEST/ RXD1[2] CPRST/ RXD1[0] Type I/O, (Pd) I/O, (Pd) I/O, (Pd) Description Reserved internal use. Must kept floating. TEST. Reserved internal use. Must kept floating. Reserved internal use. Must kept floating.
2001/01/07
Rev.1.923
RTL8208
Register Descriptions
first registers defined specification. Other registers defined Realtek Semiconductor Corp. internal reserved specific uses. Register Description Default Control Register 3100 Status Register 0F49 Identifier Register 001C Identifier Register C883 Auto-Negotiation Advertisement Register 05E1 Auto-Negotiation Link Partner Ability Register 0001 Auto-Negotiation Expansion Register 0000 Read Only Read/Write Latch until cleared Latch High until cleared Self Clearing
Register Control
Reg. 0.15 0.14 Name Reset Loopback Description 1=PHY reset. This self-clearing. This will loopback ignore activities cable media. Valid only 10Base-T. 1=Enable loopback. 0=Normal operation. When Nway enabled, this reflects result Auto-negotiation. (Read only) When Nway disabled, this SMI*. (Read/Write) When 100FX enabled, this (Read only) 1=100Mbps. 0=10Mbps. This through SMI.(Read/Write) When 100FX enabled, this (Read only) Enable Auto-negotiation process. disable Auto-negotiation process. 1=Power down. functions will disabled except SMI.read/write function. 0=Normal operation. Electrically isolate from RMII/SMII/SS-SMII. still able respond MDC/MDIO. Normal operation 1=Restart Auto-Negotiation process. 0=Normal operation. When Nway enabled, this reflects result Auto-negotiation. (Read only) When Nway disabled, this SMI*. (Read/Write) When 100FX enabled, this determined FX_DUPLEX pin. (Read/Write) 1=Full duplex operation. 0=Half duplex operation. Mode RW/SC Default
0.13
Spd_Sel
0.12
Auto Negotiation Enable Power Down Isolate Restart Auto Negotiation Duplex Mode
100FX
0.11 0.10
RW/SC
0.[7:0]
Reserved
*SMI: Serial Management Interface which composed MDC,MDIO, allows manage PHY.
2001/01/07
Rev.1.923
RTL8208
Reset order reset RTL8208 software control, must written using write operation. clears itself after reset process complete, does need cleared using second write. Writes other Control register bits will have effect until reset process completed, which requires approximately 1us. Writing this effect. Because this self clearing after cycles from write operation, will return when read. Loopback RTL8208 placed into loopback mode writing Loopback mode cleared either writing resetting chip. When this read, will return when chip software-controlled loopback mode, otherwise will return `0'. Speed Selection Auto-negotiation enabled, this effect speed selection. However, Auto-negotiation disabled software control, operating speed RTL8208 forced writing appropriate value Writing this forces 100Base-X operation, while writing forces 10Base-T operation. When this read, returns value software controlled forced speed selection only. Auto Negotiation Enable Default Auto Negotiation enable ports disable ports. Auto-negotiation disabled either software control 0.12=0. Power Down RTL8208 supports power mode which intended decrease power consumption. Writing will enable power down mode, writing will return RTL8208 normal operation. When read, this register will return when power down mode, during normal operation. Isolate Each individual isolated from writing outputs will tri-stated inputs will ignored. Since management interface still active, isolate mode cleared either writing resetting chip. When this read, will return when chip isolate mode, during normal operation. Restart Auto Negotiation self-clearing that allows Auto-negotiation process restarted, regardless current status Auto-negotiation state machine. order this have effect, Auto-negotiation must enabled. Writing this restarts Auto-negotiation while writing this effect. When this read, will always return `0'. Duplex Mode default, RTL8208 powers half duplex mode. chip forced into full duplex mode writing while Auto-negotiation disabled. Half duplex mode resumed either writing resetting chip. When Nway enabled, this reflects results Auto-negotiation, read only mode. When Nway disabled, this through SMI, read/write mode. When 100FX enabled, this through FX_DUPLEX read/write mode. Reserved Bits reserved register bits must written times. Ignore RTL8208 output when these bits read.
2001/01/07
Rev.1.923
RTL8208
Register1: Status
Reg. 1.15 1.14 1.13 1.12 1.11 1.[10:7] Name 100Base_T4 100Base_TX_FD 100Base_TX_HD 10Base_T_FD 10Base_T_HD Reserved Preamble Suppression Auto-negotiate Complete Remote Fault Description 100Base-T4 capability. 1=100Base-TX full duplex capable. 0=Not 100Base-TX full duplex capable. 1=100Base-TX half duplex capable. 0=Not 100Base-TX half duplex capable. 1=10Base-TX full duplex capable. 0=Not 10Base-TX full duplex capable. 1=10Base-TX half duplex capable. 0=Not 10Base-TX half duplex capable. RTL8208 will accept management frames with preamble suppressed. 1=Auto-negotiation process completed. Reg.4,5 valid this set. 0=Auto-negotiation process completed. 1=Remote fault indication from link partner been detected. 0=No remote fault indication detected. When 100FX mode, this means in-band signal Far-End-Fault detected. Refer MODE section. 1=Nway Auto-negotiation capable. (permanently 0=Without Nway Auto-negotiation capability. 1=Link never failed since previous read. 0=Link failed since previous read. link fails, this will until read. 1=Jabber detected. 0=No Jabber detected. jabber function disabled 100Base-X mode. Jabber supported only 10Base-T mode. 1=Extended register capable. (permanently 0=Not extended register capable. Mode RO/LH Default
Auto-Negotiation Ability Link Status Jabber Detect
RO/LL RO/LH
Extended Capability
100Base_T4 RTL8208 does support function. reads this will return `0'. 100Base_TX_FD RTL8208 capable operating 100Base-TX full duplex mode. 100Base_TX_HD RTL8208 capable operating 100Base-TX half duplex mode. 10Base_T_FD RTL8208 capable operating 10Base-T full duplex mode. 10Base_T_HD RTL8208 capable operating 10Base-T half duplex mode. Reserved Ignore output RTL8208 when these bits read. Preamble Suppression Management Frame Preamble Suppression permanently RTL8208, allowing subsequent management frames accepted with without standard preamble pattern. Only preamble bits required between successive management commands, instead normal however, minimum preamble bits required first read/write transaction after reset. idle required between management transactions defined IEEE802.3u spec). Reads this will always return `1'. Auto-negotiate Complete will return Auto-negotiation process been completed contents registers valid. Remote Fault When link partner detect far-end fault, would send far-end indication stream pattern. When RTL8208 receive this pattern, Reg1.4=1. Auto-Negotiation Ability RTL8208 capable performing IEEE Auto-negotiation, will return when read, regardless whether Auto-negotiation function been disabled. Link Status RTL8208 will return when link state machine Link Pass, indicating that valid link been established. Otherwise, will return `0'. When link failure occurs after link pass state been entered, Link 2001/01/07 Rev.1.923
RTL8208
Status will latched will remain until read. After read, becomes Link Pass state been entered again. Jabber Detect RTL8208 will return jabber condition been detected. After read, chip reset, reverts `0'. This 10Base-T only. Jabber occurs when predefined excessive long packet detected 10Base-T. When duration TX_EN exceeds jabber timer (21ms), transmit loopback functions will disabled starts blinking. After TX_EN goes more than transmitter will re-enabled stops blinking. Extended Capability RTL8208 supports extended capability registers, will return when read. Several extended registers have been implemented RTL8208.
Register2: Identifier Register
Identifier Registers together form unique identifier section this device. Identifier consists concatenation Organizationally Unique Identifier (OUI), vendor's model number model revision number. return value zero each bits Identifier desired. Identifier intended support network management. Reg. 2.[15:0] Name Description Composed 18th bits Organizationally Unique Identifier (OUI), respectively. Mode Default 001C
Register3: Identifier Register
Reg. 3.[15:10] 3.[9:4] 3.[3:0] Name Model Number Revision Number Description Assigned 19th through 24th bits OUI. Manufacturer's model number Manufacturer's revision number Mode Default 110010 001000 0011
2001/01/07
Rev.1.923
RTL8208
Register4: Auto-Negotiation Advertisement
This register contains advertisement abilities this device they will transmitted Link Partner during Auto-negotiation. Reg. Name Description Mode Default 4.15 Next Page 1=Next Page enabled. 0=Next Page disabled. (Permanently 4.14 Acknowledge Permanently 4.13 Remote Fault 1=Advertises that RTL8208 detected remote fault. 0=No remote fault detected. 4.[12:11] Reserved 4.10 Pause 1=Advertises that RTL8208 flow control capability. 0=Without flow control capability. TP_PAUSE 100FX mode, this 100FX_PAUSE upon reset. 100/10TP mode, this TP_PAUSE upon reset. FX_PAUSE 100Base-T4 100Base-T4 capable. 100Base-T4 capable. (Permanently 100Base-TX-FD 1=100Base-TX full duplex capable. 0=Not 100Base-TX full duplex capable. 100Base-TX 1=100Base-TX half duplex capable. 0=Not 100Base-TX half duplex capable. 10Base-T-FD 1=10Base-TX full duplex capable. 0=Not 10Base-TX full duplex capable. 10Base-T 1=10Base-TX half duplex capable. 0=Not 10Base-TX half duplex capable. 4.[4:0] Selector Field [00001]=IEEE802.3 00001 Next Page RTL8208 does implement Next Page function, will always return when read. Acknowledge Because Next Page function implemented, will always return when read. Remote Fault When RTL8208 receive valid signal Reg4.13=1. RTL8208 advertises this information inform link partner. Reserved Ignore output RTL8208 when these bits read. Pause -Setting this indicates availability Flow Control capabilities when full duplex operation use. This used communicate Pause Capability Link Partner effect operation. 100Base-T4 Because RTL8208 does support function, reads this will return `0'. 100Base-TX-FD This advertises ability Link Partner that RTL8208 operate 100Base-TX full duplex mode. Writing this will suppress transmission this ability Link Partner. Resetting chip will restore default value. default value writing will this `1'. Reading this will return last written value default value write been completed since last reset. 100Base-TX This advertises ability Link Partner that RTL8208 operate 100Base-TX half duplex mode. Writing this will suppress transmission this ability Link Partner. Resetting chip will restore default value. default value writing will this `1'. Reading this will return last written value default value write been completed since last reset. 10Base-T-FD This advertises ability Link Partner that RTL8208 operate 10Base-T full duplex mode. Writing this will suppress transmission this ability Link Partner. Resetting chip will restore default value. default value writing will this `1'. Reading this will return last written value default value write been completed since last reset. 10Base-T This advertises ability Link Partner that RTL8208 operate 10Base-T half duplex mode. Writing this will suppress transmission this ability Link Partner. Resetting chip will restore default value. default value writing will this `1'. Reading this will return last written value default value write been completed since last reset. Selector Field Bits contain fixed value 00001, indicating that chip belongs 802.3 class transceivers.
2001/01/07
Rev.1.923
RTL8208
Register5: Auto-Negotiation Link Partner Ability
This register contains advertised abilities Link Partner received during Auto-negotiation. content changes after successful Auto-negotiation. Reg. Name Description Mode Default 5.15 Next Page 1=Link partner desires Next Page transfer. 0=Link partner does desire Next Page transfer. 5.14 Acknowledge 1=Link Partner acknowledges reception words. 0=No acknowledgement Link Partner. 5.13 Remote Fault 1=Remote Fault indicated Link Partner. 0=No remote fault indicated Link Partner. 5.12-11 Reserved 5.10 Pause 1=Flow control supported Link Partner. 0=No flow control supported Link Partner. When Nway enabled, this reflects Link Partner ability. (read only) 100FX mode, this FX_PAUSE SMI. 100Base-T4 1=100Base-T4 supported Link Partner. 0=100Base-T4 supported Link Partner. 100Base-TX-FD 1=100Base-TX full duplex supported Link Partner. 0=100Base-TX full duplex supported Link Partner. 100FX mode, this when Reg.0.8=1 FX_DUPLEX When Nway disabled, this when Reg.0.13=1 Reg.0.8=1. 100Base-TX 1=100Base-TX half duplex supported Link Partner. 0=100Base-TX half duplex supported Link Partner. 100FX mode, this when Reg.0.8=0 FX_DUPLEX When Nway disabled, this when Reg.0.13=1 Reg.0.8=0. 10Base-T-FD 1=10Base-TX full duplex supported Link Partner. 0=10Base-TX full duplex supported Link Partner. When Nway disabled, this when Reg.0.13=0 Reg.0.8=1. 10Base-T 1=10Base-TX half duplex supported Link Partner. 0=10Base-TX half duplex supported Link Partner. When Nway disabled, this when Reg.0.13=0,and Reg.0.8=0. 5.[4:0] Selector Field [00001]=IEEE802.3 00001 Note that values only guaranteed valid once Auto-negotiation successfully completed, indicated Status Register. Next Page returns value when Link Partner implements Next Page function Next Page information that wants transmit. However, since RTL8208 does implement Next Page function, ignores Next Page bit, except copy this register. Acknowledge used Auto-negotiation indicate that device successfully received Link Partner's Link Code Word. Remote Fault returns value when Link Partner signals that detected remote fault. RTL8208 advertises this information, does upon Reserved Ignore output RTL8208 when these bits read. Pause Indicates that Link Partner pause set. 100Base-T4 Though RTL8208 does support function, this reflects this ability Link Partner. 100Base-TX-FD This indicates that Link Partner support 100Base-TX full duplex mode. This cleared time Auto-negotiation restarted RTL8208 reset. 100Base-TX This indicates that Link Partner support 100Base-TX half duplex mode. This cleared time 2001/01/07 Rev.1.923
RTL8208
Auto-negotiation restarted RTL8208 reset. 10Base-T-FD This indicates that Link Partner support 10Base-T full duplex mode. This cleared time Auto-negotiation restarted RTL8208 reset. 10Base-T This indicates that Link Partner support 10Base-T half duplex mode. This cleared time Auto-negotiation restarted RTL8208 reset. Selector Field Bits reflect value Link Partner's selector field. These bits cleared time Auto-negotiation restarted chip reset, generally reflect value 0001, indicating that Link Partner 802.3 device.
Register6: Auto-Negotiation Expansion
Reg. 6.[15:5] Name Reserved Parallel Detection Fault Link Partner Next Page Able Local Next Page Able Page Received Link Partner AutoNegotiation Able Description fault been detected Parallel Detection function. 0=No fault been detected Parallel Detection function. Link Partner Next Page able. Link Partner Next Page able. RTL8208 Next Page able. RTL8208 Next Page able. (permanently=0) Page been received. Page been received. Auto- Negotiation enabled, this means: Link Partner Auto-Negotiation able. Link Partner Auto-Negotiation able. 100FX Nway disabled, this always Mode RO/LH Default (AutoNegotiation) (100FX)
Reserved Ignore output RTL8208 when these bits read. Parallel Detection Fault read-only that gets latched high when parallel detection fault occurs Auto-negotiation state machine. further details, please consult IEEE standard. reset after register read, when chip reset. Link Partner Next Page Able returns when Link Partner Next Page capabilities. same value Link Partner Ability Register. Local Next Page Able RTL8208 does have Next Page capabilities, will always return when read. Page Received latched high when link code word received from Link Partner, checked acknowledged. This cleared when link lost chip reset. Link Partner Auto-Negotiation Able returns when Link Partner known have Auto-negotiation capabilities. Before Auto-negotiation information exchanged, Link Partner does comply with IEEE Auto-negotiation, returns value `0'.
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Functional Description
General
7.1.1 (Serial Management Interface)
(Serial Management Interface) also known Management Interface, which consists signals, MDIO MDC; allowing controller control monitor state PHY. clock input latch MDIO rising edge. clock from 25MHz. MDIO bi-directional connection used write data read data from PHY. address base pins PHY_ADDR[4:3] eight ports addresses RTL8208 internally 000,001,010,011,100,101,110,and 111. Read/Write Cycles Preamble bits) Read Write Start bits) Code bits) PHYAD bits) AAAAA AAAAA REGAD bits) RRRRR RRRRR TurnAround bits) Data bits) Idle
high-impedance. During idle time, MDIO state determined external 1.5K pull-up resistor.
RTL8208 supports Preamble Suppression, which allows issue Read/Write Cycles without preamble bits (but needs least Idle every cycle). However, first management cycle after power-on reset, 32-bit preamble needed. guarantee first successful transaction after power-on reset, should delayed least 700us issue first Read/Write Cycle relative rising edge reset.
7.1.2 Port Pair Loop Back Mode (PP-LPBK)
PP-LPBK mode enabled pulling high reset. When PP-LPBK mode, ports RTL8208 configured four pairs, port0 port1, port2 port3, port4 port5, port port7. Each pair RMII interface loop back, acting like signal regeneration /transformation repeater, switch controller necessary. PP-LPBK mode, port port selection different from that normal mode. port selection configuration follows: this table, means port, means Fiber port. PP-LPBK SEL_TXFX[1:0] mode (Pin 99,107) Port0, Port1 (Pin (normal mode) (PP-LPBK) Port2, Port3 Port4, Port5 Port6, Port7
Since this configuration loop back mode, uses Full duplex only, Half duplex supported. loop-back-pair ports should configured same Speed. Although this mode does effect normal N-Way mode, order keep same speed each pair's ports, there auto-detection scheme. This scheme specifies that port pair already linked, when other port linked later, earlier link-on port will re-start Auto-negotiation, trying keep ports linked same speed. When PP-LPBK mode set, there three requirements: must based upon RMII mode; switch controller connected; TX_EN[7:0] pulled down.
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7.1.3 Address
Each transceiver RTL8208 will have unique address management. address will through address pins. pins latched trailing reset. Transceiver will have address AA000, where AA=PHYAD [4:3]. Each internal address AA000, AA001, AA010, AA011, AA100, AA101, AA110, AA111. Every time write read operation executed, transceiver compares address with address definition, operation executed only when addresses match.
7.1.4 Auto-Negotiation
100/10 port, RTL8208 default setup Auto-Negotiation enabled. Setting Register 0.12=0 write disable Auto-Negotiation. 100FX port, Auto-Negotiation always disabled. Auto-Negotiation enabled port, RTL8208 will negotiate with link partner determine speed duplex status. RTL8208's ability advertised Register after Auto-Negotiation finished, link partner's ability will stored Register link partner Auto-Negotiation disabled, RTL8208 enters parallel-detection state identify speed link partner. RTL8208 will link same speed link partner, half duplex mode. Auto-Negotiation also used determine Full-duplex flow control. flow control ability advertised Register 4.10. link partner's flow control ability stored Register 5.10. following section more information.
7.1.5 Full-Duplex Flow Control
hardware TP_pause 100FX_pause enabled power-on reset, Register 5.10=1 Register 4.10=1. Therefore, after reset completed: When Auto-Negotiation enabled, Register 4.10 overwritten MAC, Register 5.10 updated after N-Way completed and, Register 5.10 read only MAC. When Auto-Negotiation disabled, Register 5.10 through interface. does write Register 5.10, still Register 5.10=1, which means hardware forced flow control enabled.
Initialization Setup
7.2.1 Reset
RTL8208 initialized while reset state. During reset, each transceiver will reset simultaneously. There ways reset RTL8208: Power-on auto reset; hardware reset; software reset. internal power-on auto reset circuit reset chip while reset (pin47) floating. hardware reset signal must asserted RESET#, least 100ms. software reset implemented writing Register 0.15=1, which self clearing.
7.2.2 Setup configuration
operational modes RTL8208 configured either hardware (pulled high low) upon reset software programming accessing RTL8208 registers through SMI. Refer register description sections.
10Base-T
7.3.1 Transmit Function
When TX_EN active, from RMII/SMII/SS-SMII serialized, Manchester-encoded, driven into network medium packet stream. on-chip filtering wave shaping circuit eliminates need external filtering. transmit function disabled when link failed when Auto-negotiation proceeds.
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7.3.2 Receive Function
Manchester decoder converts incoming serial stream when circuit detects signal digital serial stream then converted 2-bit (RMII) 1-bit (SMII/SS-SMII) data format. preamble incoming stream stripped regenerated. generated into once incoming detected data bits entering elastic buffer over threshold.
7.3.3 Link Monitor
10Base-T link pulse detection circuit constantly monitors RXIP/RXIN pins presence valid link pulses. Auto-polarity implemented correcting detected reverse polarity RXIP/RXIN signal pairs.
7.3.4 Jabber
Jabber occurs when TX_EN asserted over 21ms. Both transmit loopback functions disabled once jabber occurs. Register (Jabber detect) high until jabber disappears read again. Jabber function supported 10-Base-T only, implemented 100Base-TX. collision corresponding port will blink while Jabber occurs. Jabber dismissed after TX_EN remains least 500ms.
7.3.5 Loopback
Loopback mode achieved writing Register 0.14=1. Loopback mode routes transmitted data output NRZI conversion module, back receiving path. This mode used check device's connection 5-bit symbol bus, verify operation phase locked loop.
100Base-TX
internal 125MHz clock generated on-chip circuit synchronize transmit data generate clock signal incoming data stream.
7.4.1 Transmit Function
Upon detection TX_EN high, RTL8208 converts RMII/SMII/SS-SMII code-group substitutes code-groups first code-groups, which called Start Stream Delimiter (SSD). 4B5B coding continues data long TX_EN asserted high. TX_EN, code-groups appended last data field, which will stripped remote receiving side. During inter-packet gap, where TX_EN deasserted, IDLE code-groups transmitted sake clocking remote receiver. 5-bit serial data stream after 4B5B coding then scrambled defined TP-PMD Stream Cipher function flatten power spectrum energy such that effects significantly reduced. This multi-level signaling technology moves power spectrum energy from high frequency frequency, which also benefits emission. Scrambling implemented 100Base-FX.
7.4.2 Receive Function
receive path includes receiver composed adaptive equalizer restoration circuits. These circuits compensate incoming distortion MLT-3 signal. MLT-3 NRZI, NRZI converter used convert analog signals digital bit-streams. circuit also included clock data bits exactly with minimum error rate. De-scrambler, 5B/4B decoder serial-to-parallel conversion circuits follow. CRS_DV asserted later than when (Start-of-Stream-Delimiter) detected within bits time (delay elastic buffer mentioned RMII section), ends toggling once data elastic buffer been dumped RXD.
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Name Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000* 0101* 0101* 0000* 0000* 1000 0111 0111 0111 0111 0111 0111 0111 0111 0111 0111 Code 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 11111 11000 10001 01101 00111 00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001 Definition Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Idle Start stream Delimiter, Part Start stream Delimiter, Part stream Delimiter, Part stream Delimiter, Part Transmit Error (used force signaling errors) Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code
*Treated invalid code (mapped 0111) when received data field.
4B5B Encoding
7.4.3 Link Monitor
100Base-TX mode, receive signal energy detected monitoring receive pair transitions signal level. Signal levels qualified using squelch detect circuits. When signal valid signals detected receive pair, link monitor will enter remain "Link Fail" state where only idle codes will transmitted. When valid signal detected receive pair minimum period time, link monitor will enter "Link Pass" state transmit receive functions will enabled.
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RTL8208
7.4.4 Baseline Wander Compensation
RTL8208 ANSI TP-PMD compliant supports input Base Line Wander (BLW) compensation 100Base-TX mode. RTL8208 does require external attenuation circuitry receive inputs, RXIP/RXIN. accepts TP-PMD compliant waveforms directly, requiring only termination transformer. change average content, over time, coupled digital transmission over given transmission medium. result from interaction between frequency components transmitted stream frequency response coupling component(s) within transmission system. frequency content digital stream goes below frequency pole coupling transformers, then droop characteristics transformers will dominate resulting potentially serious BLW. compensated for, packet loss will occur.
100Base-FX
RTL8208 configured into 100Base-FX mode through SEL_TXFX[1:0] (RPT_MODE should According setting SEL_TXFX[1:0], port port eight ports configured 100Base-FX operation. RPT_MODE=0 SEL_TXFX[1:0] Port 2'b00 2'b01 2'b10 2'b11
UTP: 10Base-T/100Base-TX, 100Base-FX.
Port
Medium type Port2 Port3 Port4 Port5 Port6 Port7
Compared common 100Base-FX applications, RTL8208 lacks pair differential (signal detect) signals achieve link monitoring function (patent), which significantly reduces count this octal PHY. RTL8208 transceivers interface with external 100Base-FX fiber optic device receiver instead magnetics module used with twisted pair cable. differential transmit receive data pairs will operate PECL voltage levels instead those required twisted-pair transmission. data will encoded using two-level NRZI instead three-level MLT3. data stream scrambled fiber-optic transmission.
7.5.1 Transmit Function
100Base-FX transmission, processed 100Base-TX, except without scrambling, before NRZI stage. Instead converting MLT-3 signals, 100Base-TX, serial data stream driven NRZI PECL signals, which enter fiber transceiver differential-pairs form. fiber transceiver should available working 3.3V environment. Refer fiber application section more information. PECL characteristics Parameter PECL Input High Voltage PECL Input Voltage PECL Output High Voltage PECL Output Voltage Symbol Vdd-1.16 Vdd-1.81 Vdd-1.02 Vdd-0.88 Vdd-1.47 Vdd-1.62 Unit
7.5.2 Receive Function
Signals received through PECL receiver inputs from fiber transceiver, directly passed clock recovery circuit data/clock recovery. scrambler/descrambler bypassed 100Base-FX mode.
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7.5.3 Link Monitor
100Base-FX mode, RTL8208 receive path detects valid link word, enters link state. valid link word detected, link down state. Therefore, SD+/- necessary. RTL8208 uses reduced 100Base-FX interface.
7.5.4 Far-End-Fault-Indication (FEFI)
Register (Remote Fault indication detected) FEFI when 100FX enabled, which indicates FEFI been detected. FEFI alternative in-band signaling method which composed consecutive followed `0'. From point view RTL8208, once this pattern detected times, Register set, which means transmit path (Remote side's receive path) some problems. other hand, RTL8208 detects valid link pulse RxOP/N pair, sends FEFI stream pattern, which turn will cause remote side detect Far-End-Fault indication. This means RTL8208 sees problems receive path. FEFI mechanism used only 100Base-FX applications.
RMII/SMII/SS-SMII
interface RMII, SMII, SS-SMII through MODE[1:0]. When floating MODE[1:0] upon power-on reset, RTL8208 operates RMII mode (default). MODE[1:0] 2'b1x 2'b00 2'b01 Operation Mode RMII SMII SS-SMII REFCLK Clock input 50MHz, 100ppm 125MHz, 100ppm 125MHz, 100ppm
Below illustrates signals required each interface: RMII REFCLK SMII REFCLK SYNC SS-SMII REFCLK TX_SYNC RX_SYNC RX_CLK RXD0[7:0] RXD0[7:0]
CRS_DV[3:0] CRS_DV[4] CRS_DV[7:5] RXD0[7:0] RXD1[7:0] TX_EN[3:0] TX_EN[4] TX_EN[7:5] TXD0[7:0] TXD1[7:0]
TX_CLK TXD0[7:0] TXD0[7:0]
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7.6.1 RMII (Reduced MII)
RTL8208 meets RMII requirements outlined RMII Consortium specifications. main advantage introduced RMII count reduction; e.g., operates with only 50Mhz reference clock both sides without separate clocks needed both paths, with interface. However, some hardware modification needed this change, most important outstanding which presence elastic buffer absorption frequency difference between 50MHz reference clock clocking information incoming data stream. Another change implemented that RXDV Carrier_Sense merged into signal, CRS_DV, which asserted high while detecting incoming packet data. When internal Carrier_Sense de-asserted, CRS_DV de-asserted when first di-bit nibble presented onto RXD[1:0] synchronously REFCLK. there still data FIFO that been presented onto RXD[1:0], then second di-bit nibble CRS_DV reasserts. This pattern assertion de-assertion continues until received data FIFO been presented onto RXD[1:0]
CRS_DV[7:0] RXD0[7:0] RXD1[7:0]
CRS_DV[7:0] RXD0[7:0] RXD1[7:0]
RTL8208
TX_EN[7:0] TXD0[7:0] TXD1[7:0] REFCLK
8-port
RTL8208
TX_EN[7:0] TXD0[7:0] TXD1[7:0] REFCLK
8-port
25MHz
50MHz oscillator
RMII Signal Diagram 50MHz Oscillator Solution
RMII Signal Diagram 25MHz Crystal Solution
7.6.2 SMII (Serial MII)
RTL8208 also supports SMII interface MAC, which allows further reduction number signals. illustrated below, both RTL8208 synchronous 125MHz reference clock.
SYNC TXD0[7:0]
8-port
RTL8208
RXD0[7:0]
REFCLK
125MHz oscillator
SMII Signal Diagram
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RTL8208
Receive Path Receive data control information signaled 10-bit segments. SYNC signal used delimit 10-bit segments. responsible generate these SYNC pulses every clocks. 100Mbps mode, each segment represents byte data. However, 10Mbps mode, each segment repeated times represent byte data. receive sequence contains information defined standard receive path.
RX_DV RXD0 RXER from previous frame RXD1 Speed =10Mbps =100Mbps RXD2 Duplex Half Full RXD3 Link Down RXD4 RXD5 RXD6 RXD7
Jabber Upper Nibble False Carrier Invalid Detected Detected Valid
Data Byte (Two Data Nibbles)
SMII Reception Encoding
REFCLK
SYNC RXD[0] RXDV RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7
SMII Reception Transmit Path Transmit data control information signaled 10-bit segments. SYNC signal used delimit 10-bit segments. responsible generate these SYNC pulses every clocks. 100Mbps mode, each segment represents byte data. However, 10Mbps mode, each segment repeated times represent byte data.
TXER TXEN TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7
Data Byte (Two Data Nibbles)
SMII Transmission Encoding
REFCLK
SYNC
TX_ER
TX_EN
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
SMII Transmission Collision Detection RTL8208 does indicate that collision occurred. left detect assertion both CRS_DV TX_EN.
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7.5.3 SS-SMII (Source Synchronous -Serial MII)
Source-Synchronous SMII designed applications requiring trace delay more than 1ns. Three signals added SMII interface: RX_SYNC, RX_CLK, TX_CLK; SYNC SMII modified TX_SYNC SS-SMII.
TX_SYNC TXD0[7:0] TX_CLK
8-port
RX_SYNC RXD0[7:0] RX_CLK REFCLK
RTL8208
125MHz oscillator
SS-SMII Signal Diagram Receive Path Receive data control information signaled 10-bit segments. RX_SYNC signal used delimit 10-bit segments. RTL8208 responsible generate these RX_SYNC pulses every clocks. 100Mbps mode, each segment represents byte data. However, 10Mbps mode, each segment repeated times represent byte data. receive sequence contains information defined standard receive path.
RX_CLK
RX_SYNC RXD[0] RXDV RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7
SS-SMII Reception Transmit Path Transmit data control information signaled 10-bit segments. TX_SYNC signal used delimit 10-bit segments. responsible generate these TX_SYNC pulses every clocks. 100Mbps mode, each segment represents byte data. However, 10Mbps mode, each segment repeated times represent byte data. receive sequence contains information defined standard receive path. sample segments.
TX_CLK
TX_SYNC
TXD[0]
TX_ER
TX_EN
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
SS-SMII Transmission Collision Detection RTL8208 does indicate that collision occurred. left detect assertion both CRS_DV TX_EN. 2001/01/07 Rev.1.923
RTL8208
Power Saving Power Down Mode
7.7.1 Power Saving Mode
RTL8208 implements power saving mode port basis. port automatically enters power saving mode seconds after cable disconnected from regardless whether RTL8208's operation mode Nway Force mode. Once port enters power saving mode, transmits normal link pulses only TXOP/TXON pins keeps monitoring RXIP/RXIN detect incoming signals which might 100Base-TX MLT-3 idle pattern, 10Base-T link pulses Nway's (fast link pulses). After detects incoming signals, wakes from power saving mode operates normal mode according result connection. Power saving mode supported when 100FX operation.
7.7.2 Power Down Mode
Setting Register 0.11through interface forces corresponding port RTL8208 enter power down mode, which disables transmit/receive functions RMII functions that port, except (MDC/MDIO management interface).
Configuration
RTL8208 supports serial status streams display. forms status streams, shown below, controlled LEDMODE[1:0] pins, which latched upon reset. statuses represented active-low, except Link/Act Bi-color mode, whose polarity depends status. LEDMODE[1:0] Mode Output sequences 3-bit serial stream Col/Fulldup, Link/Act, 2-bit serial stream Spd, Link/Act 3-bit Bi-color Col/Fulldup, Link/Act, Statuses Col/Fulldup Link/Act Description Col, Full duplex Indicator. Blinking every 43ms when collision happens. full duplex, high half duplex mode. Link, Activity Indicator. 3-bit serial stream mode, link established. 3-bit Bi-color mode, Link/Act high link established when speed (100Mb/s); Link/Act link established when speed high (10Mb/s). Link/Act Blinks every 43ms when corresponding port transmitting receiving. Speed Indicator. 100Mb/s, high 10Mb/s.
7.8.1 Blinking Time
blinking time 120ms setting LED_BLNK_TIME=0. statuses supporting 43/120ms blinking time Col/Fulldup, Link/Act. status Link/Act/Spd, blinking time affected LED_BLNK_TIME.
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7.8.2 Serial Stream Order
Every stream output port port, from port0 port7 with Col/Fulldup first port stream. 2-bit serial stream mode, sequence Spd, then Link/Act. following diagrams illustrate sequences 3-bit 2-bit serial stream mode.
2.56 2.56 2.56 2.56 2.56 2.56 2.56 2.56 2.56
LEDCLK LEDDTA
Col/Dup
Link/Act
Col/Dup
Link/Act
Col/Dup
Link/Act
Port 3-bit serial stream
Port 3-bit serial stream
Port 3-bit serial stream
3-Bit Serial Stream Mode
2.56
2.56
2.56
2.56
2.56
2.56
2.56
LEDCLK LEDDTA
Link/Act
Link/Act
Link/Act
Port 2-bit serial stream
Port 2-bit serial stream
Port 2-bit serial stream
2-Bit Serial Stream Mode
74164 port port Link/Act port Col/Dup port port Link/Act port Col/Dup port port Link/Act
LEDDTA LEDCLK
74164
port Col/Dup port port Link/Act port Col/Dup port port Link/Act port Col/Dup port
74164
port Link/Act port Col/Dup port port Link/Act port Col/Dup port port Link/Act port Col/Dup
External circuit 3-bit serial mode
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74164 port Link/Act port port Link/Act port port Link/Act port port Link/Act port
LEDDTA LEDCLK
74164
port Link/Act port port Link/Act port port Link/Act port port Link/Act port
External circuit 2-bit serial mode
7.8.3 Bi-Color
3-bit Bi-color mode, Link/Act used Bi-color package, which single package with LEDs connected parallel with opposite polarities.
Yellow
Link/Act Indication Bi-Color state Link 100Mb/s Link Green 10Mb/s Link Yellow
Green
Link/Act
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2.5V Power Generation
RTL8208 uses transistor generate 2.5V from 3.3V power supply. This 2.5V provides digital core analog receive circuits. Once your system needs more than RTL8208 chip (greater than ports), transistor RTL8208 chips even rating enough. Instead, transistor each RTL8208. connect beads directly between collector transistor VDDAL. This will affect stability 2.5V power significantly bead exists.
3.3V
3.3V
RTL8208
VDDAH VDDAH: 3.3V VDDAL: 2.5V
2SB1197K Ic(max.)=800mA 2.5V 47uF
VCTRL VDDAL
0.1uF
Using Transistor Produce 2.5V power transistor 2SB1197K, follows following specifications. Absolute maximum ratings (Ta=25°C) Parameter Symbol Collector-base voltage VCBO Collector-emitter voltage VCEO Emitter-base voltage VEBO Collector current Collector power dissipation Junction temperature Storage temperature Tstg more information, refer http://www.rohm.com Limits -0.8 -55~+150 Unit A(DC)
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Design Layout Guide
order achieve maximum performance RTL8208, good design attention required throughout design layout process. following recommendations help implement high performance system.
General Guidelines
Create good power source, minimizing noise from switching power supply circuits. Verify quality components, such clock source transformer, meet application requirements. Keep power ground noise levels below 150mV. bulk capacitors (4.7uF-10uF) between power ground planes. 0.1uF decoupling capacitors reduce high-frequency noise power ground planes. Keep decoupling capacitors close possible RTL8208 power pins. Provide termination TXOP/N RXIP/N.
Differential Signal Layout Guidelines
Keep differential pairs close possible route both traces identically possible. Avoid vias layer changes possible. Keep different pairs away from each other.
Clock Circuit
clock should 25M/50MHz/125MHz 100ppm with jitter less than 0.5ns. 50MHz 125MHz clock source, make length clock path RTL8208 equal length possible. length difference should under inch. 50MHz, please damping resistor clock source side. possible, make clock trace smooth, strait, surrounded ground traces minimize high-frequency emissions.
2.5V power
connect bead directly between collector transistor VDDAL. This will affects stability 2.5V power significantly bead exists. bulk capacitor (4.7uF-10uF) between collector transistor ground plane. transistor more than RTL8208 chip, even rating enough. transistor each RTL8208.
Power Planes
layout board size small, better divide power plane into digital analog power planes. 0.1uF decoupling capacitors bulk capacitors between power plane ground plane.
Ground Planes
layout board size small, keep system ground region continuous, unbroken plane. Place moat (gap) between system ground chassis ground. better test performance, please iron case, screw connect frame ground iron case.
Transformer Options
magnetics support turn ratio both transmit receive paths valid RTL8208. There many vendors improving their magnetics design meet this requirement, several listed below. Vendor Pulse Magnetic Model H1164 ML164 Vendor BothHand Model 40ST1041AX FC-638L
center-tap primary side transformer should connected ground with capacitors, because RTL8208's special design. 2001/01/07 Rev.1.923
RTL8208
Application information
10Base-T/100Base-TX Application
RXIP
0.1uF
Pulse H1164
RJ45
RXIN
RTL8208
TXOP
0.1uF
TXON
IBREF
1.96,
0.1uF/3KV
Chasis
10Base-T/100Base-TX Diagram Central primary side H1164 must left floating, cannot bypassed capacitor.
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100Base-FX Application
(3.3V fiber transceiver)
VCC_RX (3.3V)
DELTA OPT-155A2H1
Duplex FDDI Fast Ethernet Optical Transceiver Module
RXIP RXIN
GND_RX
RTL8208
VCC_TX (3.3V) VCC_RX (3.3V) VCC_TX (3.3V)
VCC_RX VCC_TX
TXON TXOP
GND_TX
IBREF
1.96,
Chasis
100Base-FX Application (3.3V Fiber Transceiver)
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Electrical Characteristics
10.1 Absolute Maximum Ratings
WARNING: Absolute maximum ratings limits beyond which cause permanent damage device affect device reliability. voltages specified reference unless otherwise specified. Parameter Minimum Maximum Units Storage Temperature +150 Supply Referenced -0.5 +4.0 Digital Input Voltage -0.5 Output Voltage -0.5
10.2 Operating Range
Parameter Ambient Operating Temperature(Ta) 3.3V Supply Voltage Range(VDDAH) 2.5V Supply Voltage Range(VDDAL,VDD) Minimum 3.15 2.375 Maximum 3.45 2.625 Units
10.3 Characteristics
Parameter Power Supply Current 2.5V Symbol Conditions Base-T, idle Base-T, Peak continuous 100% utilization Base-TX, idle Base-TX, Peak continuous 100% utilization Power saving Power down Base-T, idle Base-T, Peak continuous 100% utilization Base-TX, idle Base-TX, Peak continuous 100% utilization Power saving Power down Base-T, idle Base-T, Peak continuous 100% utilization Base-TX, idle Base-TX, Peak continuous 100% utilization Power saving Power down
Typical
Power Supply Current 3.3V
Total Power Consumption ports
81.2 88.9 125.5 145.7 76.7 15.5 88.5 499.2 370.7 371.3 48.1 1870 1537 1590 2.25 2.75 0.25
Units
Input High Voltage Input Voltage Input Current Input Capacitance Output High Voltage Output voltage
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Rev.1.923
RTL8208
Parameter Output Tristate Leakage Current TX+/- Output Current High TX+/- Output Current TX+/- Output Current High TX+/- Output Current RX+/- Common-mode input voltage RX+/- Differential input resistance Receiver, 10BaseT Differential Input Resistance Input Squelch Threshold |IOZ| Conditions
Typical
Units
Transmitter, 100Base-TX (1:1 Transformer Ratio) Transmitter, 10Base-T(1:1 Transformer Ratio) Receiver, 100Base-TX
10.4 Characteristics
Parameter Differential Output Voltage, peak-to-peak Differential Output Voltage Symmetry Differential Output Overshoot Rise/Fall time Rise/Fall time imbalance Duty Cycle Distortion Timing jitter Differential Output Voltage, peak-to-peak TP_IDL Silence Duration Short Circuit Fault Tolerance Differential Output Impedance (return loss) Common-Mode Output Voltage Transmitter Output Jitter Differential Output Impedance (return loss) Harmonic Content Start-of-idle Pulse width Deviation from best-fit time-grid, 010101 Sequence Idle pattern Transmitter, 10Base-T from each output Vcc, pattern Period time from start TP_IDL link pulses period time between link pulses Peak output current short circuit seconds. Return loss from 5MHz 10MHz reference resistance Terminate each with resistive load. Return loss from 5MHz 10MHz reference resistance 100. below fundamental, cycles ones data TP_IDL width 10.5 Conditions Transmitter, 100Base-TX from each output Vcc, Best-fit over times from each output Vcc, |Vp+|/|Vp-| Percent Vp10-90% VpMin
Typical
Units
1.938 99.3 3.29 4.3/3.4 ±175 4.27 15.75
12.4
25.5
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RTL8208
10.5 Digital Timing Characteristics
Parameter Active TX_EN Sampled first output Inactive TX_EN Sampled first output Propagation Delay First input CRS_DV assert First input CRS_DV de-assert Propagation Delay Propagation Delay TX_EN output Conditions 100Base-TX Transmit System Timing
Typical
Units Bits Bits Bits Bits Bits Bits Bits Bits Bits Bits Bits
tTXpd From TXD[1:0] TXOP/N 100Base-TX Receive System Timing From RXIP/N CRS_DV From RXIP/N CRS_DV tRXpd tTXpd From RXIP/N RXD[1:0] 10Base-T Transmit System Timing From TXD[1:0] TXOP/N From TX_EN assert TXOP/N 10Base-T Receive System Timing Preamble RXIP/N CRS_DV asserted TP_IDL CRS_DV de-asserted
Carrier Sense Turn-on delay tCSON tCSOFF Carrier Sense Turn-off Delay tRXpd From RXIP/N RXD[1:0] Propagation Delay timing tLEDon While blinking Time tLEDoff While blinking Time Jabber timing (10Base-T only) Jabber Active From TX_EN=1 Jabber asserted Jabber de-assert From TX_EN=0 Jabber de-asserted RMII Timing TXD, TX_EN Setup time [1:0], TX_EN REFCLK rising edge setup time TXD, TX_EN Hold time [1:0], TX_EN REFCLK rising edge hold time RXD, CRSDV, RXER Output delay from REFCLK rising edge REFCLK delay [1:0], CRSDV, RXER SMII Timing TXD, SYNC Setup time TXD, SYNC REFCLK rising edge setup time TXD, SYNC Hold time SYNC REFCLK rising edge hold time RXD, REFCLK delay Output delay from REFCLK rising edge Timing clock rate MDIO Setup Time Write cycle MDIO Hold Time Write cycle MDIO output delay relative Read cycle rising edge
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RTL8208
10.6 Thermal Data
Parameter Thermal resistance: junction ambient, ft/s airflow Thermal resistance: junction case, ft/s airflow Conditions layers PCB, ambient temperature 25°C layers PCB, ambient temperature 25°C Typical 38.2 Units °C/W °C/W
2001/01/07
Rev.1.923
RTL8208
Mechanical Dimensions
Symbol
Dimension inch Typical 0.134 0.004 0.010 0.036 0.102 0.112 0.122 0.005 0.009 0.013 0.002 0.006 0.010 0.541 0.551 0.561 0.778 0.787 0.797 0.010 0.020 0.030 0.665 0.677 0.689 0.902 0.913 0.925 0.027 0.035 0.043 0.053 0.063 0.073 0.004
Dimension Typical 3.40 0.10 0.25 0.91 2.60 2.85 3.10 0.12 0.22 0.32 0.05 0.15 0.25 13.75 14.00 14.25 19.75 20.00 20.25 0.25 0.75 16.90 17.20 17.50 22.90 23.20 23.50 0.68 0.88 1.08 1.35 1.60 1.85 0.10
Dimension include interlead flash. Dimension does include dambar protrusion/intrusion. Controlling dimension Millimeter General appearance spec. should based final visual inspection spec.
TITLE (14x20 PACKAGE OUTLINE L/F, FOOTPRINT LEADFRAME MATERIAL APPROVE DOC. 530-ASS-P004 VERSION PAGE CHECK Q128 DATE Oct. 1998 REALTEK SEMI-CONDUCTOR CO.,
2001/01/07
Rev.1.923
RTL8208
Realtek Semiconductor Corp. Headquarters Industry East Road Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Tel: 886-3-5780211 Fax: 886-3-5776047 WWW: www.realtek.com.tw
2001/01/07
Rev.1.923

REALTEK SINGLE CHIP OCTAL 10/100 MBPS FAST ETHERNET TRANSCEIVER RTL820

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