MC3110 Single Chip Technical Specifications Brushed Servo Motion

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MC3110 Single Chip Technical Specifications Brushed Servo Motion

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PilotMotion Processor
MC3110 Single Chip Technical Specifications
Brushed Servo Motion Control
Performance Motion Devices, Inc. Bedford Road Lincoln, 01773
Revision 1.8, July 2003
NOTICE
This document contains proprietary confidential information Performance Motion Devices, Inc., protected federal copyright law. contents this document disclosed third parties, translated, copied, duplicated form, whole part, without express written permission PMD. information contained this document subject change without notice. part this document reproduced transmitted form, means, electronic mechanical, purpose, without express written permission PMD. Copyright 2000 Performance Motion Devices, Inc. Navigator, Pilot C-Motion trademarks Performance Motion Devices,
Warranty
warrants performance products specifications applicable time sale accordance with PMD's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Performance Motion Devices, Inc. (PMD) reserves right make changes products discontinue product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability.
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Disclaimer
assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such products services might used. PMD's publication information regarding third party's products services does constitute PMD's approval, warranty endorsement thereof.
MC3110 Technical Specifications
MC3110 Technical Specifications
Related Documents
Pilot Motion Processor User's Guide (MC3000UG) members Pilot Motion Processor family. Pilot Motion Processor Programmer's Reference (MC3000PR) Descriptions Pilot Motion Processor commands, with coding syntax examples, listed alphabetically quick reference. Pilot Motion Processor Technical Specifications These booklets contain physical electrical characteristics, timing diagrams, pinouts descriptions each: MC3110, brushed servo motion control (MC3110TS) MC3310, brushless servo motion control (MC3310TS) MC3410, microstepping motion control (MC3410TS) MC3510, stepper motion control (MC3510TS) Pilot Motion Processor Developer's Manual (DK3000M) install configure DK3110 developer's board.
MC3110 Technical Specifications
MC3110 Technical Specifications
Table Contents
Warranty. Safety Notice Disclaimer. Related Documents. Table Contents. Pilot Family Functional Characteristics. Configurations, parameters, performance Physical characteristics mounting dimensions. Environmental electrical ratings System configuration. Peripheral device address mapping. Electrical Characteristics. characteristics. characteristics. Timing Diagrams Clock Quadrature encoder input Reset Host interface, 8/16 mode (requires external logic device) 4.4.1 Instruction write, 8/16 mode. 4.4.2 Data write, 8/16 mode. 4.4.3 Data read, 8/16 mode. 4.4.4 Status read, 8/16 mode. Host interface, 16/16 mode (requires external logic device) 4.5.1 Instruction write, 16/16 mode. 4.5.2 Data write, 16/16 mode. 4.5.3 Data read, 16/16 mode. 4.5.4 Status read, 16/16 mode. External memory timing. 4.6.1 External memory read. 4.6.2 External memory write Peripheral device timing 4.7.1 Peripheral device read. 4.7.2 Peripheral device write Pinouts Descriptions. Pinouts MC3110 chip description table.
MC3110 Technical Specifications
Parallel Communication Host interface description table 16-bit Host Interface (IOPIL16) 8-bit Host Interface (IOPIL8) Application Notes. Design Tips. RS-232 Serial Interface 422/485 Serial Interface. Motor Interface 12-bit Parallel Interface. 16-bit Serial Interface. Interface. User-defined 12-bit Interface. 7.10 16-bit Input 7.11 External Gating Logic Index
MC3110 Technical Specifications viii
Pilot Family
MC3110
Number axes Motor type supported Output format Incremental encoder input Parallel word device input Parallel communication Serial communication S-curve profiling On-the-fly changes Directional limit switches Programmable output Software-invertable signals servo control Feedforward (accel vel) Derivative sampling time Data trace/diagnostics output Pulse direction output Index Home signals Motion error detection Axis settled indicator DAC-compatible output Position capture Analog input User-defined External support Multi-chip synchronization Chip part numbers Developer's p/n's:
MC3310
Brushless servo Commutated (6step sinusoidal)
MC3410
Stepping Microstepping
MC3510
Stepping Pulse Direction
Brushed servo Brushed servo (single phase)
(MC3113)
MC3110 DK3110
(MC3313)
MC3310 DK3310
(with encoder) (with encoder) (MC3413)
MC3410 DK3410
(with encoder) (with encoder) MC3510 DK3510
Parallel communication available additional logic device
Introduction
This manual describes operational characteristics MC3110 Motion Processor from PMD. This device member MC3000 family single-chip, single-axis motion processors.
MC3110 Technical Specifications
Each device MC3000 family complete chip-based motion processor providing trajectory generation related motion control functions axis including servo loop closure onboard commutation where appropriate. This family products provides software-compatible selection dedicated motion processors that handle large variety system configurations. chip architecture only makes ideal task motion control, allows similarities software commands, software written motor type re-used motor type changed.
Pilot Family Summary
MC3110 This single-chip, single-axis motion processor outputs motor commands either Sign/Magnitude DAC-compatible format with brushed servo motors, with brushless servo motors having external commutation. MC3310 This single-chip, single-axis motion processor outputs sinusoidally commutated motor signals appropriate driving brushless motors. Depending motor type, output twophase three-phase signal either DAC-compatible format. MC3410 This single-chip, single-axis motion processor outputs microstepping signals stepping motors. phased signals axis generated either DAC-compatible format. MC3510 This single-chip, single-axis motion processor outputs pulse direction signals stepping motor systems.
MC3110 Technical Specifications
Functional Characteristics
Configurations, parameters, performance
Configuration Operating modes Communication modes Single axis, single chip. Closed loop (motor command driven from output servo filter) Open loop (motor command driven from user-programmed register) 8/16 parallel external parallel with internal command word size) 16/16 parallel external parallel with internal command word size) Point point asynchronous serial Multi-drop asynchronous serial 1,200 baud 416,667 baud -2,147,483,648 +2,147,483,647 counts -32,768 +32,767 counts/sample with resolution 1/65,536 counts/sample -32,768 +32,767 counts/sample2 with resolution 1/65,536 counts/sample2 counts/sample3, with resolution 1/4,294,967,296 counts/sample3 S-curve point-to-point (Velocity, acceleration, jerk, position parameters) Trapezoidal point-to-point (Velocity, acceleration, deceleration, position parameters) Velocity-contouring (Velocity, acceleration, deceleration parameters) Scalable Velocity feedforward Acceleration feedforward Bias. Also includes integration limit, settable derivative sampling time, output motor command limiting bits Motion error window (allows axis stopped upon exceeding programmable window) Tracking window (allows flag axis exceeds programmable position window) Axis settled (allows flag axis exceeds programmable position window programmable amount time after trajectory motion compete) (10-bit resolution kHz) bits) Incremental million counts/sec) Parallel-word million counts/sec) bits (reads axes every µsec) 102.4 µsec 32.767 milliseconds 102.4 µsec <10µsec difference between master slave servo cycle MC3113 chipset only axis: each direction travel axis: index home signals AxisIn signal axis, AxisOut signal axis MC3110 Technical Specifications
Serial port baud rate range Position range Velocity range Acceleration/deceleration ranges Jerk range Profile modes
Filter modes
Filter parameter resolution Position error tracking
Motor output modes Maximum encoder rate Parallel encoder word size Parallel encoder read rate Servo loop timing range Minimum servo loop time Multi-chip synchronization Limit switches Position-capture triggers Other digital signals (per axis)
Software-invertable signals Analog input User defined discrete RAM/external memory support Trace modes Max. number trace variables Number traceable variables Number host instructions
Index, Home, AxisIn, AxisOut, PositiveLimit, NegativeLimit (all individually programmable) 10-bit analog inputs 16-bit wide user defined 65,536 blocks 32,768 16-bit words block. Total accessible memory 2,147,483,648 words one-time continuous
MC3110 Technical Specifications
Physical characteristics mounting dimensions
dimensions inches (with millimeters brackets).
Dimension
Minimum (inches)
1.070 0.934 1.088
Maximum (inches)
1.090 0.966 1.112 0.800 nominal
MC3110 Technical Specifications
Environmental electrical ratings
Storage Temperature (Ts) Operating Temperature (Ta) Power Dissipation (Pd) Nominal Clock Frequency (Fclk) Supply Voltage limits (Vcc) Supply Voltage operating range (Vcc) 20.0 -0.3V +7.0V 4.75V 5.25V
industrial version with operating range -40°C 85°C also available. Please contact more information.
System configuration
following figure shows principal control data paths MC3110 system.
Host
HostIntrpt
HostData0-15
~HostWrite
~HostRead
~HostSlct
Serial Port
HostCmd
Parallel port
HostRdy
Pilot Motion Processor
System clock MHz)
Home
Index
Encoder
Parallel Communication PLD/FPGA
20MHz clock
(MC3310 only)
Hall sensors
Negative
AxisOut
Positive
AxisIn
data/address
External memory
Limit switches
User
output
converter
Motor Amplifier
Parallel-word input
Serial port configuration
shaded area shows CPLD/FPGA that must provided designer parallel communication required. description necessary logic form schematics) this device detailed section this manual. chip contains profile generator, which calculates velocity, acceleration, position values trajectory; digital servo filter, which stabilizes motor output signal.
MC3110 Technical Specifications
output
filter produces types output: Pulse-Width Modulated (PWM) signal output; DAC-compatible value routed data appropriate converter. Axis position information returns motion processor form encoder feedback using either incremental encoder input signals, parallel word input.
Peripheral device address mapping
Device addresses chip's data memory-mapped following locations: Address 0200h 0800h 1000h 2000h 4000h 8000h Device Serial port data Parallel-word encoder User-defined page pointer Motor-output DACs Parallel interface Description Contains configuration data (transmission rate, parity, stop bits, etc) asynchronous serial port Base address parallel-word feedback devices Base address user-defined devices Page pointer external memory Base address motor-output converters Base address parallel interface communication
MC3110 Technical Specifications
Electrical Characteristics
characteristics
(Vcc operating ratings, Fclk 20.0 MHz)
Symbol Vihclk Voclk Vihreset Iout Ednl Einl Parameter Supply Voltage Supply Current Minimum 4.75 Maximum 5.25 Vout typical Conditions open outputs
Input Voltages Logic input voltage Logic input voltage -0.3 Logic voltage clock (ClockIn) Logic voltage clock -0.3 (ClockIn) Logic voltage reset (reset) Logic Output Voltage Logic Output Voltage Output Voltages
0.33 Other +/-1.5
Tri-State output leakage current Input current Input/Output capacitance
Analog Input Analog input source impedance Differential nonlinearity error. Difference between step width ideal value. Integral nonlinearity error. Maximum deviation from best straight line through transfer characteristics, excluding quantization error.
characteristics
timing diagrams, Section numbers. symbol indicates active signal.
Timing Interval Clock Frequency (Fclk) Clock Pulse Width Clock Period (note Encoder Pulse Width Dwell Time State ~HostSlct Hold Time Minimum nsec nsec nsec nsec nsec Maximum (note
MC3110 Technical Specifications
Timing Interval ~HostSlct Setup Time HostCmd Setup Time HostCmd Hold Time Read Data Access Time Read Data Hold Time ~HostRead High HI-Z Time HostRdy Delay Time ~HostWrite Pulse Width Write Data Delay Time Write Data Hold Time Read Recovery Time (note Write Recovery Time (note Read Pulse Width Address Setup Delay Time Data Access Time Address Setup Delay Time Address Setup WriteEnable High RAMSlct WriteEnable High Address Hold Time WriteEnable Pulse Width Data Setup Time Data Setup before Write High Time Address Setup Delay Time Data Access Time Data Hold Time Address Setup Delay Time Address Setup WriteEnable High PeriphSlct WriteEnable High Address Hold Time WriteEnable Pulse Width Data Setup Time Data Setup before Write High Time Read Write Delay Time Reset Pulse Width RAMSlct Strobe Strobe High RAMSlct High WriteEnable Strobe Strobe High WriteEnable High PeriphSlct Strobe Strobe High PeriphSlct High
Minimum nsec nsec nsec
Maximum
nsec nsec nsec nsec nsec nsec
nsec nsec nsec nsec nsec
nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec µsec nsec nsec nsec nsec nsec nsec
Note Performance figures timing information valid Fclk 20.0 only. timing information performance parameters Fclk 20.0 MHz, refer section 7.1. Note clock low/high split allowable range 45-55%.
MC3110 Technical Specifications
Timing Diagrams
values please refer table Section 3.2. host interface timing shown diagrams only valid when external logic device used provide parallel communication interface. Refer section more information.
Clock
ClockIn
Quadrature encoder input
Quad
Quad
~Index
Reset
ClockIn
~RESET
MC3110 Technical Specifications
4.4.1
Host interface, 8/16 mode (requires external logic device)
Instruction write, 8/16 mode
note
~HostSlct
HostCmd
note
~HostWrite
byte
HostData0-7
High byte
HostRdy
Note: setup hold times met, ~HostSlct HostCmd de-asserted this point.
4.4.2
Data write, 8/16 mode
~HostSlct
note
HostCmd
note
~HostWrite
byte
HostData0-7
High byte
HostRdy
Note: setup hold times met, ~HostSlct HostCmd de-asserted this point.
MC3110 Technical Specifications
4.4.3
Data read, 8/16 mode
note
~HostSlct
HostCmd
note
~HostRead
High-Z High byte High-Z High-Z
HostData0-7
byte
HostRdy
Note: setup hold times met, ~HostSlct HostCmd de-asserted this point.
4.4.4
Status read, 8/16 mode
~HostSlct
HostCmd ~HostRead
HostData0-7
High-Z
High byte
High-Z
byte
High-Z
MC3110 Technical Specifications
4.5.1
Host interface, 16/16 mode (requires external logic device)
Instruction write, 16/16 mode
~HostSlct
HostCmd
~HostWrite
HostData0-15
HostRdy
4.5.2
Data write, 16/16 mode
~HostSlct
HostCmd
~HostWrite
HostData0-15
HostRdy
MC3110 Technical Specifications
4.5.3
Data read, 16/16 mode
~HostSlct
HostCmd
~HostRead
HostData0-15
High-Z
High-Z
HostRdy
4.5.4
Status read, 16/16 mode
~HostSlct
HostCmd
~HostRead
HostData0-15
High-Z
High-Z
MC3110 Technical Specifications
4.6.1
External memory timing
External memory read
Note: recommends using memory with access time greater than nsec.
~RAMSlct
Addr0-Addr15
W/~R
~WriteEnbl Data0-Data15
~Strobe
4.6.2
External memory write
~RAMSlct
Addr0-Addr15
R/~W
W/~R
~WriteEnbl
Data0-Data15
~Strobe
MC3110 Technical Specifications
4.7.1
Peripheral device timing
Peripheral device read
~PeriphSlct
Addr0-Addr15
W/~R
~WriteEnbl Data0-Data15
~Strobe
4.7.2
Peripheral device write
~PeriphSlct
Addr0-Addr15
R/~W
W/~R
~WriteEnbl
Data0-Data15
~Strobe
MC3110 Technical Specifications
Pinouts Descriptions
Pinouts MC3110
103,
~WriteEnbl R/~W ~Strobe ~PeriphSlct ~RAMSlct ~Reset W/~R SrlRcv SrlXmt SrlEnable ~HostIntrpt ClockIn Addr0 Addr1 Addr2 Addr3 Addr4 Addr5 Addr6 Addr7 Addr8 Addr9 Addr10 Addr11 Addr12 Addr13 Addr14 Addr15 Data0 Data1 Data2 Data3 Data4 Data5 Data6 Data7 Data8 Data9 Data10 Data11 Data12 Data13 Data14 Data15
AnalogVcc AnalogRefHigh AnalogRefLow AnalogGnd Analog1 Analog2 Analog3 Analog4 Analog5 Analog6 Analog7 Analog8 PosLim1 NegLim1 AxisOut1 AxisIn1 PWMMag1 PWMSign1 QuadA1 QuadB1 ~Index1 ~Home1 NC/Synch
I/OIntrpt PrlEnable
104, 113,
Unassigned 30-34, 101, 102, 105, 106, 107-109,
AGND 78-81
MC3110 Technical Specifications
chip description table
Name number Direction
~WriteEnbl R/~W ~Strobe ~PeriphSlct ~RAMSlct ~Reset W/~R SrlRcv SrlXmt SrlEnable ~HostIntrpt I/OIntrpt
Description
When low, this signal enables data written bus. This signal high when chip performing read, when performing write. This signal when data address valid during communications. This signal when peripheral devices data being addressed. This signal when external memory being accessed. This master reset signal. When brought low, this resets processor initial conditions. This signal inverse R/~W; high when R/~W low, vice versa. some decode circuits, this more convenient than R/~W. This receives serial data from asynchronous serial port. serial communication used, this should tied Vcc. This transmits serial data asynchronous serial port. This sets serial port enable line. SrlEnable always high point-topoint protocol high during transmission multi-drop protocol. When low, this signal causes interrupt sent host processor. This signal interrupts chip when host transfer complete. should connected CPIntrpt parallel interface chip. parallel interface disabled (see below) this signal left unconnected tied Vcc. This signal enables/disables parallel communication with host. this signal tied high, parallel interface enabled. this signal tied parallel interface disabled. section this manual more information parallel communication.
output output output output output input output input output output output input
PrlEnable
input
WARNING! This signal should only tied high external logic device that implements parallel communication logic included design. This signal output during device reset such connection must series resistor.
Data0 Data1 Data2 Data3 Data4 Data5 Data6 Data7 Data8 Data9 Data10 Data11 Data12 Data13 Data14 Data15
bi-directional
Multi-purpose data lines. These pins comprise chip's external data bus, used communications with peripheral devices such external memory DACs. They also used parallel-word input user-defined operations.
MC3110 Technical Specifications
Name number Direction
Addr0 Addr1 Addr2 Addr3 Addr4 Addr5 Addr6 Addr7 Addr8 Addr9 Addr10 Addr11 Addr12 Addr13 Addr14 Addr15 ClockIn AnalogVcc
Description
Multi-purpose Address lines. These pins comprise chip's external address bus, used select devices communication over data bus. They used output, parallel word input, user-defined operations. Pilot Motion Processor User's Guide complete memory map.
output
input input
AnalogRefHigh
input
AnalogRefLow
input
AnalogGND
Analog1 Analog2 Analog3 Analog4 Analog5 Analog6 Analog7 Analog8 PWMMag1
input
This clock signal motion processor. driven nominal MHz. chip analog power supply voltage. This must connected analog input supply voltage, which must range 4.5-5.5 analog input circuitry used, this must connected Vcc. chip analog high voltage reference input. allowed range AnalogRefLow AnalogVcc. analog input circuitry used, this must connected Vcc. chip analog voltage reference input. allowed range AnalogGND AnalogRefHigh. analog input circuitry used, this must connected GND. chip analog input ground. This must connected analog input power supply return. analog input circuitry used, this must connected GND. These signals provide general-purpose analog voltage levels, which sampled internal converter. resolution bits. allowed range AnalogRefLow AnalogRefHigh. unused pins should tied AnalogGND. analog input circuitry used, these pins should tied GND.
output
PWMSign1 QuadA1 QuadB1
output input
This provides Pulse Width Modulated signal motor. This magnitude signal. resolution bits frequency 20.0 KHz. This provides sign (direction) signal motor amplifier. This signal high when output positive, when negative. These pins provide quadrature signals incremental encoder. When axis moving positive (forward) direction, signal leads signal 90°. theoretical maximum encoder pulse rate MHz. Actual maximum rate will vary, depending signal noise. NOTE: Many encoders require pull-up resistor each signal establish proper high signal. Check your encoder's electrical specification.
MC3110 Technical Specifications
Name number Direction
~Index1
Description
This provides Index signal incremental encoder. valid index pulse recognized processor when this signal transitions from high low.
input
There internal gating index signal with encoder inputs. This must performed externally desired. Refer section 7.11 example schematic.
~Home1
input
This provides Home signal, general-purpose inputs positioncapture mechanism. valid Home signal recognized processor when ~Home goes low.
WARNING! this used, signal should tied high.
PosLim1
input
This signal provides input from positive-side (forward) travel limit switch. power-up Reset this signal defaults active interpretation, interpretation explicitly using SetSignalSense instruction.
WARNING! this used, signal should tied high.
NegLim1
input
This signal provides input from negative-side (reverse) travel limit switch. power-up Reset this signal defaults active interpretation, interpretation explicitly using SetSignalSense instruction.
WARNING! this used, signal should tied high. This signal output during device reset such connection must series resistor.
AxisOut1 AxisIn1
NC/Synch
This programmed track state Status registers. this used left unconnected. input This general-purpose programmable input. used breakpoint input, stop motion axis, cause Update occur. this used left unconnected. input/output MC3110 this used. MC3113, this synchronization signal. disabled mode, configured input used. master mode, outputs synchronization pulse that used slave nodes other devices synchronize with internal chip cycle master node. slave mode, configured input pulse synchronizes internal chip cycle. digital supply voltage. these pins must connected supply voltage. must range 4.75 5.25 103,
output
WARNING! must tied HIGH with pull-up resistor. nominal value Ohms suggested.
AGND unassigned
unassigned
ground. these pins must connected power supply return. 104, 113, 78-81 These signals must tied AnalogGND. analog input circuitry used, these pins must tied GND. These signals connected better noise immunity reduced 105, 106, 107, power consumption they left unconnected (floating). 108, 30-34, These signals must left unconnected (floating). 101, 102,
MC3110 Technical Specifications
Parallel Communication
With addition external logic device, Pilot motion processor communicate with host processor using parallel data stream. This offers higher communication rate than serial interface used configurations where serial connection available convenient. This section details required logic that must implemented external device well necessary connections chip. reference design files parallel interface chip, Actel/ViewLogic format, available from PMD. There versions design, interfacing with host processors that have 8-bit data host processors that have 16-bit data bus. designs called IOPIL8 IOPIL16 respectively. interface chip essentially identical both. function chip provide shared-memory style interface between host chip, comprised four 16-bit wide locations. These used transferring commands data between host Pilot motion processor. chip accesses command/data registers using 16-bit external data while host accesses registers parallel interface with chip select, read, write command/data signals. necessary, host side interface modified designer match specific requirements host processor.
Host interface description table
Name
HostCmd
Direction
input output
Description
This signal asserted high write host instruction motion processor, read status HostRdy HostIntrpt signals. asserted read write data word. This signal used synchronize communication between motion processor host. HostRdy will (indicating host port busy) read write operation according interface mode use, follows: Interface Mode HostRdy goes 8/16 after second byte instruction word after second byte each data word transferred 16/16 after 16-bit instruction word after each 16-bit data word serial HostRdy will high, indicating that host port ready transmit, when last transmission been processed. host port communications must made with HostRdy high (ready). typical busy-to-ready cycle 12.5 microseconds, substantially longer, microseconds. When ~HostRead low, data word read from motion processor. When ~HostWrite low, data word written motion processor. When ~HostSlct low, host port selected reading writing operations. chip chip interrupt. This signal sends interrupt chip whenever host-chipset transmission occurs. should connected chip I/OIntrpt. This signal high when chip reading data from chip, when writing data. should connected chip R/W. This signal goes when data address become valid during Motion processor communication with peripheral devices data bus, such external memory DAC. should connected chip Strobe. MC3110 Technical Specifications
HostRdy
~HostRead ~HostWrite ~HostSlct CPIntrpt
input input input output input input
CPR/~W CPStrobe
Name
CPPeriphSlct CPAddr0 CPAddr1 CPAddr15 MasterClkIn CPClk
Direction
input input input output bi-directional, tri-state
Description
This signal goes when peripheral device data being addressed. should connected chip 130, PeriphSlct. These signals high when chip communicating with chip distinguished from other device data bus). They should connected chip pins (Addr0), (Addr1), (Addr15). This master clock signal motion processor. driven nominal This signal provides clock pulse chip. frequency half that MasterClkIn (pin 89), nominal. connected directly chip I/Oclk signal (pin 58). These signals transmit data between host Motion processor through parallel port. Transmission mediated control signals ~HostSlct, ~HostWrite, ~HostRead HostCmd. 16-bit mode, bits used (HostData0-15). 8-bit mode, only loworder bits data used (HostData0-7).
HostData0 HostData1 HostData2 HostData3 HostData4 HostData5 HostData6 HostData7 HostData8 HostData9 HostData10 HostData11 HostData12 HostData13 HostData14 HostData15 CPData0 CPData1 CPData2 CPData3 CPData4 CPData5 CPData6 CPData7 CPData8 CPData9 CPData10 CPData11 CPData12 CPData13 CPData14 CPData15
bi-directional
These signals transmit data between chip pins Data0-15 chip, motion processor data bus.
MC3110 Technical Specifications
16-bit Host Interface (IOPIL16)
This design implements parallel interface with host processor utilizing 16-bit data bus. understanding underlying operation design only necessary designer intends make modifications. most cases this design implemented without changes. following notes should read while referencing schematics. IOPIL16 level schematic. timing host chip communication found section timing chip communication found section 4.7. description below identifies elements each schematic starting with host side signals. paragraph title identifies schematic(s) being described text. IOPIL16 host interface shown sheet IOPIL16 incoming data HD[15:0] latched transparent latches when ~HG1 ~HG2 high. This would result write from host latched data HI[15:8] HI[7:0] schematic IOPIL16 IOPIL16 Data from interface host, HO[15:8] HO[7:0] enabled onto host bus, HD[15:0], HOES2 HOES1 respectively. output latches, which present data during host read, always transparent because GOUT connected VDD. latched option Actel part used could omitted host interface different CPLD FPGA does have this feature. IOPIL16 control host interface starts IOPIL16 HOES1 HOES2 ~HSEL ~HRD enable read data onto host bus, previously described. HRDY handshaking signal host allow asynchronous communication between host host must wait until HRDY true before attempting communicate with This signal copied host status register. host status register read time determine state HRDY, HRDY output used interrupt host. ~HSEL, ~HRD, ~HWR, buffered inputs host control signals. HOST INTERFACE/IOPIL16 Data from host HI[15:8] HI[7:0] written into REG1 REG2 schematic HOST INTERFACE ~EN1 ~EN2. These registers have multiplexed input with both host data data being written these registers. This convenient diagnostic purposes very efficient Actel A42MX FPGA's, which multiplexer based configuration logic device used demands separate registers could used host data. schematic this register shown DFME8. Only commands checksums written registers REG1 REG2 while data written read from data registers, DATREG shown IOPIL16 These data registers buffer data sent from reducing number interrupts must handle. output from REG1 REG2, CIQ[15:8] CIQ[7:0] IOPIL16 where they multiplexed with other data registers. multiplexed result, IQ[15:8] IQ[7:0], multiplexed with HST[15:8] HST[7:0] output host status registers REG3 REG4. previously mentioned, HRDY becomes HST15 read host. rest status register written provide information host. acts address bit, usually address bus. When host writing, indicates data high indicates command. When host reading, indicates data high indicates status. Read status only transaction
MC3110 Technical Specifications
allowed while HRDY low. During host write gate (G1:HOST INTERFACE) flops latch incoming data interface latches driving ~HG1, ~HG2 from start write transaction until first negative clock transition after first positive transition following start write cycle. This tail-biting circuit removes requirement hold time data bus. HICTLA Most control logic host interface shown schematic HICTLA. sequencer generates HCYC clock interval after interface been accessed host finished transaction. nature transaction, rd/wr, command/data, read status preserved three flops F13, host write write, DSIW, enable REG1 REG2 HOST INTERFACE schematic discussed previously. host data write generates ~ENHD1 ~ENHD2 data registers DATREG schematic. logic bottom page generates interrupt, HRDY HCMDFL. HCMDFL used status indicate command. DSIW, writing REG1 REG2 HOST INTERFACE schematic clears interrupt reasserts HRDY. HRDY de-asserted during host transactions except read status, stays de-asserted until completed DSIW cycle that clears interrupt reasserts HRDY. mentioned previously data transfers from host data registers interrupt knows number data transfers that must take place after decoding command. places this number, 0-3, least significant bits host status register, HST[1:0]. These become DPNT[1:0] this page schematic enable interrupt read write. always leaves theses unless setting multiple word data transfer. INTEN true LRDST, latched read status, false, HCYC will generate interrupt This will also hold HRDY false until after writes interface register, DSIW, thereby generating ~CLRFLGS. IOPIL16 interface shown sheet IOPIL16 incoming data DSD[15:0] latched transparent latches when ~DG1 ~DG2 high. This occurs completion write from chip. latched data DSI[15:8] DSI[7:0] schematic IOPIL16 IOPIL16 DSI[7:0] also goes IOPIL16 Data from interface DO[15:8] DO[7:0] enabled onto bus, DSD[15:0], DOE2 DOE1 respectively. output latches, which present data during read, always transparent because GOUT connected VDD. latched Actel part contains both input output latches. output latches could omitted interface different CPLD FPGA does have this feature. incoming address bits CPA0 CPA1 also latched using ~DG3. 20CK signal clock This clock derived from clock input. IOPIL16 control starts IOPIL16 control generated from ~CPSTRB, ~CPIS, CPSEL R/W. ~DG1, ~DG2, ~DG3 latch incoming data DOE1 DOE2 outenable data from this chip tail-bite write avoid having specify hold times data. Flop divides 40MHz clock down MHz. clock could used this interface
MC3110 Technical Specifications
DSPWA write control contained schematic DSPWA. interface uses page addressing save pins. make page register. addition there address bits, LA1. write address selects page register with DSI[2:0] going page register selecting page successive transfers. read from address reads status register pages. Pages only ones implemented this device. latches level. write decoding generates DSIW which enables writes DFME8 registers reg1 reg2 shown HOST INTERFACE schematic. DSIW also clears interrupt restores HRDY. DSWST writes host status register also shown HOST INTERFACE schematic. DSWDREG implements writing data registers shown IOPIL16 DATREG. Finally logic bottom page generates CPCYC, 1-clock interval after cycle over that implements actual writes registers. data latches post cycle transfers keeps much logic synchronous possible given asynchronous devices, without requiring clocking several times speed. DSPRA read control contained schematic DSPRA. selects status latched address IQ[15:0] address only significant status bits bits (indicating interrupting host), bits (both indicating host interface) (set during host command transfer during data transfer). HOST INTERFACE Both host special mode transfer data avoid unnecessary interrupts. This special mode under control transparent host. When receives command from host initializes transfer setting number transfers expected (0,1,2 LSB's host status register, REG3 REG4 HOST INTERFACE. This write (DSWST) also loads these bits into down counter DCNT2 IOPIL16 Note that low, which indicates host command, asynchronously clears this register enabling interrupts schematic HICTLA. DPNT[1:0] high, indicating host data transfer, SINT goes high indicating host cycle counter decremented. MXAD2 selects address from latched address bits page register contains counter contents DPNT[1:0] not. This allows have direct access registers using addresses 1,2,and page host other hand only read write data register, counter will auto decrement from down allowing host access registers DATREG where REG1=R1 REG2=R3 REG3=R5 writes enabled decoders DECE2X4, while reads selected muxes, MUX1 MUX2 controlled muxes MDS1 MDS0. output data IQ[15:0] goes HOST INTERFACE schematic below IOPIL16 DSPRA below IOPIL16 write data HI[15:8], HI[7:0] from host DSI[15:8] DSI[7:0] from
MC3110 Technical Specifications
HINTF HSTSEL
INBUF
IN17
HSEL
HSEL
HOST INTERFACE (HINTRFA) HO[7:0] HO[7:0] HO[15:8] HO[15:8]
HSTRD
INBUF
IN18
HSTWR
INBUF
IN19
HI[7:0] HI[15:8] HI[15:8] HI[7:0]
HADR0
INBUF
IN20
DSI[15:8] DSI[15:8] DSI[7:0] DSI[7:0] DPNT[1:0] HST[1:0] DSWST DSIW DSWST SINT DSIW CIQ[15:8] CIQ[7:0]
CIQ[7:0] CIQ[15:8]
SINT
IQ[7:0] IQ[7:0] HST14 IQ[15:8] IQ[15:8] HCMDFL DSPINTR HST15 ENHD1 ENHD2 HSEL
ST15 DSPINTR
OUTBUF
ENHD1 ENHD2
HRDY
AND2B
HOES1
HSEL
AND2B
HOES2
OUTBUF
DSPINTR
OUT5
DSPINT
IOPIL16
2002
DRAWN
PNT0 PNT1
CSEL0 CSEL1 DSPRA
DSWDREG DSI[7:0] DSI[7:0] DSWST DSIW
DSWDREG ST15 DSIW DSWST IQ[15:0] IQ[15:0] ST15
IN27
INBUF
IN28
CPSEL
CPR-W
INBUF
DO[15:0] IN26 CPSEL CPSTRB CPSTRB CPIS DSPWA CLKINT CPCYC CPCYC DSPRA DO[15:0]
STRB
INBUF
IN30
INBUF
CKBUF 20CK
CPIS
CPSTRB CPIS CPSEL
NAND3B
CSACC
AND4B
DOE1 CLKIN
INBUF
40CK
DF1A
20CK
AND4B
DOE2
NAND3B
NAND3B
CSACC
CSACC
NAND4B
IOPIL16
2002
DRAWN
HIGH SLEW
HIGH SLEW
HIGH SLEW
HIGH SLEW
HO12
HD12
GOUT
GOUT
GOUT
GOUT
HI12
BBDLHS
BBDLHS
BBDLHS
BBDLHS
HIGH SLEW
HIGH SLEW
HIGH SLEW
HIGH SLEW
HO13
HD13
GOUT
GOUT
GOUT
GOUT
HI13
BBDLHS
BBDLHS
BBDLHS
BBDLHS
HIGH SLEW
HIGH SLEW
HIGH SLEW
HIGH SLEW
HO10
HD10
HO14
HD14
GOUT
GOUT
GOUT
HI10
GOUT
HI14
BBDLHS
BBDLHS
BBDLHS
BBDLHS
HIGH SLEW
HIGH SLEW
HIGH SLEW
HIGH SLEW
HO11
HO15 HD11
HD15
GOUT
GOUT
GOUT
GOUT
HI11
HI15
BBDLHS
BBDLHS
BBDLHS
BBDLHS
HI[7:0]
HI[15:0]
HO[7:0]
HO[15:8]
HOES1 HOES2
IOPIL16
2002
DRAWN
DOE1
HIGH SLEW
DOE1
HIGH SLEW
DOE2
HIGH SLEW
DOE2
HIGH SLEW
DSD0
DSD4
DSD8
DO12
DSD12
GOUT
DSI0
GOUT
DSI4
GOUT
DSI8
GOUT
DSI12
BBDLHS
BBDLHS
BBDLHS
BBDLHS
DOE1
DOE1
DOE2
HIGH SLEW
DOE2
HIGH SLEW
HIGH SLEW
HIGH SLEW
DSD1
DSD5
DSD9
DO13
DSD13
GOUT
DSI1
GOUT
DSI5
GOUT
DSI9
GOUT
DSI13
BBDLHS
BBDLHS
BBDLHS
BBDLHS
DOE1
HIGH SLEW
DOE1
DOE2
HIGH SLEW
DOE2
HIGH SLEW
HIGH SLEW
DSD2
DSD6
DO10
DSD10
DO14
DSD14
GOUT
DSI2
GOUT
DSI6
GOUT
DSI10
GOUT
DSI14
BBDLHS
BBDLHS
BBDLHS
BBDLHS
DOE1
HIGH SLEW
DOE2
DOE2
HIGH SLEW
DOE1
HIGH SLEW
DSD3
HIGH SLEW
DSD7 DO11
DO15 DSD11
DSD15
GOUT
GOUT
DSI3
DSI7
GOUT
GOUT
DSI11
DSI15
BBDLHS
BBDLHS
BBDLHS
BBDLHS
DSI[7:0]
DSI[15:8]
DO[15:8] DO[7:0] DOE2 DOE1
HIGH SLEW HIGH SLEW
DOE2
CPA0
CPA1
GOUT
GOUT
OUTBUF
BBDLHS
BBDLHS
20CK
CLKOUT
IOPIL16
2002
DRAWN
ENHD1 DSWDREG
OR2A
END1
DREG ENHD2 DOE1 CIQ[7:0] CIQ[7:0] CIQ[15:8] CIQ[15:8] HI[7:0] HI[7:0] HI[15:8] HIH[15:8] IQ[7:0] DSI[7:0] DSI[7:0] IQ[15:8] DSI[15:8] DSI[15:8] RA[1:0] LA[1:0] LA[1:0] END1 END2 END1 END2 DATREG RA[1:0] IQ[15:8] DPNT1 DPNT0 IQ[7:0] SINT DOE1
OR2A
END2
AND3
NAND2B
DPINC
DCNT2
DSWST DPINC DSI[1:0]
SLOAD ENABLE ACLR CLOCK Q[1:0] DATA[1:0]
DPNT[1:0]
MXAD2
DATA0_[1:0] RESULT[1:0] DATA1_[1:0]
RA[1:0]
LA[1:0]
SEL0
IOPIL16
2002
DRAWN
REG1
HST[1:0] IQ[7:0] REG3 HI[7:0] A[7:0] Q[7:0] DSI[7:0] B[7:0] DSI[7:2]
DATA[5:0] CLOCK Q[5:0]
MUX1
MUX2X8
DFME8
REG6
CIQ[7:0] DSWST
ENABLE
HST[7:0]
DATA0_[7:0] RESULT[7:0] DATA1_[7:0]
HO[7:0]
HST[7:2]
BUF1
SEL0
DSIW
REG2 DSWST
REG4
REG7
BUF2
DSLA
DFME8
ENABLE ACLR CLOCK Q[6:0]
HI[15:8] A[7:0] DSI[15:8] B[7:0] Q[7:0] CIQ[15:8] DSI[14:8]
HST[14:8]
DATA[6:0]
HST14 MUX2 IQ[15:8]
MUX2X8
HICTLA ENHD1 ENHD2 HST[1:0] DPNT[1:0] SINT HSEL HRDY DSPINTR HCMDFL DSIW DSIW HICTLA HST15 DSPINTR HCMDFL HSEL SINT HST[15:8] ENHD1 ENHD2
DATA0_[7:0] RESULT[7:0] DATA1_[7:0]
HO[15:8]
SEL0
HSEL
AND2B
NAND2
DF1C
HOST INTERFACE (HINTRFA)
2002
DRAWN
NAND2
HSEL
INV1
OA1C
HCYC
HSEL
HCYC
DFM6A
HCYC
JKF2C
AND2B
HSEL
AND2B
SHWR INV3
HCYC HSEL
JKF2C
HCMD
HCYC
AND3B
SHCMD
JKF2C
INV4
LRDST
HSEL
AND3B
SLRDST
INV2
DSIW
DSPINTR
NOR2
NAND2
ENHD2
NOR2
NOR4
HRDY
NAND2
ENHD1
DPNT[1:0] DPNT0 DPNT1
NAND2B NAND3B
RDEN WREN
SINT CLRFLGS
OR3C
HCYC INTEN
EBSY
AND3
SINTR
DSPINTR
LRDST HCYC
AND2A
HCYC HCMD DSIW
AND2
HCCYC
HCMDFL
HICTLA
2002
DRAWN
CLRFLGS
DSI[7:0]
DSI0
DFE1B
PNT0
AND3B
DSI1
DFE1B
PNT1
AND3A
DSI2 DSWPNT
DFE1B
PNT2
DEC2 LR/W
DECE2X4D
CPCYC ADW0
NAND2
DSWPNT
ADW2 ADW3
DL1B
LR/W
CPCYC1 ADW2 CPCYC1 ADW3
AND3
DSIW
AND3
DSWST
ADW0 LR/W CPCYC1
AND4B
DSWDREG
DFE3A
BUF2
CPCYC
DFM6A
BUF3
CPCYC1
CPIS CPSTRB CPSEL
AND3B
DSPWA
2002
DRAWN
ST15
CH15
MUX2X16
CH15,GND,GND,GND[12:1],CH0
DATA0_[15:0]
DO[15:0]
RESULT[15:0]
IQ[15:0]
DATA1_[15:0]
GND[12:1]
SEL0
$ARRAY=12
IQSEL
DSPRA
2002
DRAWN
A[7:0]
B[7:0]
DFME1A
DFME1A
DFME1A
DFME1A
DFME1A
DFME1A
DFME1A
DFME1A
Q[7:0]
DFME8
NOV. 2002
DRAWN
EN1R1 EN1R3 DSPSEL DFME8 DSPSEL2 DFME8
MUX1
MUX4X8
CIQ[7:0]
R1[7:0] R1[7:0] Q[7:0] HI[7:0] A[7:0] Q[7:0] DSI[7:0] B[7:0] R3[7:0] R2[7:0] R3[7:0]
DATA0_[7:0] DATA1_[7:0] RESULT[7:0] DATA2_[7:0] DATA3_[7:0]
HI[7:0] A[7:0] DSI[7:0] B[7:0] EN2R1 EN2R3 HIH[15:8] A[7:0] Q[7:0] DSI[15:8] B[7:0] DSI[15:8] B[7:0] R1[15:8] HIH[15:8] A[7:0] Q[7:0] R3[15:8] MDS1 DFME8 DFME8
IQ[7:0]
SEL1
SEL0
MDS0
MUX2
AND4A
MUX4X8
EN1R2
DSIR
CIQ[15:8] R1[15:8]
DSPSEL1
DFME8 DOE1
DATA0_[7:0] DATA1_[7:0]
HI[7:0] A[7:0] Q[7:0] DSI[7:0] B[7:0] EN2R2 R2[7:0]
IQ[15:8]
RESULT[7:0]
MDS0
R2[15:8] MDS1 R3[15:8]
DATA2_[7:0] DATA3_[7:0]
DEC1
DECE2X4 DATA0
SEL1
SEL0
HIH[15:8] DSI[15:8] B[7:0] A[7:0]
DFME8
DATA1
EN1R1 EN1R2 EN1R3 MDS1 MDS0
R2[15:8] Q[7:0]
LA[1:0]
END1
ENABLE
DSPSEL RA[1:0]
DSPSEL1 DEC2 DSPSEL2
DECE2X4 DATA0 DATA1
EN2R1 EN2R2 EN2R3
DATREG
END2
ENABLE
2002
DRAWN
8-bit Host Interface (IOPIL8)
This design implements parallel interface with host processor utilizing 8-bit data bus. understanding underlying operation design only necessary designer intends make modifications. most cases this design implemented without changes. following notes should read while referencing schematics. IOPIL16 level schematic. timing host chip communication found section timing chip communication found section 4.7. description below identifies elements each schematic starting with host side signals. paragraph title identifies schematic(s) being described text. IOPIL8 host interface IOPIL8 shown sheet IOPIL8 incoming data HD[7:0] latched transparent latches when ~HG1 goes high. This would write from host latched data HI[7:0] goes IOPIL8 IOPIL8 Data from interface host, HO[7:0] enabled onto host bus, HD[7:0], HOES1. output latches, which present data during host read, always transparent because GOUT connected VDD. latched option Actel part used could omitted host interface different CPLD FPGA does have this feature. HD[15:8] tri-stated outputs because Actel grounds unused pins this would interfere with using existing test equipment. These reserved I/O's ommitted different implementation with bus. IOPIL8 control host interface starts IOPIL8 HOES1 ~HSEL ~HRD, enable read data onto host bus, previously described. HRDY handshaking signal host allow asynchronous communication between host host must wait until HRDY true before attempting communicate with This signal copied host status register. host status register read time determine state HRDY, HRDY output used interrupt host. ~HSEL, ~HRD, ~HWR, buffered inputs host control signals. HOST INTERFACE/IOPIL8 Data from host HI[7:0] written into REG1 REG2 schematic HOST INTERFACE ~EN1 ~EN2. transfers bits take writes reads 8-bit bus. These registers have multiplexed input with both host data data being written this register. This convenient diagnostic purposes very efficient Actel A42MX FPGA's, which multiplexer based configuration logic device used demands separate registers could used host data. schematic this register shown DFME8. Only commands checksums written registers REG1 REG2 while data written read from data registers, DATREG shown IOPIL8 These data registers buffer data sent from reducing number interrupts must handle. output from REG1 REG2, CIQ[15:8] CIQ[7:0] IOPIL8 where they multiplexed with other data registers. multiplexed result, IQ[15:8] IQ[7:0], multiplexed with HST[15:8] HST[7:0] output host status registers REG3 REG4. This four input mux, MUX4X8, also muxes data onto 8-bit bus. previously mentioned HRDY becomes HST15 read host. rest status register written provide information
MC3110 Technical Specifications
host. acts address bit, usually address bus. When host writing, indicates data high indicates command. When host reading, indicates data high indicates status. Read status only transaction allowed while HRDY low. During host write gate (G1:HOST INTERFACE) flops latch incoming data interface latches driving ~HG1 from start write transaction until first negative clock transition after first positive transition following start write cycle. This tail-biting circuit removes requirement hold time data bus. HICTLA Most control logic host interface shown schematic HICTLA. sequencer generates HCYC clock interval after interface been accessed host finished transaction. nature transaction, rd/wr, command/data, read status preserved three flops F13, Since transfers must take place over transfers required. toggle flop used determine whether cycle first second required. toggle flop initialized state, which indicates that this first transfer (high byte), writing host status This status read host HRDY writable addition flop associated gating determine present command transaction first second byte command. toggle flop gets into wrong state missed aborted transfer next command will back correct state. host write write, DSIW, enable REG1 REG2 HOST INTERFACE schematic discussed previously. host data write generates ~ENHD1 ~ENHD2 data registers DATAREG schematic. host writes ~EN2, ~EN1, ~ENHD2, ~ENHD1 also determined state toggle flop using HIEN LOEN. 1CMD used this logic ensure correct behavior when command correcting state toggle. logic bottom page generates interrupt, HRDY HCMDFL. HCMDFL used status indicate command. DSIW, writing REG1 REG2 HOST INTERFACE schematic clears interrupt reasserts HRDY. HRDY de-asserted during host transactions except read status, stays de-asserted until completed DSIW cycle that clears interrupt reasserts HRDY. mentioned previously data transfers from host data registers interrupt knows number data transfers that must take place after decoding command. places this number, 0-3, least significant bits host status register, HST[1:0]. These become DPNT[1:0] this page schematic enable interrupt read write. always leaves these bits unless setting multiple word data transfer. INTEN true LRDST, latched read status, false, HCYC will generate interrupt This will also hold HRDY false until after writes interface register, DSIW, thereby generating ~CLRFLGS. IOPIL8 interface shown sheet IOPIL8 incoming data DSD[15:0] latched transparent latches when ~DG1 ~DG2 high. This occurs completion write from chip. latched data DSI[15:8] DSI[7:0] schematic IOPIL8 IOPIL16 DSI[7:0] also goes IOPIL16 Data from interface DO[15:8] DO[7:0] enabled onto bus, DSD[15:0], DOE2 DOE1 respectively. output latches, which present data during read, always transparent because GOUT connected VDD. latched Actel part contains both input output latches. output latches could omitted interface different CPLD FPGA does have this feature. incoming address bits CPA0 CPA1 also latched using ~DG3. 20CK signal clock This clock derived from clock input.
MC3110 Technical Specifications
IOPIL8 control starts IOPIL8 control generated from ~CPSTRB, ~CPIS, CPSEL R/W. ~DG1, ~DG2, ~DG3 latch incoming data DOE1 DOE2 out-enable data from this chip tail-bite write avoid having specify hold times data. Flop divides 40MHz clock down MHz. clock could used this interface DSPWA write control contained schematic DSPWA. interface uses page addressing save pins. make page register. addition there address bits, LA1. write address selects page register with DSI[2:0] going page register selecting page successive transfers. read from address reads status register pages. Pages only ones implemented this device. latches level. write decoding generates DSIW which enables writes DFME8 registers reg1 reg2 shown HOST INTERFACE schematic. DSIW also clears interrupt restores HRDY. DSWST writes host status register also shown HOST INTERFACE schematic. DSWDREG implements writing data registers shown IOPIL8 DATREG. Finally logic bottom page generates CPCYC, 1-clock interval after cycle over that implements actual writes registers. data latches post cycle transfers keeps much logic synchronous possible given asynchronous devices, without requiring clocking several times speed. DSPRA read control contained schematic DSPRA. selects status latched address IQ[15:0] address only significant status bits bits (indicating interrupting host), indicating 8-bit host interface) (set during host command transfer during data transfer). HOST INTERFACE Both host special mode transfer data avoid unnecessary interrupts. This special mode under control transparent host. When receives command from host initializes transfer setting number transfers expected (0,1,2 LSB's host status register, REG3 REG4 HOST INTERFACE. This write (DSWST) also loads these bits into down counter DCNT2 IOPIL8 Note that low, which indicates host command, asynchronously clears this register enabling interrupts schematic HICTLA. DPNT[1:0] high, indicating host data transfer, SINT goes high indicating host cycle counter decremented. MXAD2 selects address from latched address bits page register contains counter contents DPNT[1:0] not. This allows have direct access registers using address 1,2,and page host other hand only read write data register, counter will auto decrement from down allowing host access registers DATAREG where REG1=R1 REG2=R3 REG3=R5 writes enabled decoders DECE2X4 while reads selected muxes, MUX1 MUX2 controlled muxes MDS1 MDS0. output data IQ[15:0] goes HOST INTERFACE schematic below IOPIL8 DSPRA below IOPIL8 write data HI[7:0] from host DSI[15:8] DSI[7:0] from Note that END1
MC3110 Technical Specifications
END2, write enables, both high DSWDREG, while they high time host writes controlled toggle flop. SINT enables DPINC only when toggle high after second transfer.
MC3110 Technical Specifications
HINTF HSTSEL
INBUF
IN17
HSEL
HSEL
HOST INTERFACE (HINTRFA) HO[7:0] HO[7:0]
HSTRD
INBUF
IN18
HSTWR
INBUF
IN19
HI[7:0] HI[7:0]
HADR0
INBUF
IN20
DSI[15:8] DSI[15:8] DSI[7:0] DSI[7:0] DPNT[1:0] HST[1:0] DSWST DSIW DSWST SINT DSIW CIQ[15:8] CIQ[7:0]
CIQ[7:0] CIQ[15:8]
SINT
IQ[7:0] IQ[7:0] HST14 IQ[15:8] IQ[15:8] HCMDFL DSPINTR HST15 ENHD1 ENHD2 HSEL
ST15 DSPINTR
OUTBUF
ENHD1 ENHD2
HRDY
AND2B
HOES1
OUTBUF
DSPINTR
OUT5
DSPINT
IOPIL8
2002
DRAWN
PNT0 PNT1
CSEL0 CSEL1 DSPRA ST15 ST15 IQ[15:0]
DSWDREG DSI[7:0] DSI[7:0] DSWST DSIW
DSWDREG
DSIW DSWST
IQ[15:0]
IN27
INBUF
IN28 DO[15:0] DO[15:0] IN26 CPSEL CPSTRB CPSEL CPSTRB DSPRA DSPWA CLKINT CPIS CPCYC CPCYC
CPR-W
INBUF
STRB
INBUF
IN30
INBUF
CKBUF 20CK
CPIS
CPSTRB CPIS CPSEL
NAND3B
CSACC
AND4B
DOE1 CLKIN
INBUF
40CK
DF1A
20CK
AND4B
DOE2
NAND3B
NAND3B
CSACC
CSACC
NAND4B
IOPIL8
2002
DRAWN
HIGH SLEW
HIGH SLEW
GOUT
TRIBUFF
GOUT
BBDLHS
BBDLHS
TRIBUFF
HIGH SLEW
HIGH SLEW
TRIBUFF
HD10
GOUT
GOUT
TRIBUFF
HD11
BBDLHS
BBDLHS
HIGH SLEW
HIGH SLEW
TRIBUFF
HD12
GOUT
TRIBUFF
HD13
GOUT
BBDLHS
BBDLHS
TRIBUFF
HD14
HIGH SLEW
HIGH SLEW
TRIBUFF
HD15
GOUT
GOUT
BBDLHS
BBDLHS
BYTE TRISTATE HI[7:0] AVOID LOADING BUSSES
HO[7:0]
HOES1
IOPIL8
2002
DRAWN
DOE1
HIGH SLEW
DOE1
HIGH SLEW
DOE2
HIGH SLEW
DOE2
HIGH SLEW
DSD0
DSD4
DSD8
DO12
DSD12
GOUT
DSI0
GOUT
DSI4
GOUT
DSI8
GOUT
DSI12
BBDLHS
BBDLHS
BBDLHS
BBDLHS
DOE1
DOE1
DOE2
HIGH SLEW
DOE2
HIGH SLEW
HIGH SLEW
HIGH SLEW
DSD1
DSD5
DSD9
DO13
DSD13
GOUT
DSI1
GOUT
DSI5
GOUT
DSI9
GOUT
DSI13
BBDLHS
BBDLHS
BBDLHS
BBDLHS
DOE1
HIGH SLEW
DOE1
DOE2
HIGH SLEW
DOE2
HIGH SLEW
HIGH SLEW
DSD2
DSD6
DO10
DSD10
DO14
DSD14
GOUT
DSI2
GOUT
DSI6
GOUT
DSI10
GOUT
DSI14
BBDLHS
BBDLHS
BBDLHS
BBDLHS
DOE1
HIGH SLEW
DOE2
DOE2
HIGH SLEW
DOE1
HIGH SLEW
DSD3
HIGH SLEW
DSD7 DO11
DO15 DSD11
DSD15
GOUT
GOUT
DSI3
DSI7
GOUT
GOUT
DSI11
DSI15
BBDLHS
BBDLHS
BBDLHS
BBDLHS
DSI[7:0]
DSI[15:8]
DO[15:8] DO[7:0] DOE2 DOE1
HIGH SLEW HIGH SLEW
DOE2
CPA0
CPA1
GOUT
GOUT
OUTBUF
BBDLHS
BBDLHS
20CK
CLKOUT
IOPIL8
2002
DRAWN
ENHD1 DSWDREG
OR2A
END1
DREG ENHD2 DOE1 CIQ[7:0] CIQ[7:0] CIQ[15:8] CIQ[15:8] HI[7:0] HI[7:0] SINT IQ[7:0] IQ[7:0] DSI[7:0] DSI[7:0] IQ[15:8] DSI[15:8] DSI[15:8] RA[1:0] LA[1:0] LA[1:0] END1 END2 END1 END2 DATREG RA[1:0] IQ[15:8] DPNT1 DPNT0 DOE1
OR2A
END2
AND3
NAND2B
DPINC
DCNT2
DSWST DPINC DSI[1:0]
SLOAD ENABLE ACLR CLOCK Q[1:0] DATA[1:0]
DPNT[1:0]
MXAD2
DATA0_[1:0] RESULT[1:0] DATA1_[1:0]
RA[1:0]
LA[1:0]
SEL0
IOPIL8
2002
DRAWN
REG1
HST[1:0]
MUX4X8
REG3 HI[7:0] A[7:0] Q[7:0] DSI[7:0] B[7:0] DSI[7:2]
DATA[5:0] CLOCK Q[5:0]
DFME8
REG6
IQ[7:0]
CIQ[7:0]
DSWST
ENABLE
HST[7:0]
DATA0_[7:0] DATA1_[7:0] RESULT[7:0]
HO[7:0]
IQ[15:8] HST[7:2] HST[15:8]
DATA2_[7:0] DATA3_[7:0]
BUF1 DSIW
REG2 DSWST
REG4
SEL1 SEL0
REG7
BUF2
DSLA
DFME8
ENABLE ACLR CLOCK Q[6:0]
TOGGLE HST[14:8]
HI[7:0] A[7:0] DSI[15:8] B[7:0] Q[7:0] CIQ[15:8] DSI[14:8]
TOGGLE
DATA[6:0]
SELECTS [15:8], BYTE FIRST
HST14
DSWST DSI15
NAND2
RSTOG
HICTLA ENHD1 ENHD2 HST[1:0] DPNT[1:0] RSTOG HSEL RSTOG HSEL SINT TOGGLE HRDY DSPINTR HCMDFL DSIW DSIW HICTLA SINT TOGGLE HST15 DSPINTR HCMDFL ENHD1 HST[15:8] ENHD2
HSEL
NAND2
AND2B
DF1C
HOST INTERFACE (HINTRFA)
2001
DRAWN
HSEL HSEL
INV1
OA1C
HCYC
HCYC
DFM6A
HCYC
JKF2C
AND2B
HSEL
AND2B
SHWR INV3
HCYC 1CMD TOGGLE
JKF2C
HCMD
NAND2A
HSEL
HCYC
AND3B
SHCMD
HCYC
DFE3A
LCMD
RSTOG HCYC
AND2A
1CMD
JKF2C
INV4
LRDST
TOGGLE (1ST BYTE)
HSEL
AND3B
SLRDST
INV2 TOGGLE 1CMD
OR2A
HIEN
AOI1
NAND3
ENHD2
DSPINTR
HIEN DSIW
LOEN 1CMD TOGGLE DPNT[1:0] DPNT0 DPNT1
AND2A
NAND3
NOR4
HRDY
ENHD1
LOEN DSIW
AOI1
NAND2B NAND3B
RDEN WREN
SINT CLRFLGS
OR3C
HCYC INTEN
EBSY
AND3
SINTR
DSPINTR
LRDST 1CMD TOGGLE
AND3A
AND2A
HCYC
ENINTR
HCYC HCMD DSIW
AND2
HCCYC
HCMDFL
HICTLA
2002
CLRFLGS
DRAWN
DSI[7:0]
DSI0
DFE1B
PNT0
AND3B
DSI1
DFE1B
PNT1
AND3A
DSI2 DSWPNT
DFE1B
PNT2 CPCYC DEC2 LR/W
DECE2X4D
NAND2
ADW0
DSWPNT
ADW2 ADW3
DL1B
LR/W CPCYC1 ADW2
AND3
DSIW
CPCYC1 ADW3
AND3
DSWST
ADW0 LR/W CPCYC1
AND4B
DSWDREG
DFE3A
BUF2
CPCYC
DFM6A
BUF3
CPCYC1
CPIS CPSTRB CPSEL
AND3B
DSPWA
2002
DRAWN
ST15
CH15
MUX2X16
CH15,VDD,GND,GND[12:1],CH0
GND[12:1]
DATA0_[15:0] RESULT[15:0]
DO[15:0]
$ARRAY=12 IQ[15:0]
DATA1_[15:0]
SEL0
IQSEL
DSPRA
2002
DRAWN
A[7:0]
B[7:0]
DFME1A
DFME1A
DFME1A
DFME1A
DFME1A
DFME1A
DFME1A
DFME1A
Q[7:0]
DFME8
NOV. 2002
DRAWN
EN1R1 EN1R3 DSPSEL DFME8 DSPSEL2 DFME8
MUX1
MUX4X8
CIQ[7:0] R1[7:0] R1[7:0] Q[7:0] DSI[7:0] B[7:0] EN2R1 EN2R3 HI[7:0] A[7:0] Q[7:0] DSI[15:8] B[7:0] DSI[15:8] B[7:0] EN1R2 DSPSEL1 HI[7:0] A[7:0] Q[7:0] DSI[7:0] B[7:0] EN2R2 DSIR HI[7:0] DSI[15:8] B[7:0] A[7:0] Q[7:0] R2[15:8]
DATA0_[7:0] DATA1_[7:0]
HI[7:0] A[7:0] HI[7:0] A[7:0] Q[7:0] DSI[7:0] B[7:0] R3[7:0] R3[7:0] R2[7:0]
IQ[7:0]
RESULT[7:0]
DATA2_[7:0] DATA3_[7:0]
SEL1 SEL0
DFME8 R1[15:8] HI[7:0] A[7:0] Q[7:0] R3[15:8] MDS1 DFME8
MDS0
MUX2
MUX4X8
AND4A
CIQ[15:8] DSIR R1[15:8]
DATA0_[7:0] DATA1_[7:0]
DFME8
DOE1 R2[7:0]
IQ[15:8]
RESULT[7:0]
MDS0
R2[15:8] R3[15:8]
DATA2_[7:0] DATA3_[7:0]
SEL1
SEL0
DFME8
MDS1 MDS1 MDS0
DSPSEL
LA[1:0]
DECE2X4
DSPSEL1 END1
DATA0 ENABLE DATA1
EN1R1 EN1R2 EN1R3
DSPSEL2 RA[1:0]
DECE2X4
END2
DATA0 ENABLE DATA1
EN2R1 EN2R2 EN2R3
DATREG
2002
DRAWN
Application Notes
Design Tips
following recommendations design circuits that utilize Motion Processor. Serial Interface serial configuration decode logic implemented (see section 7.2) data should tied high. This places serial interface default configuration 9600,n,8,1 after power reset. Controlling output during reset When motion processor reset state (when reset line held low) immediately after power outputs unknown state, causing undesirable motor movement. recommended that enable line motor amplifier held disabled state host processor some logic circuitry until communication motion processor established. This form delay circuit amplifier enable line after power enable line ANDed with reset line. Parallel word encoder input When using parallel word input motor position, useful also decode this information into User space. This allows current input value read using chip instruction ReadIO diagnostic purposes. Using standard system clock frequency often desirable share common clock among several components design. case Motion Processors possible clock below standard value 20MHz. this case system frequencies will reduced fraction input clock verses standard 20MHz clock. list below shows affected system Serial baud rate carrier frequency Timing characteristics shown section Cycle time
example, input clock 17MHz used with serial baud rate 9600 following timing changes will Serial baud rate decreases 9600 *17/20 8160 frequency decreases *17/20 Cycle time increases 102.4 µsec *20/17 120.48 µsec
MC3110 Technical Specifications
MC3110 Technical Specifications
RS-232 Serial Interface
interface between MC3110 chip RS-232 serial port shown following figure. Comments Schematic encode characteristics serial port such baud rate, number stop bits, parity, etc. will read these switches during initialization, these parameters also changed using SetSerialPort chipset command. connector wired shown connected directly serial port without requiring null modem cable.
MC3110 Technical Specifications
DS[0.15]
A[0.15] .1UF C1C2+ C2C2 .1UF SERXMIT SERRCV STRB2 ISR/W STRBIS2 RSIP9 DIP-8 74LS244 COULD IMPLEMENTED NAND4
RSIP9 DIP-8 SW10 SW11 SW12 SW13 SW14 SW15 SW16 74LS244 DS10 DS11 DS12 DS13 DS14 DS15 SW10 SW11 SW12 SW13 SW14 SW15 SW16
DS10 DS11 DS12 DS13 DS14 DS15
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 POSLIM1 NEGLIM1 AXISIN1 AXISOUT1 QUADA1 QUADB1 ~INDEX1 ~HOME1 HALL1A HALL1B HALL1C
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ~RAMSLCT ~PERIPHSLCT R/~W ~STROBE ~WRITEENBL W/~R
DS[0.15]
DS[0.15]
~HOSTINTRPT PWMMAG1 PWMMAG2 PWMMAG3 PWMSIGN1 PWMSIGN2 SRLRCV SRLXMT SRLENABLE I/OINTRPT PRLENABLE SYNCH ANALOG1 ANALOG2 ANALOG3 ANALOG4 ANALOG5 ANALOG6 ANALOG7 ANALOG8 ANALOGVCC ANALOGREFHIGH ANALOGREFLOW ANALOGGND
C1C2 C2T1IN T2IN R1OUT R2OUT VT1OUT T2OUT R1IN R2IN VTXD
.1UF
.1UF
.1UF CONNECTOR FEMALE WIRED SHOWN WILL CONNECT WITHOUT DUMMY MODEM.
AD232
RSCLK
CLOCKIN
CP2N11
~RESET
PERFORMANCE MOTION DEVICES BEDFORD LINCOLN, 01773 Title RS232 SERIAL INTERFACE Size Date:
Document Number Monday, July 2003
Sheet
422/485 Serial Interface
interface between MC3110 chip RS-422/485 serial port shown following figure. Comments Schematic included table determine jumper setup that matches chosen configuration. using RS485, last must have jumpers RS485 LAST. connector wiring example only. should wired according specification that accompanies connector which attached. correct operation, logic should provided that contains start serial configuration motion processor. Refer RS232 Serial Interface schematic example required logic. Note that RS485 interface cannot used point point mode. only used multidrop configuration where chip SrlEnable line used control transmit/receive operation serial transceiver. Chips multi-drop environment should operated different baud rates. This will result communication problems.
MC3110 Technical Specifications
TX-RX
TERMINATE TRANSMIT JMP3
JMP3
4.7K
SRLXMT SRLRCV SRLENABLE
4.7UF TANT .1UF
MAX491
HOST
CONNECTOR ANGLE MALE
JMP3 TX-RX
JMP3 TERMINATE RECEIVE
TYPE
RS422
RS485
RS485 LAST
NOTE:RS422 CAPABLE FULL DUPLEX USES PAIRS. RS485 HALF-DUPLEX PAIR DAISY CHAINED
USES RS485. SINGLE COMMUNICATE WITH RS422 HOST SHOWN TABLE. SINGLE PAIR WIRED EITHER P1-1,9 P1-2,3 Title RS485. Size Date:
PERFORMANCE MOTION DEVICES BEDFORD LINCOLN, 01773 RS422/485 Interface Document Number Thursday, April 2002
Sheet
Motor Interface
following schematic shows typical interface circuit between MC3110 amplifier output mode. Comments Schematic LMD18200 H-bridge driver used.
MC3110 Technical Specifications
HIGH FREQUENCY CERAMIC 100UF SHOULD PLACED CLOSE POSSIBLE PINS 18200. NATIONAL SEMI APPLICATION INFORMATION
>MOTOR+ MAG1 MPWR OUT1 OUT2 BRAKE MGND LMD18200 >MOTORIN4001 TYPICAL DIODES NATIONAL LMD18200 TYPICAL H-BRIDGE MOTOR DRIVERS .01UF .01UF
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 POSLIM1 NEGLIM1 AXISIN1 AXISOUT1 QUADA1 QUADB1 ~INDEX1 ~HOME1 HALL1A HALL1B HALL1C
AXIS1 QUADA1 QUADB1 INDX1 HOME1
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ~RAMSLCT ~PERIPHSLCT R/~W ~STROBE ~WRITEENBL W/~R
~HOSTINTRPT PWMMAG1 PWMMAG2 PWMMAG3 PWMSIGN1 PWMSIGN2 SRLRCV SRLXMT SRLENABLE I/OINTRPT PRLENABLE SYNCH
SIGN1
ANALOG1 ANALOG2 ANALOG3 ANALOG4 ANALOG5 ANALOG6 ANALOG7 ANALOG8 ANALOGVCC ANALOGREFHIGH ANALOGREFLOW ANALOGGND ~RESET CLOCKIN
CP24N11
PERFORMANCE MOTION DEVICES BEDFORD LINCOLN, 01773 Title Single Phase SIGN MAGNITUDE Size Date:
Document Number Tuesday, November 2002
Sheet
12-bit Parallel Interface
interface between MC3110 chip quad shown following figure. single channel also used provided meets interface timing requirements. Comments Schematic data bits written addressed address bits when this fashion address 4000 used axis address reserved chips with drives axis.
MC3110 Technical Specifications
DS[0.15] A[0.15] ISSTRBW EGND CS1A1 VREFH
DS10 DS11 DS12 DS13 DS14 DS15
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 POSLIM1 NEGLIM1 AXISIN1 AXISOUT1 QUADA1 QUADB1 ~INDEX1 ~HOME1 HALL1A HALL1B HALL1C
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ~RAMSLCT ~PERIPHSLCT R/~W ~STROBE ~WRITEENBL W/~R
VLOG
VREFH
DS[4.15] DS10 DS11 DS12 DS13 DS14 DS15 DB10 DB11
VOUTA
DACVA1
VOUTB
DACVA2
VOUTC
DACVA3
~HOSTINTRPT PWMMAG1 PWMMAG2 PWMMAG3 PWMSIGN1 PWMSIGN2 SRLRCV SRLXMT SRLENABLE I/OINTRPT PRLENABLE SYNCH ANALOG1 ANALOG2 ANALOG3 ANALOG4 ANALOG5 ANALOG6 ANALOG7 ANALOG8 ANALOGVCC ANALOGREFHIGH ANALOGREFLOW ANALOGGND
VOUTD
DACVA4
/LDAC /RESET VREFL
BURR-BROWN 7724,7725 PLCC
VREFL
DACS 0X4000+ 0,2,4,6.
RSCLK
CLOCKIN
~RESET
CLEAN SUPPLIES PROVIDED VREFH VREFL GENERALLY NECESSARY PROVIDE OFFSET ADJUST. CP2N11
ISA0 EA14U2
CS1-
ISSTRBW PERFORMANCE MOTION DEVICES BEDFORD LINCOLN, 01773 CS1A
STRBTHE LOGIC WITHIN DOTTED LINES EASILY IMPLEMENTED WITHIN CPLD.
A14-
PREFERRED LOGIC
Title Single Phase Size Date: Document Number Tuesday, November 2002
Sheet
16-bit Serial Interface
following schematic shows interface circuit between MC3110 dual 16-bit serial DAC. Comments Schematic data bits from chip latched 74H165 shift registers when writes address 400x hex, address bits latched DLAT latches decoded cycle. fed-back and-or gate latches, decoded WRF, next clock will clear sequencer flop DFF3. This will disable latch second clock will clear second DFF3 flop, forcing DACWRN low, setting first flop since will have gone high. DACWRN will clear 74109, SHFTCNTN. counter, 74161, also parallel loaded counter enabled going high. counter will start counting shift register start shifting until clock after DACWRN flop sets since load overrides count enable. When DACWR flop shift register will start shifting counter will count shifts. After shifts CNT15 from counter will high next clock will DACLAT flop SHFTCNTN flop. This will stop shift after shifts assert through depending address stored latch. 16th clock also counted causing counter roll over CNT15 low. next clock will therefore clear DACLAT flop causing latch signal through terminate bits data latched addressed DAC. control logic back original state waiting next write DACs SERCK 10MHz clock, 20MHz clock divided since AD1866 DACs will 20MHz.
MC3110 Technical Specifications
DACL DS[0.15]
NAND2 CLKINH DS[0.15] SH/LD 74165 DS15 DS10 DS11 DS12 DS13 DS14 SH/LD 74165 SHFTCNTN
SERCK SERCK
DS[0.15] ISR/W STRBCLK RSA0 ISR/W STRBCLK
A14N ISA0 STRB2 SHTCNTN RSWRF
74LS74
AND3 NOR2 SERCK AD1866 DLAT LOGIC LABELLED IMPLEMENTED CPLD MODULE PORTS REPRESENT INPUTS OUTPUTS FROM CPLD INPUT SIGNALS COMMON DLAT DACL SERCK 74109 DACL SDAT SDAT DACWRN LOAD 74161
DFF3
DFF3
SERD
SDAT
DGND AGND
SERCK
74109
+12VA OP497 100K Size Date:
DGND AGND
DACV1
DACV1
-12VA
PERFORMANCE MOTION DEVICES BEDFORD LINCOLN, 01773 Title SERIAL Document Number Thursday, April 2002
AD1866 AXIS SHOWN TYPICAL AXIS Sheet
Interface
following schematic shows interface circuit between MC3110 external ram. Comments Schematic capable directly addressing words 16-bit memory. will also paging register address word pages. schematic shows paging addressing 128KB chips, i.e. pages chip. page address decoding shown only possible paging bits. decoding time from memory output must exceed read with wait states. writes provide extra access time reverse data bus.
MC3110 Technical Specifications
D[0.15]
A[0.14]
DSISR/W EW/R EPGR3 74LS377 MPG0 MPG1 POS139 POS139 EPGR3 74LS377 PAGE REGISTER BITS MPG0 MPG1 DSCS2 WEW/R MCM6226 MPG0 MPG1 DSCS2 WEW/R MCM6226 NOTE:THE CRITICAL DECODE MEMORY ACCESS TIME DURING READ, REQUIRED ACCESS TIME FROM LOW. ILLUSTRATED THERE 100NS. ACCOMPLISH DECODING FROM PAGE WRITE MEMORY READ WRITE. DECODING WILL HAVE CAREFULLY DONE MEMORIES WITH SINGLE CHIP SELECT. NOTE: POS139 STANDARD WITH INVERTED OUTPUTS MPG0 MPG1 DSCS1 WEW/R MCM6226 MPG0 MPG1 DSCS1 WEW/R MCM6226
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 POSLIM1 NEGLIM1 AXISIN1 AXISOUT1 QUADA1 QUADB1 ~INDEX1 ~HOME1 HALL1A HALL1B HALL1C
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ~RAMSLCT ~PERIPHSLCT R/~W ~STROBE ~WRITEENBL W/~R
~HOSTINTRPT PWMMAG1 PWMMAG2 PWMMAG3 PWMSIGN1 PWMSIGN2 SRLRCV SRLXMT SRLENABLE I/OINTRPT PRLENABLE SYNCH ANALOG1 ANALOG2 ANALOG3 ANALOG4 ANALOG5 ANALOG6 ANALOG7 ANALOG8 ANALOGVCC ANALOGREFHIGH ANALOGREFLOW ANALOGGND
D[0.15]
A[0.14]
ISR/W PGR-
RSCLK
~RESET CLOCKIN
CP2N11
PERFORMANCE MOTION DEVICES BEDFORD LINCOLN, 01773 Title INTERFACE Size Date:
Document Number Tuesday, November 2002
Sheet
User-defined
interface between MC3110 chip bits user output bits user input shown following figure. Comments Schematic schematic implements word user output registered 74LS377's word user inputs read 244's. schematic decodes bits address possible addresses UIO0 through UIO7. Registers buffers shown only UIO0, implementation shown easily extended. lower address bits decoded provide user output words user input words bits.
MC3110 Technical Specifications
D[0.15]
A[0.14]
UI0-8 UI0-9 UI0-10 UI0-11 UI0-12 UI0-13 UI0-14 UI0-15 UI0n UI0n UI0-0 UI0-1 UI0-2 UI0-3 UI0-4 UI0-5 UI0-6 UI0-7 UI0n UI0n USER INPUTS WEUIO0 74LS377 USER OUTPUTS UO0-0 UO0-1 UO0-2 UO0-3 UO0-4 UO0-5 UO0-6 UO0-7 UIO0 UIO1 UIO2 UIO3 UIO4 UIO5 UIO6 UIO7
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 POSLIM1 NEGLIM1 AXISIN1 AXISOUT1 QUADA1 QUADB1 ~INDEX1 ~HOME1 HALL1A HALL1B HALL1C
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ~RAMSLCT ~PERIPHSLCT R/~W ~STROBE ~WRITEENBL W/~R
ISWEW/R WEUIO0 74LS377 UO0-8 UO0-9 UO0-10 UO0-11 UO0-12 UO0-13 UO0-14 UO0-15 NOR2 A12n
~HOSTINTRPT PWMMAG1 PWMMAG2 PWMMAG3 PWMSIGN1 PWMSIGN2 SRLRCV SRLXMT SRLENABLE I/OINTRPT PRLENABLE SYNCH
A12n UIOn UIO0 UI0n
LOGIC LABELED IMPLEMENTED CPLD. LOWER ADDRESS BITS, A0-A8, DECODED PROVIDE USER INPUTS USER OUTPUTS.
ANALOG1 ANALOG2 ANALOG3 ANALOG4 ANALOG5 ANALOG6 ANALOG7 ANALOG8 ANALOGVCC ANALOGREFHIGH ANALOGREFLOW ANALOGGND RSCLK ~RESET CLOCKIN
CP2N11
PERFORMANCE MOTION DEVICES BEDFORD LINCOLN, 01773 Title USER Size Date:
Document Number Tuesday, November 2002
Sheet
12-bit Interface
following schematic shows typical interface circuit between MC3110 quad complement converter used position input device. single channel also used provided meets interface timing requirements. Comments Schematic converter samples complement digital words. DACRD- used perform read also used load counter FFh. counter will reloaded each read will count significantly between reads. counter will therefore start counting down after last read will generate cvt- pulse after 12.75 µsec. conversions will take approximately µsec, data will available next reads after µsec. words from extended bits with 74LS244.
MC3110 Technical Specifications
DS[0.15] A[0.15] -5VA DACRDGND ENCNTVCC LOAD 74ALS169 DACRDGND LOAD 74ALS169 CVT2 DFF2 ENCNTGND AGND ISSTRBW/R AD7874 DS11 DS10 DS11 NOTE:SIGN EXTENTION COMPLEMENT DACRD2 74LS244 DS15 DS14 DS13 DS12
DS[0.15]
DS10 DS11 DS12 DS13 DS14 DS15
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 POSLIM1 NEGLIM1 AXISIN1 AXISOUT1 QUADA1 QUADB1 ~INDEX1 ~HOME1 HALL1A HALL1B HALL1C
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ~RAMSLCT ~PERIPHSLCT R/~W ~STROBE ~WRITEENBL W/~R
POS1 POS2 NOTE:FS INPUTS POS3 POS4 CVTDACRDU2
VIN1 VIN2
DB11 DB10
VIN3 VIN4
CONVST REFIN
REFOUT DGND AGND
~HOSTINTRPT PWMMAG1 PWMMAG2 PWMMAG3 PWMSIGN1 PWMSIGN2 SRLRCV SRLXMT SRLENABLE I/OINTRPT PRLENABLE SYNCH ANALOG1 ANALOG2 ANALOG3 ANALOG4 ANALOG5 ANALOG6 ANALOG7 ANALOG8 ANALOGVCC ANALOGREFHIGH ANALOGREFLOW ANALOGGND
RSCLK
CLOCKIN
~RESET
DACRD- WILL LOAD COUNTER 255. 12.8 USEC. AFTER LAST DACRDTHE COUNTER WILL REACH START NEXT CONVERSION. INPUT WILL CONVERTED USEC. READY NEXT READ USEC LATER.
DACRDB
CP2N11
NOTE:THE LOGIC LABELED IMPLEMENTEDIN PLD.
PERFORMANCE MOTION DEVICES BEDFORD LINCOLN, 01773 Title Size Date:
Document Number Tuesday, November 2002
Sheet
7.10 16-bit Input
interface between MC3110 chip converter parallel input position device shown following figure. Comments Schematic schematic shows used provide parallel position input. registers required output converters make 68-nanosecond access time worst-case timing A/D's specify nanoseconds data nanoseconds from data tri-state bus. Each time data read counter decimal. This provides 35.2-microsecond delay before next conversion. With 10-microsecond conversion time data will available next reads after microseconds. delay used provide position sample close actual position.
MC3110 Technical Specifications
DS[0.15] A[0.15] IMPLEMENTEDIN PLD. A11n NOTE:THE LOGIC LABELED AGND
DS[0.15] DACRDD0
ISSTRBW/R A11n
DACRDC1 2.2UF 2.2UF
BYTE
AGND1 AGND2 DGND
DS10 DS11 DS12 DS13 DS14 DS15
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 POSLIM1 NEGLIM1 AXISIN1 AXISOUT1 QUADA1 QUADB1 ~INDEX1 ~HOME1 HALL1A HALL1B HALL1C
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ~RAMSLCT ~PERIPHSLCT R/~W ~STROBE ~WRITEENBL W/~R
VANA
NOTE:FS INPUTS
AD976
AIN1 33.2 CVTGND
BUSY
~HOSTINTRPT PWMMAG1 PWMMAG2 PWMMAG3 PWMSIGN1 PWMSIGN2 SRLRCV SRLXMT SRLENABLE I/OINTRPT PRLENABLE SYNCH ANALOG1 ANALOG2 ANALOG3 ANALOG4 ANALOG5 ANALOG6 ANALOG7 ANALOG8 ANALOGVCC ANALOGREFHIGH ANALOGREFLOW ANALOGGND
ANALOG DEVICES SPECIFICATIONS ADITIONAL INFORMATION POWER BYPASSING.
RSCLK
CLOCKIN
CP2N11
~RESET
DACRDGND ENCNT2 LOAD 74ALS169
LOAD 74ALS169 LOAD 74ALS169 CVT2
DFF2 PERFORMANCE MOTION DEVICES BEDFORD LINCOLN, 01773 DACRD- WILL LOAD COUNTER 700. 38.4 USEC. AFTER DACRDTHE COUNTER WILL REACH START NEXT CONVERSION. INPUT WILL CONVERTED USEC. READY NEXT READ AFTER USEC. Title INPUT Size Date:
ENCNTA
DACRDGND
DACRDGND
DACRD-
Document Number Tuesday, November 2002
Sheet
7.11 External Gating Logic Index
typical circuit gating Index signal with encoder channels shown following schematic. Comments Schematic order proper operation Index signal when used position capture, signal must gated with encoder channels ensure that this signal only active when three signals LOW. motion processor does perform this gating internally.
MC3110 Technical Specifications
QUADA1 QUADB1 HOME1 QUADA1 QUADB1 INDEX1 INDX1
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 POSLIM1 NEGLIM1 AXISIN1 AXISOUT1 QUADA1 QUADB1 ~INDEX1 ~HOME1 HALL1A HALL1B HALL1C
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ~RAMSLCT ~PERIPHSLCT R/~W ~STROBE ~WRITEENBL W/~R
~HOSTINTRPT PWMMAG1 PWMMAG2 PWMMAG3 PWMSIGN1 PWMSIGN2 SRLRCV SRLXMT SRLENABLE I/OINTRPT PRLENABLE SYNCH ANALOG1 ANALOG2 ANALOG3 ANALOG4 ANALOG5 ANALOG6 ANALOG7 ANALOG8 ANALOGVCC ANALOGREFHIGH ANALOGREFLOW ANALOGGND
CLOCKIN
CP24N11 PERFORMANCE MOTION DEVICES BEDFORD LINCOLN, 01773 Title EXTERNAL GATING LOGIC INDEX Size Date: Document Number Tuesday, November 2002 Sheet
~RESET

MC3110 Single Chip Technical Specifications Brushed Servo Motion

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