PM7339 S/UNI-CDB SATURN USER NETWORK INTERFACE CELL DELINEATION B
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RELEASED DATASHEET PMC-2000313 ISSUE
PM7339 S/UNI-CDB
SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
PM7339 S/UNICDB
S/UNI-CDB
SATURN USER NETWORK INTERFACE QUAD CELL DELINEATION BLOCK
DATASHEET
PROPRIETARY CONFIDENTIAL ISSUE 2000
PMC-SIERRA, INC. PROPRIETARY CONFIDENTIAL PMC-SIERRA INC., CUSTOMERS' INTERNAL
RELEASED DATASHEET PMC-2000313 ISSUE
PM7339 S/UNI-CDB
SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
REVISION HISTORY Issue Issue Date 2000 March 2000 Details Change descriptions were corrected. SPLT Configuration registers were corrected. Document created.
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PM7339 S/UNI-CDB
SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
CONTENTS FEATURES APPLICATIONS REFERENCES. S/UNI-CDB BLOCK DIAGRAM. DATASHEET OVERVIEW.11 DIAGRAM DESCRIPTION. FUNCTIONAL DESCRIPTION. 8.10 8.11 SPLR PLCP LAYER RECEIVER. ATMF ACELL DELINEATOR RXCP-50 RECEIVE CELL PROCESSOR. RXFF RECEIVE FIFO CPPM CELL PLCP PERFORMANCE MONITOR. PRGD PSEUDO-RANDOM SEQUENCE GENERATOR/DETECTOR SPLT SMDS PLCP LAYER TRANSMITTER TXCP-50 TRANSMIT CELL PROCESSOR. TXFF TRANSMIT FIFO JTAG TEST ACCESS PORT. MICROPROCESSOR INTERFACE
NORMAL MODE REGISTER DESCRIPTION OPERATION 10.1 SOFTWARE INITIALIZATION SEQUENCE.
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PM7339 S/UNI-CDB
SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
TEST FEATURES DESCRIPTION 11.1 JTAG TEST PORT
D.C. CHARACTERISTICS ORDERING THERMAL INFORMATION. MECHANICAL INFORMATION.
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PM7339 S/UNI-CDB
SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
LIST REGISTERS REGISTER 000H, 100H, 200H, 300H: S/UNI-CDB CONFIGURATION REGISTER 001H, 101H, 201H, 301H: S/UNI-CDB CONFIGURATION REGISTER 002H, 102H, 202H, 302H: S/UNI-CDB TRANSMIT CONFIGURATION REGISTER 003H, 103H, 203H, 303H: S/UNI-CDB RECEIVE CONFIGURATION REGISTER 008H, 108H, 208H, 308H: SPLR CONFIGURATION REGISTER 00CH, 10CH, 20CH, 30CH: SPLT CONFIGURATION REGISTER 100H: S/UNI-CDB MASTER TEST REGISTER 400H: S/UNI-CDB MASTER TEST
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PM7339 S/UNI-CDB
SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
LIST FIGURES FIGURE CELL DELINEATION STATE DIAGRAM FIGURE VERIFICATION STATE DIAGRAM. FIGURE INPUT OBSERVATION CELL (IN_CELL) FIGURE OUTPUT CELL (OUT_CELL) FIGURE BI-DIRECTIONAL CELL (IO_CELL) FIGURE LAYOUT OUTPUT ENABLE BI-DIRECTIONAL CELLS
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PM7339 S/UNI-CDB
SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
LIST TABLES TABLE TABLE TABLE TABLE TABLE TABLE TABLE REGISTER MEMORY MAP. STATSEL[2:0] OPTIONS SPLR FORM[1:0] CONFIGURATIONS. SPLT FORM[1:0] CONFIGURATIONS TEST MODE REGISTER MEMORY INSTRUCTION REGISTER BOUNDARY SCAN REGISTER
TABLE CHARACTERISTICS. TABLE PACKAGING INFORMATION TABLE THERMAL INFORMATION
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PM7339 S/UNI-CDB
SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
FEATURES Quad cell delineation device operating maximum rate Mbit/s. Provides UTOPIA Level compatible ATM-PHY Interface. Implements Physical Layer Convergence Protocol (PLCP) transmission systems according AForum User Network Interface Specification ANSI TA-TSY-000773, TA-TSY-000772, E1transmission systems according ETSI 300-269 ETSI 300-270. Uses PMC-Sierra PM4341 T1XC, PM4344 TQUAD, PM6341 E1XC, PM6344 EQUAD framer/line interface chips applications. Provides programmable pseudo-random test pattern generation, detection, analysis features. Provides integral transmit receive HDLC controllers with 128-byte FIFO depths. Provides performance monitoring counters suitable accumulation periods second. Provides 8-bit microprocessor interface configuration, control status monitoring. Provides standard signal P1149.1 JTAG test port boundary scan board test purposes. power 3.3V CMOS technology with tolerant inputs. Available high density 256-pin SBGA package (27mm 27mm).
receiver section: Provides PLCP frame synchronization, path overhead extraction, cell extraction PLCP PLCP formatted streams. Provides 8-bit wide 16-bit wide Utopia FIFO buffer receive path with parity support, multi-PHY (Level control signals.
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PM7339 S/UNI-CDB
SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
Provides Aframing using cell delineation. Acell delineation optionally disabled allow passing cell bytes regardless cell delineation status. Provides cell descrambling, header check sequence (HCS) error detection, idle cell filtering, header descrambling (for with packets), accumulates number received idle cells, number received cells written FIFO, number errors. Provides four cell FIFO rate decoupling between line, higher layer processing entity. FIFO latency reduced changing number operational cell FIFOs. Provides programmable pseudo-random test-sequence detection 2321 length patterns conforming ITU-T O.151 standards) analysis features.
transmitter section: Provides 8-bit wide 16-bit wide Utopia FIFO buffer transmit path with parity support multi-PHY (Level control signals. Provides optional Acell scrambling, header scrambling (for with packets), generation/insertion, programmable idle cell insertion, diagnostics features accumulates transmitted cells read from FIFO. Provides four cell FIFO rate decoupling between line higher layer processing entity. FIFO latency reduced changing number operational cell FIFOs. Provides reference input locking transmit PLCP frame rate externally applied frame reference. Provides programmable pseudo-random test sequence generation 232-1 length sequences conforming ITU-T O.151 standards). Diagnostic abilities include single error insertion error insertion error rates ranging from 10-1 10-7.
Loopback features: Provides diagnostic loopbacks line loopbacks.
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PM7339 S/UNI-CDB
SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
APPLICATIONS ASwitches, Multiplexers, Routers SMDS Switches, Multiplexers Routers DSLAM Integrated Access Devices (IAD)
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SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
REFERENCES
ANSI T1.627 1993, "Broadband ISDN ALayer Functionality Specification". ANSI T1.646 1995, "Broadband ISDN Physical Layer Specification UserNetwork Interfaces Including DS1/ATM". AForum AUser-Network Interface Specification, V3.1, October, 1995. AForum "UTOPIA, APHY Interface Specification, Level Version June, 1995. Bell Communications Research, TA-TSY-000773 "Local Access System Generic Requirements, Objectives, Interface Support Switched Multi-megabit Data Service" Issue March 1990 Supplement December 1990. Draft Standard T/NA(91)17 "Metropolitan Area Network Physical Layer Convergence Procedure 2.048 Mbit/s", April 1994. ITU-T Recommendation O.151 "Error Performance Measuring Equipment Operating Primary Rate Above", October, 1992. ITU-T Recommendation I.432 "B-ISDN User-Network Interface Physical Layer Specification", 1993 ITU-T Recommendation G.704 "General Aspects Digital Transmission Systems; Terminal Equipments Synchronous Frame Structures Used 1544, 6312, 2048, 8488 kbit/s Hierarchical Levels", July, 1995.
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PM7339 S/UNI-CDB
SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
S/UNI-CDB BLOCK DIAGRAM
IEEE P1149.1 JTAG Test Access Port
TDATO[4:1] TOHM[4:1] TCLK[4:1]
SPLT Transmit Aand PLCP Framer
TXCP_50 Cell Processor
TXFF Cell FIFO
System
DTCA [4:1] TDAT[15:0] TPRTY TSOC TADR[4:0] TENB TFCLK PHY_ADR[2:0] ATM8 RFCLK RENB RADR[4:0] RSOC RPRTY RDAT[15:0] DRCA[4:1]
RCLK[4:1] RDATI[4:1] ROHM[4:1]
ATMF/SPLR Receive Aand PLCP Framer
RXCP_50 Cell Processor CPPM PLCP/cell Perf. Monitor
RXFF Cell FIFO
Microprocessor
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PM7339 S/UNI-CDB
SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
DATASHEET OVERVIEW
PM7339 S/UNI-CDB functionally equivalent PM7346 S/UNI-QJET placed DS3/E3/J2 Framer Bypass mode. devices software compatible compatible. This datasheet provides complete pin-out description S/UNICDB, well differences between these devices. software initialization sequence required device operate properly. This software initialization described section 10.1. complete functional register description, please refer SUNI-QJET Datasheet, PMC-960835.
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PM7339 S/UNI-CDB
SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
DIAGRAM S/UNI-CDB packaged 256-pin SBGA package having body size 27mm 27mm pitch 1.27
TDAT[10]
TDAT[14]
D[1]
D[5]
A[3]
A[7]
INTB
TRSTB
TOHM[4]
RCLK[4]
TDAT[9]
TDAT[13]
D[0]
D[4]
A[0]
A[2]
A[6]
A[9]
A[10]
TCLK[4]
TDATO[3]
TDAT[7]
TDAT[11]
TDAT[15]
D[2]
D[6]
A[1]
A[5]
A[8]
RSTB
TDATO[4]
ROHM[4]
TCLK[3]
TDAT[3]
TDAT[4]
TDAT[6]
TDAT[8]
TDAT[12]
D[3]
D[7]
A[4]
RDATI[4]
TOHM[3]
BIAS
TDATO[2]
TCLK[2]
RDATI[3]
TFCLK
TDAT[0]
TDAT[2]
TDAT[5]
TOHM[2]
ROHM[3]
RDATI[2]
ROHM[2]
TADR[2]
TADR[3]
TADR[4]
TDAT[1]
RCLK[3]
RCLK[2]
TDATO[1]
TOHM[1]
TSOC
TPRTY
TADR[1]
TCLK[1]
ROHM[1]
RCLK[1]
BIAS
TENB
TADR[0]
RDATI[1]
DTCA[2]
DTCA[3]
DTCA[4]
DTCA[1]
PHY_ADR[2]
BOTTOM
VIEW
PHY_ADR[1] PHY_ADR[0]
ATM8
DRCA[4]
DRCA[3]
DRCA[2]
DRCA[1]
RSOC
RENB
RADR[3]
RFCLK
RADR[4]
RADR[2]
RADR[1]
RADR[0]
RPRTY
RDAT[13]
RDAT[15]
RDAT[14]
RDAT[12]
RDAT[9]
FRMSTAT[2]
REF8KI
RDAT[11]
RDAT[10]
RDAT[8]
BIAS
RDAT[6]
RDAT[2]
TPOHCLK[4] REF8KO[4]
RPOHCLK[3] TPOHINS[2]
RPOH[2]
TPOHCLK[1] RPOHCLK[1]
BIAS
FRMSTAT[1] FRMSTAT[3] FRMSTAT[4]
RDAT[7]
RDAT[3]
TICLK[4]
TPOHINS[4]
RPOH[4]
TIOHM[3]
TPOHCLK[3]
RPOH[3]
TIOHM[2]
TPOHCLK[2] RPOHCLK[2]
TIOHM[1]
TPOHFP[1]
REF8KO[1]
RDAT[5]
RDAT[1]
TIOHM[4]
TPOHFP[4] RPOHCLK[4]
TPOH[3]
TPOHINS[3]
LCD[3]
TICLK[2]
TPOH[2]
LCD[2]
TICLK[1]
TPOHINS[1]
RPOH[1]
RDAT[4]
RDAT[0]
TPOH[4]
LCD[4]
TICLK[3]
TPOHFP[3]
REF8KO[3]
TPOHFP[2]
REF8KO[2]
TPOH[1]
LCD[1]
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PM7339 S/UNI-CDB
SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
DESCRIPTION Name TDATO[4] TDATO[3] TDATO[2] TDATO[1] Type Output Function Transmit Data (TDATO[4:1]). TDATO[4:1] contains transmit data stream when single-rail (unipolar) output format enabled TDATO[4:1] function selection controlled TFRM[1:0] TUNI bits S/UNI-CDB Transmit Configuration Registers. TDATO[4:1] updated falling edge TCLK[4:1] default, configured updated rising edge TCLK[4:1] through TCLKINV S/UNI-CDB Transmit Configuration Registers. Finally, TDATO[4:1] updated rising edge TICLK[4:1], enabled TICLK S/UNI-CDB Transmit Configuration Registers.
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SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
Name TOHM[4] TOHM[3] TOHM[2] TOHM[1]
Type Output
Function Transmit Overhead Mask (TOHM[4:1]). TOHM[4:1] indicates position overhead bits (non-payload bits) transmission system stream aligned with TDATO[4:1]. When PLCP formatted signal transmitted, TOHM[4:1] logic once transmission frame, indicates frame alignment. TOHM[4:1] delayed version TIOHM[4:1] input, indicates position each overhead transmission frame. TOHM[4:1] updated falling edge TCLK[4:1]. TOHM[4:1] function selection controlled TFRM[1:0] TUNI bits S/UNI-CDB Transmit Configuration Registers. TOHM[4:1] updated falling edge TCLK[4:1] default, enabled updated rising edge TCLK[4:1]. This sampling controlled TCLKINV S/UNI-CDB Transmit Configuration Registers. Finally, TOHM[4:1] updated rising edge TICLK[4:1], enabled TICLK S/UNI-CDB Transmit Configuration Registers.
TCLK[4] TCLK[3] TCLK[2] TCLK[1]
Output
Transmit Output Clock (TCLK[4:1]). TCLK[4:1] provides transmit direction timing. TCLK[4:1] buffered version TICLK[4:1] enabled update TDATO[4:1] TOHM[4:1] outputs rising falling edge.
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SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
Name RDATI[4] RDATI[3] RDATI[2] RDATI[1]
Type Input
Function Receive Data (RDATI[4:1]). RDATI[4:1] contains data stream when singlerail (unipolar) input format enabled. RDATI[4:1] function selection controlled RFRM[1:0] bits S/UNI-CDB Configuration Registers. RDATI[4:1] sampled rising edge RCLK[4:1] default, enabled sampled falling edge RCLK[4:1]. This sampling controlled RCLKINV S/UNI-CDB Receive Configuration Registers. Receive Overhead Mask (ROHM[4:1]). When PLCP Adirectmapped signal received, ROHM[4:1] pulsed once transmission frame, indicates frame alignment relative RDATI[4:1] data stream. When alternate frame-based signal received, ROHM[4:1] indicates position each overhead transmission frame. RLCV/ROHM[4:1] function selection controlled RFRM[1:0] bits S/UNI-CDB Receive Configuration Registers, PLCPEN SPLR Configuration register. RLCV[4:1], ROHM[4:1] sampled rising edge RCLK[4:1] default, enabled sampled falling edge RCLK[4:1]. This sampling controlled RCLKINV S/UNI-CDB Receive Configuration Registers.
ROHM[4] ROHM[3] ROHM[2] ROHM[1]
Input
RCLK[4] RCLK[3] RCLK[2] RCLK[1]
Input
Receive Clock (RCLK[4:1]). RCLK[4:1] provides receive direction timing. RCLK[4:1] externally recovered transmission system baud rate clock that samples RDATI[4:1] RLCV/ROHM[4:1] inputs rising falling edge.
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SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
Name REF8KI
Type Input
Function Reference Input (REF8KI). PLCP frame rate locked external reference applied this input internal phase-frequency detector compares transmit PLCP frame rate with externally applied reference adjusts PLCP frame rate. REF8KI input must transition high once every correct operation. REF8KI input treated asynchronous signal must "glitchfree". LOOPT register logic PLCP frame rate locked RPOHFP[x] signal instead REF8KI input.
TPOHINS[4] TPOHINS[3] TPOHINS[2] TPOHINS[1]
Input
Transmit Path Overhead Insertion (TPOHINS[4:1]). TPOHINS[4:1] controls insertion PLCP overhead octets TPOH[4:1] input. When TPOHINS[4:1] logic associated overhead TPOH[4:1] stream inserted transmit PLCP frame. When TPOHINS[4:1] logic PLCP path overhead generated inserted internally. TPOHINS[4:1] sampled rising edge TPOHCLK[4:1]. Transmit PLCP Overhead Data (TPOH[4:1]). TPOH[4:1] contains PLCP path overhead octets (Zn, which inserted transmit PLCP frame. octet data TPOH[4:1] shifted order from most significant (bit least significant (bit TPOH[4:1] sampled rising edge TPOHCLK[4:1].
TPOH[4] TPOH[3] TPOH[2] TPOH[1]
Input
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PM7339 S/UNI-CDB
SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
Name TCELL[4] TCELL[3] TCELL[2] TCELL[1]
Type Output
Function Transmit Cell Indication (TCELL[4:1]). TCELL[x] valid when TCELL S/UNI-CDB Misc. register (09BH, 19BH, 29BH, 39BH) set. TCELL[x] pulses once every cell (idle assigned) transmitted. TCELL[x] updated using timing derived from transmit input clock (TICLK[x]), active minimum TICLK[x] periods RCLK[x] periods loop-timed). Transmit PLCP Overhead Clock (TPOHCLK[4:1]). TPOHCLK[4:1] active when PLCP processing enabled. TPOHCLK[4:1] nominally 26.7 clock PLCP frame 33.7 clock based PLCP frame. TPOHFP[4:1] updated falling edge TPOHCLK[4:1]. TPOH[4:1], TPOHINS[4:1] sampled rising edge TPOHCLK[4:1]. Transmit Input Overhead Mask (TIOHM[4:1]). TIOHM[4:1] indicates position overhead bits when configured transmission system streams. TIOHM[4:1] delayed internally produce TOHM[4:1] output. When configured operation over transmission system sublayer, TIOHM[4:1] required, should logic When configured other transmission systems, TIOHM[4:1] logic each overhead position. TIOHM[4:1] logic transmission system contains overhead bits. TIOHM[4:1] sampled rising edge TICLK[4:1].
TPOHCLK[4] TPOHCLK[3] TPOHCLK[2] TPOHCLK[1]
Output
TIOHM[4] TIOHM[3] TIOHM[2] TIOHM[1]
Input
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SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
Name TICLK[4] TICLK[3] TICLK[2] TICLK[1]
Type Input
Function Transmit Input Clock (TICLK[4:1]). TICLK[4:1] provides transmit direction timing. TICLK[4:1] externally generated transmission system baud rate clock. internally buffered produce transmit clock output, TCLK[4:1], enabled update TDATO[4:1] TOHM[4:1] outputs TICLK[4:1] rising edge. TICLK[4:1] maximum frequency MHz. Receive PLCP Overhead Frame Position (RPOHFP[4:1]). RPOHFP[4:1] locates individual PLCP path overhead bits receive overhead data stream, RPOH[4:1]. RPOHFP[4:1] logic while (the most significant bit) path user channel octet (F1) present RPOH[4:1] stream. RPOHFP[4:1] updated falling edge RPOHCLK[4:1]. RPOHFP[4:1] available when PLCPEN register logic SPLR Configuration Register. Receive PLCP Overhead Data (RPOH[4:1]). RPOH[4:1] contains PLCP path overhead octets (Zn, extracted from received PLCP frame when PLCP layer in-frame. When PLCP layer loss frame state, RPOH[4:1] forced ones. octet data RPOH[4:1] shifted order from most significant (bit least significant (bit RPOH[4:1] updated falling edge RPOHCLK[4:1].
RPOHFP[4] RPOHFP[3] RPOHFP[2] RPOHFP[1]
Output
RPOH[4] RPOH[3] RPOH[2] RPOH[1]
Output
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PM7339 S/UNI-CDB
SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
Name RPOHCLK[4] RPOHCLK[3] RPOHCLK[2] RPOHCLK[1]
Type Output
Function Receive PLCP Overhead Clock (RPOHCLK[4:1]). RPOHCLK[4:1] active when PLCP processing enabled. frequency this signal depends selected PLCP format. RPOHCLK[4:1] nominally 26.7 clock PLCP frame 33.7 clock based PLCP frame. RPOHFP[4:1] RPOH[4:1] updated falling edge RPOHCLK[4:1]. Loss Cell Delineation (LCD[4:1]). LCD[4:1] active high signal which asserted while Acell processor detected Loss Cell Delineation defect.
LCD[4] LCD[3] LCD[2] LCD[1] FRMSTAT[4] FRMSTAT[3] FRMSTAT[2] FRMSTAT[1]
Output
Output
Framer Status (FRMSTAT[4:1]). FRMSTAT[4:1] active high signal which configured show when PLCP framer detected certain conditions. FRMSTAT[4:1] outputs programmed STATSEL[2:0] bits S/UNI-CDB Configuration Register indicate: PLCP Loss Frame, PLCP Frame, AIS, Loss Signal. FRMSTAT[4:1] should treated glitch free asynchronous signal. AInterface Width Selection (ATM8). ATM8 input determines whether S/UNI-CDB works with 8-bit wide interface (RDAT[7:0] TDAT[7:0]) 16-bit wide interface (RDAT[15:0] TDAT[15:0]). ATM8 logic then 8-bit wide interface chosen. ATM8 logic then 16-bit wide interface chosen.
ATM8
Input
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SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
Name TDAT[15] TDAT[14] TDAT[13] TDAT[12] TDAT[11] TDAT[10] TDAT[9] TDAT[8] TDAT[7] TDAT[6] TDAT[5] TDAT[4] TDAT[3] TDAT[2] TDAT[1] TDAT[0]
Type Input
Function Transmit Cell Data (TDAT[15:0]). This carries Acell octets that written selected transmit FIFO. TDAT[15:0] sampled rising edge TFCLK considered valid only when TENB simultaneously asserted S/UNI-CDB been selected TADR[4:2] PHY_ADR[2:0] inputs. S/UNI-CDB configured operate with 8-bit wide 16-bit wide Adata interface ATM8 input pin. When configured 8-bit wide interface, TDAT[15:8] used should tied ground.
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SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
Name TPRTY
Type Input
Function Transmit parity (TPRTY). transmit parity (TPRTY) signal indicates parity TDAT[15:0] TDAT[7:0] bus. configured 8-bit (via ATM8 input pin), then parity calculated over TDAT[7:0]. configured 16-bit bus, then parity calculated over TDAT[15:0]. parity error indicated status maskable interrupt. Cells with parity errors inserted transmit stream, TPRTY input unused. even parity selection made using TPTYP register bit. TPRTY sampled rising edge TFCLK considered valid only when TENB simultaneously asserted S/UNI-CDB been selected TADR[4:0] PHY_ADR[2:0] inputs.
TSOC
Input
Transmit Start Cell (TSOC). transmit start cell (TSOC) signal marks start cell TDAT bus. When TSOC high, first word cell structure present TDAT bus. necessary TSOC present each cell. interrupt generated TSOC high during word other than first word cell structure. TSOC sampled rising edge TFCLK considered valid only when TENB simultaneously asserted S/UNI-CDB been selected TADR[4:2] PHY_ADR[2:0] inputs.
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SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
Name TENB
Type Input
Function Transmit Multi-Phy Write Enable (TENB). TENB signal active input which used along with TADR[4:0] inputs initiate writes transmit FIFOs. When sampled using rising edge TFCLK, word TDAT written into transmit FIFO selected TADR[4:0] address bus. When sampled high using rising edge TFCLK, write performed, TADR[4:0] address latched identify transmit FIFO accessed. complete octet cell must written transmit FIFO before inserted into transmit stream. Idle cells inserted when complete cell available. Transmit Address (TADR[4:0]). TADR[4:0] used select FIFO (and hence port) that written using TENB signal FIFO whose cellavailable signal visible output. TADR[4:0] sampled rising edge TFCLK together with TENB. Note that null-PHY address invalid address will identified port S/UNI-CDB.
TADR[4] TADR[3] TADR[2] TADR[1] TADR[0]
Input
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Name
Type Output
Function Transmit Multi-Phy Cell Available (TCA). signal indicates when cell available transmit FIFO port selected TADR[4:0]. When high, indicates that corresponding transmit FIFO full complete cell written. When goes low, configured indicate either that corresponding transmit FIFO near full that corresponding transmit FIFO full. will transition rising edge TFCLK which samples Payload byte (TCALEVEL0=0) (TCALEVEL0=1) 8-bit interface (ATM8=1), rising edge TFCLK which samples Payload word (TCALEVEL0=0) (TCALEVEL0=1) 16-bit interface (ATM8=0) being polled same use. reduce FIFO latency, FIFO depth which indicates "full" one, two, three four cells. Note that regardless what fill level indicate "full" transmit cell processor store complete cells. tri-stated when either null-PHY address (1FH) address matching address space PHY_ADR[2:0] latched TFCLK) from TADR[4:2] inputs. polarity (with respect description above) inverted when TCAINV register logic
TFCLK
Input
Transmit FIFO Write Clock (TFCLK). This signal used write Acells four cell transmit FIFOs. TFCLK cycles lower instantaneous rate. Please note that TFCLK input tolerant, only input pin.
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Name DTCA[4] DTCA[3] DTCA[2] DTCA[1]
Type Output
Function Direct Access Transmit Cell Available (DTCA[4:1]). These output signals indicate when cell available transmit FIFO corresponding port. When high, DTCA[x] indicates that corresponding transmit FIFO full complete cell written. DTCA[x] configured indicate either that corresponding transmit FIFO near full accept more than four writes that corresponding transmit FIFO full. DTCA[x] will thus transition rising edge TFLCK which samples Payload byte (TCALEVEL0=0) (TCALEVEL0=1) 8-bit interface (ATM8=1), rising edge TFCLK which samples Payload word (TCALEVEL0=0) (TCALEVEL0=1) 16-bit interface (ATM8=0). reduce FIFO latency, FIFO depth which DTCA[x] indicates "full" one, two, three four cells. Note that regardless what fill level DTCA[x] indicate "full" transmit cell processor store complete cells. polarity DTCA[x] (with respect description above) inverted when TCAINV register logic DTCA[4:1] outputs used support Utopia Direct Access mode.
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Name RDAT[15] RDAT[14] RDAT[13] RDAT[12] RDAT[11] RDAT[10] RDAT[9] RDAT[8] RDAT[7] RDAT[6] RDAT[5] RDAT[4] RDAT[3] RDAT[2] RDAT[1] RDAT[0] RPRTY
Type Output
Function Receive Cell Data (RDAT[15:0]). This carries Acell octets that read from receive AFIFO selected RADR[4:0]. RDAT[15:0] tri-stated when RENB high. RDAT[15:0] updated rising edge RFCLK. S/UNI-CDB configured operate with 8-bit wide 16-bit wide Adata interface ATM8 input pin. RDAT[15:8] will remain tri-stated ATM8 logic RDAT[15:0] tri-stated when either null-PHY address (1FH) address matching address space PHY_ADR[2:0] latched from RADR[4:2] inputs when RENB high.
Output
Receive Parity (RPRTY). receive parity (RPRTY) signal indicates parity RDAT bus. S/UNI-CDB configured operate with 8-bit wide 16-bit wide Adata interface ATM8 input pin. 8-bit mode, RPRTY reflects parity RDAT[7:0]. 16-bit mode, RPRTY reflects parity RDAT[15:0]. even parity selection made using RXPTYP register bit. RPRTY tri-stated when either nullPHY address (1FH) address matching address space PHY_ADR[2:0] latched from RADR[4:2] inputs when RENB high.
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Name RSOC
Type Output
Function Receive Start Cell (RSOC). This signal marks start cell RDAT bus. RSOC marks start cell RDAT bus. RSOC tri-stated when either nullPHY address (1FH) address matching address space PHY_ADR[2:0] latched from RADR[4:0] inputs when RENB high.
RENB
Input
Receive Multi-Phy Read Enable (RENB). RENB signal used initiate reads from receive FIFOs. When sampled using rising edge RFCLK, byte read available) from receive FIFO selected RADR[4:0] address output RDAT bus. When sampled high using rising edge RFCLK, read performed RDAT[15:0], RPRTY, RSOC tristated, address RADR[4:0] latched select device port next AFIFO access. RENB must operate conjunction with RFCLK access FIFOs high enough rate prevent FIFO overflows. Alayer device de-assert RENB anytime unable accept another byte. Receive Address (RADR[4:0]). RADR[4:1] signal used select FIFO (and hence port) that read from using RENB signal FIFO whose cell-available signal visible output. RADR[4:0] sampled rising edge RFCLK together with RENB. Note that null-PHY address invalid address will identified port S/UNI-CDB.
RADR[4] RADR[3] RADR[2] RADR[1] RADR[0]
Input
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Name
Type Output
Function Receive Multi-Phy Cell Available (RCA). signal indicates when cell available receive FIFO port selected RADR[4:0]. configured de-asserted when either zero four bytes remain selected/addressed FIFO. will thus transition rising edge RFCLK after Payload byte (RCALEVEL0=1) (RCALEVEL0=0) output 8-bit interface (ATM8=1), after Payload word (RCALEVEL0=1) (RCALEVEL0=0) output 16-bit interface (ATM8=0) being polled same use. tri-stated when either null-PHY address (1FH) address matching address space PHY_ADR[2:0] latched RFCLK) from RADR[4:2] inputs. polarity (with respect description above) inverted when RCAINV register logic
RFCLK
Input
Receive FIFO Read Clock (RFCLK). This signal used read Acells from receive FIFOs. RFCLK must cycle lower instantaneous rate, high enough rate avoid FIFO overflows. Please note that RFCLK input tolerant, only input pin.
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Name DRCA[4] DRCA[3] DRCA[2] DRCA[1]
Type Output
Function Direct Access Receive Cell Available (DRCA[4:1]). These output signals indicate when cell available receive FIFO corresponding port. DRCA[4:1] configured deasserted when either zero four bytes remain FIFO. DRCA[4:1] will thus transition rising edge RFCLK after Payload byte (RCALEVEL0=1) (RCALEVEL0=0) output 8-bit interface (ATM8=1), after Payload word (RCALEVEL0=1) (RCALEVEL0=0) output 16-bit interface (ATM8=0). DRCA[4:1] outputs used support Utopia Direct Access mode.
PHY_ADR[2] PHY_ADR[1] PHY_ADR[0]
Input
Device Identification Address (PHY_ADR[2:0]). PHY_ADR[2:0] inputs most-significant bits address space which this S/UNI-CDB occupies. When PHY_ADR[2:0] inputs match TADR[4:2] RADR[4:2] inputs, then four quadrants determined TADR[1:0] RADR[1:0] inputs) this S/UNI-CDB selected transmit receive Aaccess. Note that null-PHY address invalid address will identified port S/UNI-CDB.
Input
Active Chip Select (CSB). This signal must enable S/UNI-CDB register accesses. used, (RDB determine register reads writes) then should tied inverted version RSTB.
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Name
Type Input
Function Active Write Strobe (WRB). This signal pulsed enable S/UNI-CDB register write access. D[7:0] clocked into addressed register rising edge while low. Active Read Enable (RDB). This signal pulsed enable S/UNI-CDB register read access. S/UNI-CDB drives D[7:0] with contents addressed register while both low. Bi-directional Data (D[7:0]). bidirectional data D[7:0] used during S/UNI-CDB register read write accesses.
Input
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0]
Input
Address (A[10:0]). address A[10:0] selects specific registers during S/UNI-CDB register accesses.
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Name RSTB
Type Input
Function Active Reset (RSTB). This signal asynchronously reset S/UNI-CDB. RSTB Schmitt-trigger input with integral pull-up resistor. Address Latch Enable (ALE). address latch enable (ALE) active-high latches address A[10:0] when low. When high, internal address latches transparent. allows S/UNI-CDB interface multiplexed address/data bus. integral pull-up resistor. Active Open-Drain Interrupt (INTB). This signal goes when unmasked interrupt event detected internal interrupt sources. Note that INTB will remain until active, unmasked interrupt sources acknowledged their source. Test Clock (TCK). This signal provides timing test operations that carried using IEEE P1149.1 test access port. Test Mode Select (TMS). This signal controls test operations that carried using IEEE P1149.1 test access port. sampled rising edge TCK. integral pull resistor. Test Data Input (TDI). This signal carries test data into S/UNI-CDB IEEE P1149.1 test access port. sampled rising edge TCK. integral pull resistor.
Input
INTB
Output
Input
Input
Input
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Name
Type Output
Function Test Data Output (TDO). This signal carries test data S/UNI-CDB IEEE P1149.1 test access port. updated falling edge TCK. tri-state output which inactive except when scanning data progress. Active Test Reset (TRSTB). This signal provides asynchronous S/UNI-CDB test access port reset IEEE P1149.1 test access port. TRSTB Schmitt triggered input with integral pull resistor. TRSTB must asserted during power sequence. Note that used, TRSTB must connected RSTB input.
TRSTB
Input
BIAS
Input
Bias (BIAS). When tied +5V, BIAS input used bias wells input pads that pads tolerate their inputs without forward biasing internal protection devices. When tied VDD, inputs bidirectional inputs will only tolerate input levels VDD.
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Name VDD[1] VDD[2] VDD[3] VDD[4] VDD[5] VDD[6] VDD[7] VDD[8] VDD[9] VDD[10] VDD[11] VDD[12] VDD[13] VDD[14] VDD[15] VDD[16] VDD[17] VDD[18] VDD[19] VDD[20] VDD[21] VDD[22] VDD[23] VDD[24] VDD[25] VDD[26] VDD[27] VDD[28]
Type Power
Function Power. Power pins should connected well-decoupled +3.3V supply.
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Name VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29]
Type Ground
Function Ground. Ground pins should connected GND.
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Name VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40]
Type Ground
Function Ground. Ground pins should connected GND.
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Name
Type
Function connect
connect
Notes Description: S/UNI-CDB inputs bi-directionals present minimum capacitive loading operate logic levels. S/UNI-CDB outputs bi-directionals have least drive capability. data outputs, D[7:0], have drive capability. FIFO interface outputs, RDAT[15:0], RPRTY, RCA, DRCA[4:1], RSOC, TCA, DTCA[4:1], have drive capability. outputs TCLK[4:1], TDATO[4:1], TOHM[4:1], TPOHFP[4:1], LCD[4:1], RPOH[4:1], RPOHCLK[4:1],
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RPOHFP[4:1] have drive capability. other outputs have drive capability. Inputs RSTB, ALE, TMS, TRSTB have internal pull-up resistors. RSTB, TRSTB, TMS, TDI, TCK, REF8KI, TFCLK, RFCLK, TICLK[4:1], RCLK[4:1] schmitt trigger input pads. RFCLK TFCLK only input pins they tolerant. Connecting signal these inputs result damage part. [42:1] ground pins internally connected together. Failure connect these pins externally cause malfunction damage S/UNI-CDB. VDD[28:1] power pins internally connected together. Failure connect these pins externally cause malfunction damage device. These power supply connections must utilized must connect common +3.3 ground rail, appropriate. During power-up power-down, voltage BIAS must kept equal greater than voltage [28:1] pins, avoid damage device.
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FUNCTIONAL DESCRIPTION SPLR PLCP Layer Receiver PLCP Layer Receiver (SPLR) Block integrates circuitry support PLCP frame processing. SPLR provides framing PLCP based transmission formats. SPLR frames based PLCP frames with maximum average reframe times respectively. Framing declared (out frame removed) upon finding valid, consecutive sets framing octets valid sequential path overhead identifier (POHID) octets. While framed, POHID octets examined. declared when error detected both octets when consecutive POHID octets found error. declared when state persists more than PLCP formats respectively. events intermittent, counter decremented rate 1/10 (E1, PLCP) incrementing rate. thus removed when inframe state persists more than signal signal. When declared, PLCP reframe initiated. When frame, SPLR extracts path overhead octets outputs them serially output RPOH, along with RPOHCLK RPOHFP outputs. Framing octet errors path overhead identifier octet errors indicated frame errors. interleaved parity errors block errors indicated. yellow signal extracted accumulated indicate yellow alarms. Yellow alarm declared when consecutive yellow signal bits logical removed when consecutive received yellow signal bits logical octet examined maintain nibble alignment with incoming transmission system sublayer stream.
ATMF ACell Delineator ACell Delineator (ATMF) Block integrates circuitry support HCS-based cell delineation non-PLCP based transmission formats. ATMF block accepts serial cell stream from upstream transmission system sublayer entity performs cell delineation locate cell boundaries. PLCP applications, Acell positions fixed relative PLCP frame, ATMF still performs cell delineation locate cell boundaries. Cell delineation process framing Acell boundaries using header check sequence (HCS) field found Acell header. CRC-8 calculation over first octets Acell header. When
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performing delineation, correct calculations assumed indicate cell boundaries. ATMF performs sequential bit-by-bit, nibble-by-nibble, byte-by-byte hunt correct sequence. This state referred HUNT state. When receiving serial cell stream from upstream transmission system sublayer entity, bit, nibble, byte boundaries determined from location overhead. When correct found, ATMF locks particular cell boundary assumes PRESYNC state. This state verifies that previously detected pattern false indication. pattern false indication then incorrect should received within next DELTA cells. that point transition back HUNT state executed. incorrect found this PRESYNC period then transition SYNC state made. this state synchronization relinquished until ALPHA consecutive incorrect patterns found. such event transition made back HUNT state. state diagram cell delineation process shown Figure Figure Cell delineation State Diagram
Correct (bit bit)
HUNT Incorrect (cell cell)
ESYNC
ALPHA consecutive incorrect HCS's (cell cell)
SYNC
DELTA consecutive correct HCS's (cell cell)
values ALPHA DELTA determine robustness delineation method. ALPHA determines robustness against false misalignments errors. DELTA determines robustness against false delineation synchronization process. ALPHA chosen DELTA chosen
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recommended ITU-T Recommendation I.432. These values result maximum average time frame stream carrying Acells directly mapped into information payload. Loss cell delineation (LCD) detected counting number incorrect cells while HUNT state. counter value stored RXCP-50 Count Threshold register. threshold default value which results application detection time application detection time counter value zero, output signal asserted every incorrect cell. RXCP-50 Receive Cell Processor Receive Cell Processor (RXCP-50) Block integrates circuitry support scrambled unscrambled cell payloads, scrambled unscrambled cell headers, header check sequence (HCS) verification, idle cell filtering, performance monitoring. RXCP-50 operates upon delineated cell stream. PLCP based transmissions systems, cell delineation performed SPLR. nonPLCP based transmission systems, cell delineation performed ATMF. Framing status indications from these blocks ensure that cells written RXFF while SPLR loss frame state, cells written RXFF while ATMF HUNT PRESYNC states. RXCP-50 descrambles cell payload field using self synchronizing descrambler with polynomial header portion cells optionally descrambled also. Note that cell payload scrambling enabled default S/UNI-CDB required ITU-T Recommendation I.432, disabled ensure backwards compatibility with older equipment. CRC-8 calculation over first octets Acell header. RXCP-50 verifies received using accumulation polynomial, coset polynomial added (modulo received octet before comparison with calculated result required AForum specification, ITU-T Recommendation I.432. RXCP-50 programmed drop cells containing error filter cells based cell header. Filtering according particular GFC, PTI, bits Acell header (the bits must logic programmable through RXCP-50 registers. More precisely, filtering performed when filtering enabled when errors found when checking enabled. Otherwise, cells passed regardless error conditions. Cells blocked pattern invalid filtering 'Match Pattern' 'Match Mask' registers
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programmed with certain blocking pattern. AIdle cells filtered default. Acells, Null cells (Idle cells) identified standardized header pattern 'H00, 'H00, 'H00 'H01 first octets followed valid octet. While cell delineation state machine SYNC state, verification circuit implements state machine shown Figure normal operation, verification state machine remains 'Correction' state. Incoming cells containing errors passed receive FIFO. Incoming single-bit errors corrected, resulting cell passed FIFO. Upon detection single-bit error multi-bit error, state machine transitions 'Detection' state. programmable hysteresis provided when dropping cells based errors. When cell with error detected, RXCP-50 programmed continue discard cells until (where cells received with correct HCS. cell discarded (see Figure Note that dropping cells errors only occurs while ATMF SYNC state. Cell delineation optionally disabled, allowing RXCP-50 pass data bytes receives.
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Figure
Verification State Diagram
ADELINEATIO SYNC STATE
Errors Detected (Pass Cell)
ALPHA consecutive incorrect HCS's HUNT state)
Apparent Multi-Bit rror (Drop Cell)
CORRECTION MODE Single Error (Correct error pass cell) DETE CTION MODE
Drop Cell
DELTA consecutive correct HCS's (From PRESYNC state)
Errors Detected consecutive cells (Pass Last ell)
RXFF Receive FIFO Receive FIFO (RXFF) provides FIFO management S/UNI-CDB receive cell interface. receive FIFO contains four cells. FIFO provides cell rate decoupling function between transmission system physical layer Alayer. general, management functions include filling receive FIFO, indicating when receive FIFO contains cells, maintaining receive FIFO read write pointers, detecting FIFO overrun underrun conditions. FIFO interface "UTOPIA Level compliant accepts read clock (RFCLK) read enable signal (RENB). receive FIFO output (RDAT[15:0]) tri-stated when RENB logic device address (RADR[4:0]) selected does match this device's address. interface indicates start cell (RSOC) receive cell available status (RCA DRCA[4:1]) when data read from receive FIFO (using rising edges
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RFCLK). (and DRCA[x]) status changes from available unavailable when FIFO either empty (RCALEVEL0=1) near empty (RCALEVEL0 logic This interface also indicates FIFO overruns maskable interrupt register bits. Read accesses while DRCA[x]) logic will output invalid data. CPPM Cell PLCP Performance Monitor Cell PLCP Performance Monitor (CPPM) Block interfaces directly SPLR accumulate interleaved parity error events, framing octet error events, block error events saturating counters. When PLCP framer (SPLR) declares loss frame, interleaved parity error events, framing octet error events, block error events, header check sequence error events counted. When accumulation interval signaled write CPPM register address space S/UNI-CDB Identification, Master Reset, Global Monitor Update register, CPPM transfers current counter values into holding registers resets counters begin accumulating error events next interval. counters reset such manner that error events occurring during reset period missed. PRGD Pseudo-Random Sequence Generator/Detector Pseudo-Random Sequence Generator/Detector (PRGD) block software programmable test pattern generator, receiver, analyzer. types test patterns (pseudo-random repetitive) conform ITU-T O.151. PRGD programmed generate pseudo-random pattern with length 232-1 bits user programmable pattern from bits length. addition, PRGD insert single errors error rate between 10-1 10-7. PRGD programmed check presence generated pseudo-random pattern. PRGD perform auto-synchronization expected pattern, generate interrupts detection loss specified pattern. PRGD accumulate total number bits received total number errors saturating 32-bit counters. counters accumulate over interval defined writes S/UNI-CDB Identification/Master Reset, Global Monitor Update register (register 006H) writes PRGD accumulation register. When accumulation forced either method, then holding registers updated, counters reset begin accumulating next interval. counters reset such that events missed. data then available
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holding registers until next accumulation. addition counters, record bits received immediately prior accumulation available. PRGD also programmed check repetitive sequences. When configured detect pattern length bits, PRGD will load bits from detected stream, determine whether received pattern repeats itself every subsequent bits. Should fail find such pattern, will continue loading checking until finds repetitive pattern. features (error counting, auto-synchronization, etc.) available pseudo-random sequences also available repetitive sequences. Whenever PRGD accumulation forced, PRGD stores snapshot bits received immediately prior accumulation. This snapshot examined order determine exact nature repetitive pattern received PRGD. pseudo-random repetitive pattern inserted/extracted PLCP payload. cannot inserted into Acell payload. SPLT SMDS PLCP Layer Transmitter SMDS PLCP Layer Transmitter (SPLT Block integrates circuitry support based PLCP frame insertion. SPLT automatically inserts framing (A1, path overhead identification (POHID) octets provides registers automatic generation octets. Registers provided path user channel octet (F1) path status octet (G1). interleaved parity octet (B1) FEBE subfield automatically inserted. DQDB management information octets, generated. type type patterns described TA-TSY-000772 automatically inserted. type page counter reset using register SPLT Configuration register. PLCP transmit frame cycle/stuff counter octet transmit stuffing pattern referenced REF8KI input pin. Alternately, fixed stuffing pattern inserted into cycle/stuff counter octet. looped timing operating mode provided where transmit PLCP timing derived from received timing. this mode, stuffing generated based received stuffing pattern determined SPLR block. When PLCP format enabled, pattern inserted.
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Stuff Length
C1(Hex)
REF8KI input provisioned loop time PLCP transmit frame externally applied reference. growth octets 00H. octets inserted from external device path overhead stream input, TPOH. TXCP-50 Transmit Cell Processor Transmit Cell Processor (TXCP-50) Block integrates circuitry support Acell payload scrambling, header check sequence (HCS) generation, idle/unassigned cell generation. TXCP-50 scrambles cell payload field using self synchronizing scrambler with polynomial header portion cells optionally also scrambled. Note that cell payload scrambling disabled S/UNI-CDB, though required ITU-T Recommendation I.432. generated using polynomial, coset polynomial added (modulo calculated octet required AForum specification, ITU-T Recommendation I.432. resultant octet optionally overwrites octet transmit cell. When transmit FIFO empty, TXCP-50 inserts idle/unassigned cells. idle/unassigned cell header fully programmable using five internal registers. Similarly, octet information field programmed with repeating pattern using internal register. TXFF Transmit FIFO Transmit FIFO (TXFF) provides FIFO management S/UNI-CDB transmit cell interface. transmit FIFO contains four cells. FIFO depth programmed four, three, two, cells. FIFO provides cell rate decoupling function between transmission system physical layer Alayer.
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general, management functions include emptying cells from transmit FIFO, indicating when transmit FIFO full, maintaining transmit FIFO read write pointers detecting FIFO overrun condition. FIFO interface "UTOPIA Level compliant accepts write clock (TFCLK), write enable signal (TENB), start cell (TSOC) indication, parity (TPRTY), Adevice address (TADR[4:0]) when data written transmit FIFO (using rising edges TFCLK). interface provides transmit cell available status (TCA DTCA[4:1]) which transition from "available" "unavailable" when transmit FIFO near full (when TCALEVEL0 logic when FIFO full (when TCALEVEL0 logic accept more writes. reduce FIFO latency, FIFO depth which DTCA[x] indicates "full" one, two, three four cells FIFODP[1:0] bits TXCP-50 Configuration register. programmed depth less than four, more than cell written after DTCA[x] asserted TXCP-50 still allows four cells stored FIFO. This interface also indicates FIFO overruns maskable interrupt register bit, write accesses while DTCA[x] logic processed. TXFF automatically transmits idle cells until full cell available transmitted. 8.10 JTAG Test Access Port JTAG Test Access Port block provides JTAG support boundary scan. standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE STCTEST instructions supported. S/UNI-CDB identification code 073390CD hexadecimal. 8.11 Microprocessor Interface microprocessor interface block provides normal test mode registers, logic required connect microprocessor interface. normal mode registers required normal operation, test mode registers used enhance testability S/UNI-CDB. register accessed follows: Table Register Memory Address 000H 001H 002H 100H 101H 102H 200H 201H 202H 300H 301H 302H Register S/UNI-CDB Configuration S/UNI-CDB Configuration S/UNI-CDB Transmit Configuration
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Address 003H 005H 103H 105H 203H 205H 006H 106H 007H 008H 009H 00AH 00BH 00CH 00DH 00EH 00FH 020H 021H 022H 023H 024H 025H 026H 027H 028H02FH 060H 061H 107H 108H 109H 10AH 10BH 10CH 10DH 10EH 10FH 120H 121H 122H 123H 124H 125H 126H 127H 128H12FH 160H 161H 206H 207H 208H 209H 20AH 20BH 20CH 20DH 20EH 20FH 220H 221H 222H 223H 224H 225H 226H 227H 228H22FH 260H 261H 306H 307H 308H 309H 30AH 30BH 30CH 30DH 30EH 30FH 320H 321H 322H 323H 324H 325H 326H 327H 328H32FH 360H 361H 303H 305H
Register S/UNI-CDB Receive Configuration S/UNI-CDB Interrupt Status S/UNI-CDB Identification, Master Reset, Global Monitor Update S/UNI-CDB Reserved S/UNI-CDB Clock Activity Monitor Interrupt Identification SPLR Configuration SPLR Interrupt Enable SPLR Interrupt Status SPLR Status SPLT Configuration SPLT Control SPLT Diagnostics Octet SPLT Octet CPPM Reserved CPPM Change CPPM Performance Meter CPPM Error Count CPPM Error Count CPPM PLCP Framing Error Event Count CPPM PLCP Framing Error Event Count CPPM PLCP FEBE Count CPPM PLCP FEBE Count CPPM Reserved RXCP-50 Configuration RXCP-50 Configuration
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Address 062H 063H 064H 065H 066H 067H 068H 069H 06AH 06BH 06CH 06DH 06EH 06FH 070H 071H07FH 080H 081H 082H 083H 084H 085H 086H 087H 088H 089H08FH 162H 163H 164H 165H 166H 167H 168H 169H 16AH 16BH 16CH 16DH 16EH 16FH 170H 171H17FH 180H 181H 182H 183H 184H 185H 186H 187H 188H 189H18FH 262H 263H 264H 265H 266H 267H 268H 269H 26AH 26BH 26CH 26DH 26EH 26FH 270H 271H27FH 280H 281H 282H 283H 284H 285H 286H 287H 288H 289H28FH 362H 363H 364H 365H 366H 367H 368H 369H 36AH 36BH 36CH 36DH 36EH 36FH 370H 371H37FH 380H 381H 382H 383H 384H 385H 386H 387H 388H 389H38FH
Register RXCP-50 FIFO/UTOPIA Control Config RXCP-50 Interrupt Enables Counter Status RXCP-50 Status/Interrupt Status RXCP-50 Count Threshold (MSB) RXCP-50 Count Threshold (LSB) RXCP-50 Idle Cell Header Pattern RXCP-50 Idle Cell Header Mask RXCP-50 Corrected Error Count RXCP-50 Uncorrected Error Count RXCP-50 Received Cell Count RXCP-50 Received Cell Count RXCP-50 Received Cell Count RXCP-50 Idle Cell Count RXCP-50 Idle Cell Count RXCP-50 Idle Cell Count RXCP-50 Reserved TXCP-50 Configuration TXCP-50 Configuration TXCP-50 Transmit Cell Status TXCP-50 Interrupt Enable/Status TXCP-50 Idle Cell Header Control TXCP-50 Idle Cell Payload Control TXCP-50 Transmit Cell Counter TXCP-50 Transmit Cell Counter TXCP-50 Transmit Cell Counter TXCP-50 Reserved
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Address 09BH 0A0H 0A1H 0A2H 0A3H 0A4H 0A5H0A7H 0A8H 0A9H 0AAH 0ABH 0ACH 0ADH 0AEH 0AFH 0B0H0FFH 19BH 1A0H 1A1H 1A2H 1A3H 1A4H 1A5H1A7H 1A8H 1A9H 1AAH 1ABH 1ACH 1ADH 1AEH 1AFH 1B0H1FFH 29BH 2A0H 2A1H 2A2H 2A3H 2A4H 2A5H2A7H 2A8H 2A9H 2AAH 2ABH 2ACH 2ADH 2AEH 2AFH 2B0H2FFH 39BH 3A0H 3A1H 3A2H 3A3H 3A4H 3A5H3A7H 3A8H 3A9H 3AAH 3ABH 3ACH 3ADH 3AEH 3AFH 3B0H3FFH
Register S/UNI-CDB Misc. PRGD Control PRGD Interrupt Enable/Status PRGD Length PRGD PRGD Error Insertion PRGD Reserved PRGD Pattern Insertion Register PRGD Pattern Insertion Register PRGD Pattern Insertion Register PRGD Pattern Insertion Register PRGD Pattern Detector Register PRGD Pattern Detector Register PRGD Pattern Detector Register PRGD Pattern Detector Register S/UNI-CDB Reserved S/UNI-CDB Master Test Register Reserved S/UNI-CDB Test
400H 401H 7FFH
register accesses, must low.
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NORMAL MODE REGISTER DESCRIPTION Normal mode registers used configure monitor operation S/UNI-CDB. Normal mode registers opposed test mode registers) selected when A[10] low. Notes Normal Mode Register Bits:
Writing values into unused register bits effect. However, ensure software compatibility with future, feature-enhanced versions product, unused register bits must written with logic zero. Reading back unused bits produce either logic logic zero; hence, unused register bits should masked software when read. configuration bits that written into also read back. This allows processor controlling S/UNI-CDB determine programming state block. Writable normal mode register bits cleared logic zero upon reset unless otherwise noted. Writing into read-only normal mode register locations does affect S/UNI-CDB operation unless otherwise noted. Certain register bits reserved. These bits associated with megacell functions that unused this application. ensure that S/UNI-CDB operates intended, reserved register bits must only written with suggested logic levels. Similarly, writing reserved registers should avoided. S/UNI-CDB requires software initialization sequence order guarantee proper device operation long term reliability. Please refer Section 10.1 this document details program this sequence. reserved bits must programmed order device function properly.
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Register 000H, 100H, 200H, 300H: S/UNI-CDB Configuration Reserved0: This reserved must programmed logic proper operation. DLOOP: DLOOP controls diagnostic loopback. When logic written DLOOP, diagnostic loopback disabled. When logic written DLOOP, transmit data stream looped receive direction. DLOOP should logic when either LLOOP LOOPT logic LLOOP: LLOOP controls line loopback. When logic written LLOOP, line loopback disabled. When logic written LLOOP, stream received RDATI ROHM looped TDATO TOHM outputs. Note that TDATO, TOHM, TCLK outputs referenced RCLK when LLOOP logic LOOPT: LOOPT selects transmit timing source. When logic written LOOPT, transmitter loop-timed receiver. When loop timing enabled, receive clock (RCLK) used transmit timing source. When logic written LOOPT, transmit clock (TICLK) used transmit timing source. nibble stuffing derived from REF8KI input, fixed internally Setting LOOPT disables effect TICLK TXREF bits S/UNI-CDB Transmit Configuration S/UNI-CDB Type Function 8KREFO DS27_53 TOCTA Reserved4 LOOPT LLOOP DLOOP Reserved0 Default
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Configuration registers (Reference: S/UNI-QJET Datasheet: PMC-960835) respectively, thereby forcing flow-through timing. Reserved4: This reserved must programmed logic proper operation. TOCTA: TOCTA enables octet-alignment nibble-alignment transmit cell stream transmission overhead when arbitrary transmission format chosen (TFRM[1:0] binary SPLT Configuration register When arbitrary transmission format chosen TOCTA logic Acell nibbles octets aligned arbitrary transmission format overhead boundaries TIOHM input). Nibble alignment chosen FORM[1:0] bits SPLT Configuration Byte alignment chosen these FORM[1:0] bits other value. number TICLK periods between transmission format overhead positions must divisible (for nibble alignment) (for byte alignment). When TOCTA logic octet alignment performed there restriction number TICLK periods between transmission format overhead positions. DS27_53: DS27_53 used select between long data structure words 16-bit mode bytes 8-bit mode) short data structure words 16-bit mode bytes 8-bit mode) Ainterface. When DS27_53 logic one, RXCP-50 TXCP-50 blocks configured operate with long data structure; when DS27_53 logic zero, RXCP-50 TXCP-50 configured operate with short data structure. 8KREFO: 8KREFO used, conjunction with PLCPEN SPLR Configuration Register select function REF8KO/RPOHFP/RFPO/RMFPO[x] output pin. When PLCPEN logic RPOHFP function will selected 8KREFO effect (note that RPOHFP inherently 8kHz reference). PLCPEN logic then 8KREFO logic then 8kHz reference will derived from RCLK[x] signal output REF8KO. 8KREFO PLCPEN both logic then RXMFPO register S/UNI-CDB Configuration register (Reference: S/UNI-QJET Datasheet: PMC-960835) will select either RFPO RMFPO function.
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Register 001H, 101H, 201H, 301H: S/UNI-CDB Configuration Reserved0: This reserved must programmed logic proper operation. Reserved1: This reserved must programmed logic proper operation. Reserved2: This reserved must programmed logic proper operation. Reserved3: This reserved must programmed logic proper operation. Reserved4: This reserved must programmed logic proper operation. STATSEL[2:0]: STATSEL[2:0] bits used select function FRMSTAT[4:1] output. selection shown following table: Table STATSEL[2:0] Options FRMSTAT output indication function Reserved PLCP Loss Frame Type Function STATSEL[2] STATSEL[1] STATSEL[0] Reserved4 Reserved3 Reserved2 Reserved1 Reserved0 Default
STATSEL[2:0]
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STATSEL[2:0]
FRMSTAT output indication function Reserved PLCP Frame Reserved Reserved Reserved Reserved
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Register 002H, 102H, 202H, 302H: S/UNI-CDB Transmit Configuration TNEGINV: TNEGINV provides polarity control outputs TOHM. When logic written TNEGINV, TOHM output inverted. When logic written TNEGINV, TOHM output inverted. TNEGINV setting does affect loopback data diagnostic loopback. TPOSINV: TPOSINV provides polarity control output TDATO. When logic written TPOSINV TDATO output inverted. When logic written TPOSINV TDATO output inverted. TPOSINV setting does affect loopback data diagnostic loopback. TCLKINV: TCLKINV provides polarity control output TCLK. When logic written TCLKINV, TCLK inverted outputs TDATO TOHM updated falling edge TCLK. When logic written TCLKINV, TCLK inverted outputs TDATO TOHM updated rising edge TCLK. Reserved3: This reserved must programmed logic proper operation. TICLK: TICLK selects transmit clock used update TDATO TOHM outputs. When logic written TICLK, buffered version input transmit clock, TCLK, used update TDATO TOHM
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Type
Function TXSETBIT[1] TXSETBIT[0] TXREF TICLK Reserved3 TCLKINV TPOSINV TNEGINV
Default
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edge selected TCLKINV bit. When logic written TICLK, TDATO TOHM updated rising edge TICLK, eliminating flow-through TCLK signal. TICLK effect LOOPT LLOOP logic TXREF: TXREF register determines TICLK[1] TIOHM[1] should used reference transmit clock overhead pulse, respectively, instead TICLK[X] TIOHM[X]. TXREF logic then TICLK[1] TIOHM[1] will used reference transmit clock overhead/frame pulse, respectively. TXREF logic then TICLK[X] TIOHM[X] will used reference transmit clock overhead/frame pulse, respectively, quadrant loop-timing enabled (LOOPT TXREF effect corresponding quadrant. Note that when TXREF logic unused TICLK[x] TIOHM[x] should tied power ground, left floating. TXSETBIT[1:0]: These bits must programmed logic proper operation.
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Register 003H, 103H, 203H, 303H: S/UNI-CDB Receive Configuration RNEGINV: RNEGINV provides polarity control input ROHM. When logic written RNEGINV, input ROHM inverted. When logic written RNEGINV, input ROHM inverted. RNEGINV setting does affect loopback data diagnostic loopback. RPOSINV: RPOSINV provides polarity control input RDATI. When logic written RPOSINV input RDATI inverted. When logic written RPOSINV input RDATI inverted. RPOSINV setting does affect loopback data diagnostic loopback. RCLKINV: RCLKINV provides polarity control input RCLK. When logic written RCLKINV, RCLK inverted inputs RDATI ROHM sampled rising edge RCLK. When logic written RCLKINV, RCLK inverted inputs RDATI ROHM sampled falling edge RCLK. Reserved3: This reserved must programmed logic proper operation Reserved4: This reserved must programmed logic proper operation Type Function RXSETBIT[1] RXSETBIT[0] Reserved5 Reserved4 Reserved3 RCLKINV RPOSINV RNEGINV Default
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Reserved5: This reserved must programmed logic proper operation. RXSETBIT[1:0]: These bits must programmed logic proper operation.
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Register 008H, 108H, 208H, 308H: SPLR Configuration EXT: disables internal transmission system sublayer timeslot counter from identifying DS1and overhead bits. allows transmission formats that unsupported internal timeslot counter supported using ROHM[x] input. When logic written EXT, input transmission system overhead (for formats) indicated using internal timeslot counter. This counter synchronized transmission system frame alignment using ROHM[x] (for Adirect-mapped formats). When logic written EXT, indications ROHM[x] identify each transmission system overhead bit. PLCPEN: PLCPEN enables PLCP framing. When logic written PLCPEN, PLCP framing enabled. PLCP format specified FORM[1:0] bits this register. When logic written PLCPEN, PLCP related functions SPLR block disabled. PLCPEN must programmed logic arbitrary framing formats. REFRAME: REFRAME used trigger reframing. When logic written REFRAME, S/UNI-CDB forced PLCP frame search frame alignment initiated. Note that only logic logic transition REFRAME triggers reframing; multiple write operations required ensure such transition. Type Function FORM[1] FORM[0] Reserved5 Reserved4 REFRAME PLCPEN Unused Default
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Reserved4: This reserved must programmed logic proper operation Reserved5: This reserved must programmed logic proper operation. FORM[1:0]: FORM[1:0] bits select PLCP frame format shown below. These bits must "11" direct mapped mode being used (PLCPEN=0 EXT=1). Table FORM[1] SPLR FORM[1:0] Configurations FORM[0] PLCP Framing Format
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Register 00CH, 10CH, 20CH, 30CH: SPLT Configuration EXT: disables internal transmission system sublayer timeslot counter from identifying overhead bits. allows transmission formats that unsupported internal timeslot counter must supported using TIOHM[x] input. When logic written EXT, input transmission system overhead (for formats) indicated using internal timeslot counter. This counter flywheels create appropriate transmission system alignment. This alignment indicated TOHM[x] output. When logic written EXT, indications TIOHM[x] identify each transmission system overhead bit. These indications flow through S/UNI-CDB appear TOHM[x] output where they mark transmission system overhead placeholder positions TDATO[x] stream. should only logic TFRM[1:0] bits S/UNI-CDB Transmit Configuration register both logic arbitrary framing format desired. PLCPEN: PLCPEN enables PLCP frame insertion. When logic written PLCPEN, DS1, PLCP framing inserted. PLCP format specified FORM[1:0] bits this register. When logic written PLCPEN, PLCP related functions SPLT block disabled. PLCPEN must logic arbitrary framing formats. Reserved3: This reserved must programmed logic proper operation. Type Function FORM[1] FORM[0] M1TYPE M2TYPE Reserved3 PLCPEN Unused Default
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M2TYPE: M2TYPE selects type code transmitted octet. These codes required systems implementing IEEE-802.6 DQDB protocol. When logic written M2TYPE, fixed pattern type code transmitted octet. When logic written M2TYPE, 1023 cyclic code pattern (starting with hexadecimal ending with hexadecimal) transmitted octet. Please refer TA-TSY-000772, Issue Supplement details codes. M1TYPE: M1TYPE selects type code transmitted octet. These codes required systems implementing IEEE-802.6 DQDB protocol. When logic written M1TYPE, fixed pattern type code transmitted octet. When logic written M1TYPE, 1023 cyclic code pattern (starting with hexadecimal ending with hexadecimal) transmitted octet. Please refer TA-TSY-000772, Issue Supplement details codes. FORM[1:0]: When PLCPEN FORM[1:0] bits TFRM[1:0] bits S/UNI-CDB Transmit Configuration register select Adirectmapped transmission frame format shown below. When PLCPEN FORM[1:0] bits along with TFRM[1:0] bits select transmission PLCP frame format shown below. When TOCTA then FORM[1:0] bits control cell alignment with respect transmission overhead given TIOHM[x] shown below. FORM bits have effect TOCTA Table FORM[1] SPLT FORM[1:0] Configurations FORM[0] PLCP Adirect-mapped Framing Format Cell alignment byte byte
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OPERATION
10.1 Software Initialization Sequence S/UNI-CDB come reset mode that consumes excess power. device functionality altered except excessive power consumption resulting excess heat dissipation which could lead long term reliability problems. software initialization sequence this section will S/UNI-CDB into normal power consumption state should device come reset excess power state. This reset sequence must used guarantee long term reliability device. Reset S/UNI-CDB. IOTST (bit Master Test Register writing 00000100 register 400H). S/UNI-CDBReceive Cell Processor (RXCP) into test mode writing: 00000101 test register 461H 00000101 test register 561H 00000101 test register 661H 00000101 test register 761H S/UNI-CDB Receive Cell Processor block built test (BIST) controls signals writing: 01000000 test register 462H 01000000 test register 562H 01000000 test register 662H 01000000 test register 762H 10101010 test register 463H 10101010 test register 563H 10101010 test register 663H
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10101010 test register 763H S/UNI-CDB Transmit Cell Processor (TXCP) into test mode writing: 00000011 test register 481H 00000011 test register 581H 00000011 test register 681H 00000011 test register 781H S/UNI-CDB Transmit Cell Processor block built test (BIST) controls signals writing: 10000000 test register 480H 10000000 test register 580H 10000000 test register 680H 10000000 test register 780H 10101010 test register 482H 10101010 test register 582H 10101010 test register 682H 10101010 test register 782H Toggle REF8KI (pin signal least eight times (this provides clock RAM). REF8KI test clock used TXCP RXCP blocks when test mode. IOTST (bit Master Test register writing 00000000 register 400H). Resume normal device programming.
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TEST FEATURES DESCRIPTION Simultaneously asserting (low) CSB, inputs causes digital output pins data held high-impedance state. This test feature used board testing. Test mode registers used apply test vectors during production testing S/UNI-CDB. Test mode registers opposed normal mode registers) selected when A[10] high. Test mode registers also used board testing. When TSBs within S/UNI-CDB placed test mode device inputs read device outputs forced microprocessor interface (refer section "Test Mode details). addition, S/UNI-CDB also supports standard IEEE 1149.1 five-signal JTAG boundary scan test port board testing. digital device inputs read digital device outputs forced JTAG test port. Table Test Mode Register Memory Address 000H-3FFH 400H 408H 409H 40AH 40CH 40DH 40EH 40FH 460H 461H 462H 463H 464H 508H 509H 50AH 50CH 50DH 50EH 50FH 560H 561H 562H 563H 564H 608H 609H 60AH 60CH 60DH 60EH 60FH 660H 661H 662H 663H 664H 708H 709H 70AH 70CH 70DH 70EH 70FH 760H 761H 762H 763H 764H Register Normal Mode Registers Master Test Register SPLR Test Register SPLR Test Register SPLR Test Register SPLT Test Register SPLT Test Register SPLT Test Register SPLT Test Register RXCP-50 Test Register RXCP-50 Test Register RXCP-50 Test Register RXCP-50 Test Register RXCP-50 Test Register
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Address 465H 480H 481H 482H 483H 484H 485H 4A0H 4A1H 4A2H 4A3H 565H 580H 581H 582H 583H 584H 585H 5A0H 5A1H 5A2H 5A3H 665H 680H 681H 682H 683H 684H 685H 6A0H 6A1H 6A2H 6A3H 765H 780H 781H 782H 783H 784H 785H 7A0H 7A1H 7A2H 7A3H
Register RXCP-50 Test Register TXCP-50 Test Register TXCP-50 Test Register TXCP-50 Test Register TXCP-50 Test Register TXCP-50 Test Register TXCP-50 Test Register PRGD Test Register PRGD Test Register PRGD Test Register PRGD Test Register
Notes Test Mode Register Bits: Writing values into unused register bits effect. However, ensure software compatibility with future, feature-enhanced versions product, unused register bits must written with logic zero. Reading back unused bits produce either logic logic zero; hence, unused register bits should masked software when read. Writable test mode register bits initialized upon reset unless otherwise noted.
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Register 100H: S/UNI-CDB Master Test
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Register 400H: S/UNI-CDB Master Test Type Function Unused A_TM[9] A_TM[8] PMCTST DBCTRL IOTST HIZDATA HIZIO Default
This register used enable S/UNI-CDB test features. bits, except PMCTST A_TM[9:8], reset zero hardware reset S/UNI-CDB. S/UNI-CDB Master Test register affected software reset (via S/UNI-CDB Identification, Master Reset, Global Monitor Update register (006H)). HIZIO, HIZDATA: HIZIO HIZDATA bits control tri-state modes S/UNI-CDB While HIZIO logic one, output pins S/UNI-CDB except data output held tri-state. microprocessor interface still active. While HIZDATA logic one, data also held high-impedance state which inhibits microprocessor read cycles. HIZDATA overridden DBCTRL bit. IOTST: IOTST used allow normal microprocessor access test registers control test mode each block S/UNI-CDB board level testing. When IOTST logic one, blocks held test mode microprocessor write block's test mode registers manipulate outputs block consequentially device outputs (refer "Test Mode Details" "Test Features" section). DBCTRL: DBCTRL used pass control data drivers pin. When DBCTRL logic either IOTST PMCTST logic one, controls output enable data bus. While DBCTRL set, holding high causes S/UNI-CDB
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drive data holding tri-states data bus. DBCTRL overrides HIZDATA bit. DBCTRL used measure drive capability data driver pads. PMCTST: PMCTST used configure S/UNI-CDB PMC's manufacturing tests. When PMCTST logic one, S/UNI-CDB microprocessor port becomes test access port used manufacturing test vectors. PMCTST logically "ORed" with IOTST bit, cleared setting logic writing logic zero bit. A_TM[9:8]: state A_TM[9:8] bits internally replace input address lines A[9:8] respectively when PMCTST logic This allows more efficient manufacturing test vectors. 11.1 JTAG Test Port S/UNI-CDB JTAG Test Access Port (TAP) allows access controller registers: instruction, bypass, device identification boundary scan. Using TAP, device input logic levels read, device outputs forced, device identified device scan path bypassed. more details JTAG port, please refer Operations section. Table Instruction Register
Length bits Instructions EXTEST IDCODE SAMPLE BYPASS BYPASS STCTEST BYPASS BYPASS Selected Register Boundary Scan Identification Boundary Scan Bypass Bypass Boundary Scan Bypass Bypass Instruction Codes, IR[2:0]
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PM7339 S/UNI-CDB
SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
Identification Register Length bits Version number Part Number 7346H Manufacturer's identification code 0CDH Device identification 273460CDH
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RELEASED DATASHEET PMC-2000313 ISSUE
PM7339 S/UNI-CDB
SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
Table
Boundary Scan Register
Length bits
Pin/Enable Register Cell Type Pin/Enable Register Cell Type
TDAT[15] TDAT[14] TDAT[13] TDAT[12] TDAT[11] TDAT[10] TDAT[9] TDAT[8] TDAT[7] TDAT[6] TDAT[5] TDAT[4] TDAT[3] TDAT[2] TDAT[1] TDAT[0] TFCLK TADR[4] TADR[3] TADR[2] TADR[1] TADR[0] TPRTY TSOC TENB
IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IN_CELL IN_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL
RX_OEB
67:70 71:74 75:78 79:82 83:86 87:90 91:94 95:98 99:102 103:106 107:110 112;115 116:119 120:123 124:127 128:131 132:135 136:139 140:143 144;147 148:151 152:155 156:159 160:163 170:180
OUT_CELL IN_CELL IN_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IN_CELL
TICLK[4;1] TIOHM[4:1] TPOH[4:1] TPOHINS[4:1] TPOHCLK[4:1] TPOHFP[4:1] LCD[4:1] RPOH[4:1] RPOHCLK[4:1] RPOHFP[4:1] FRMSTAT[4:1] REF8KI RCLK[4:1] ROHM[4:1] RDATI[4:1] TCLK[4:1] TOHM[4:1] TDATO4:1] INTB RSTB A[10:0] D[7] DOENB D[6] DOENB[6] D[5] DOENB
IN_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL
TCA_OEB DTCA[4] DTCA[3] DTCA[2] DTCA[1]
PHY_ADR[2] PHY_ADR[1] PHY_ADR[0] ATM8 DRCA[4] DRCA[3] DRCA[2] DRCA[1]
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PM7339 S/UNI-CDB
SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
RCA_OEB RSOC RENB RFCLK RADR[4] RADR[3] RADR[2] RADR[1] RADR[0] RPRTY RDAT[15:0]
50:65
OUT_CELL OUT_CELL OUT_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL
D[4] DOENB D[3] DOENB D[2] DOENB D[1] DOENB D[0] DOENB
IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL OUT_CELL
NOTES: TDAT[15] first boundary scan chain. TCA_OEB will tri-state when logic When logic will driven. RCA_OEB will tri-state when logic When logic will driven. RX_OEB will RDAT[15:0], RPRTY, RSOC tri-state when logic When logic RDAT[15:0], RPRTY, RSOC will driven. DOENB signals will corresponding bidirectional signal (the preceding DOENB boundary scan chain note also) output when logic When logic bidirectional signal will tri-stated. will outputs controlled TCA_OEB, RCA_OEB, RX_OEB, DOENB tri-state when logic When logic those outputs will driven. Boundary Scan Cell Description following diagrams, CLOCK-DR equal when current controller state SHIFT-DR CAPTURE-DR, unchanging otherwise. multiplexer center diagram selects four inputs, depending status select lines Code listed Boundary Scan Register table located TEST FEATURES DESCRIPTION JTAG Test Port section.
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RELEASED DATASHEET PMC-2000313 ISSUE
PM7339 S/UNI-CDB
SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
Figure
IDCODE
Input Observation Cell (IN_CELL)
Scan Chain INPUT internal logic
Input
SHIFT-DR
Scan Chain
I.D. Code CK-DR
Figure
Output Cell (OUT_CELL)
Scan Chain
EXTEST OUTPUT Enable from system logic IDCODE SHIFT-DR
OUTPUT Enable
I.D. code CLOCK-DR UPDAT E-DR
Scan Chain
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RELEASED DATASHEET PMC-2000313 ISSUE
PM7339 S/UNI-CDB
SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
Figure
Bi-directional Cell (IO_CELL)
Scan Chain INPUT internal logic
EXTEST OUTPUT from internal logic SHIFT-DR INPUT from
I.D. code UPDAT E-DR
Scan Chain
Figure
Layout Output Enable Bi-directional Cells
Scan Chain
OUTPUT ENABLE from internal logic drive) INPUT internal logic OUTPUT from internal logic
OUT_CELL
_CELL
Scan Chain
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SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
D.C. CHARACTERISTICS -40°C +85°C, 3.3V ±10%, BIAS 5.5V (Typical Conditions: 25°C, 3.3V, VBIAS Table
Symbol
Characteristics
Parameter Units Conditions
BIAS IBIAS
Power Supply Tolerant Bias Current into Bias Input Voltage
2.97
3.63
Volts Volts VBIAS 5.5V Guaranteed Input voltage.
Volts
Input High Voltage
BIAS
Volts
Guaranteed Input High voltage.
Output Bi-directional Voltage
0.23
Volts
Guaranteed output voltage VDD=2.97V IOL=maximum rated pad.
Output Bi-directional High Voltage
2.93
Volts
Guaranteed output High voltage VDD=2.97V IOH=maximum rated current pad.
Reset Input Voltage
Volts
Applies RSTB, TRSTB, TICLK[4:1], RCLK[4:1], TFCLK, RFCLK, TCK, TDI, TMS, REF8KI.
Reset Input High Voltage
Volts
Applies RSTB, TRSTB, TICLK[4:1], RCLK[4:1], TFCLK, RFCLK, TCK, TDI, TMS, REF8KI.
Reset Input Hysteresis Voltage
Volts
Applies RSTB, TRSTB, TICLK[4:1], RCLK[4:1], TFCLK, RFCLK, TCK, TDI, TMS, REF8KI. GND.
IILPU IIHPU COUT
Input Current Input High Current Input Current Input High Current Input Capacitance Output Capacitance
-100
VDD. GND.
VDD.
tA=25°C, tA=25°C,
PMC-SIERRA, INC. PROPRIETARY CONFIDENTIAL PMC-SIERRA INC., CUSTOMERS' INTERNAL
RELEASED DATASHEET PMC-2000313 ISSUE
PM7339 S/UNI-CDB
SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
Symbol
Parameter
Units
Conditions
IDDOP2 IDDOP6
Bi-directional Capacitance Operating Current
12.2
tA=25°C, 3.63V, Outputs Unloaded (T1/E1 PLCP mode) 3.63V, Outputs Unloaded Mbit/s arbitrary framing format with Adirect mapping)
Operating Current
258.3
Notes D.C. Characteristics: Input bi-directional with internal pull-up resistor. Input bi-directional without internal pull-up resistor Negative currents flow into device (sinking), positive currents flow device (sourcing). Utopia interface outputs, RDAT[15:0], RPRTY, RCA, DRCA[4:1], RSOC, TCA, DTCA[4:1], have drive capability. outputs TCLK[4:1], TDATO[4:1], TOHM[4:1], [4:1], RPOH [4:1], RPOHCLK [4:1], RPOHFP [4:1] have drive capability. data outputs, D[7:0], outputs specified above have drive capability. RFCLK TFCLK only input pins they tolerant. Connecting signal these inputs result damage part.
PMC-SIERRA, INC. PROPRIETARY CONFIDENTIAL PMC-SIERRA INC., CUSTOMERS' INTERNAL
RELEASED DATASHEET PMC-2000313 ISSUE
PM7339 S/UNI-CDB
SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
ORDERING THERMAL INFORMATION Table PART PM7339 Table PART PM7339 Packaging Information DESCRIPTION 256-pin Ball Grid Array (SBGA) Thermal Information CASE TEMPERATURE Theta -40°C 85°C °C/W Theta °C/W
PMC-SIERRA, INC. PROPRIETARY CONFIDENTIAL PMC-SIERRA INC., CUSTOMERS' INTERNAL
RELEASED DATASHEET PMC-2000313 ISSUE
PM7339 S/UNI-CDB
SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
MECHANICAL INFORMATION
0.127
BALL CORNER
-B.30
BALL CORNER
BALL I.D. MARK
0.127
VIEW BOTTOM VIEW
SIDE
SIDE VIEW
SEATING PLANE
SECTION VIEW
Notes: DIMENSIONS MILLIMETER. DIMENSION DENOTES COPLANARITY DIMENSION DENOTES PARALLEL DIMENSION DENOTES FLATNESS
PACKAGE TYPE: THERMAL BALL GRID ARRAY BODY SIZE: 1.45 Dim. Min. Nom. Max. 1.32 1.45 1.58 0.56 0.63 0.70 0.76 0.82 0.88 26.90 27.00 27.10 24.03 24.13 24.23 26.90 27.00 27.10 24.03 24.13 24.23 20x20 1.27 0.60 0.75 0.90 0.15 0.15 0.20 0.15 0.33 0.50 0.20 0.30 0.35
PMC-SIERRA, INC. PROPRIETARY CONFIDENTIAL PMC-SIERRA INC., CUSTOMERS' INTERNAL
RELEASED DATASHEET PMC-2000313 ISSUE
PM7339 S/UNI-CDB
SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
NOTES
PMC-SIERRA, INC. PROPRIETARY CONFIDENTIAL PMC-SIERRA INC., CUSTOMERS' INTERNAL
RELEASED DATASHEET PMC-2000313 ISSUE
PM7339 S/UNI-CDB
SATURN USER NETWORK INTERFACE CELL DELINEATION BLOCK
CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, Canada Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com http://www.pmc-sierra.com
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None information contained this document constitutes express implied warranty PMC-Sierra, Inc. sufficiency, fitness suitability particular purpose such information fitness, suitability particular purpose, merchantability, performance, compatibility with other parts systems, products PMC-Sierra, Inc., portion thereof, referred this document. PMC-Sierra, Inc. expressly disclaims representations warranties kind regarding contents information, including, limited express implied warranties accuracy, completeness, merchantability, fitness particular use, non-infringement. event will PMC-Sierra, Inc. liable direct, indirect, special, incidental consequential damages, including, limited lost profits, lost business lost data resulting from reliance upon information, whether PMC-Sierra, Inc. been advised possibility such damage. 2000 PMC-Sierra, Inc. PMC-2000313 (R1) PMC-960486 (R6) Issue date: March 2000
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