16-Bit Transparent D-Type Latch with 3-State Outputs PI74VCX Fami

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

16-Bit Transparent D-Type Latch with 3-State Outputs PI74VCX Fami

Datasheet Thumbnail

Top Searches for this datasheet

PI74VCX16373
16-Bit Transparent D-Type Latch with 3-State Outputs
PI74VCX Family designed voltage operation, 1.8V 3.6V 3.6V Tolerant Inputs Outputs Supports Live Insertion Balanced Drive, ±24mA Uses patented Noise Reduction Circuitry Typical VOLP (Output Ground Bounce) 0.6V 2.5V, Typical VOHV (Output Undershoot) -0.6V 2.5V, Power-Off high impedance inputs outputs Industrial operation 40°C +85°C Packages available: 48-pin mil. wide plastic TSSOP 48-pin mil. wide plastic SSOP
Product Description
Pericom Semiconductors PI74VCX series logic circuits produced Companys advanced 0.35 micron CMOS technology, achieving industry leading speed. PI74VCX16373 particularly suitable implementing buffer registers, ports, bidirectional drivers, working registers. This device used 8-bit latches 16bit latch. When Latch Enable (LE) input HIGH, outputs follow inputs. When taken LOW, outputs latched levels inputs. buffered Output Enable (OE) input used place eight outputs either normal logic state (high logic levels) high-impedance state which outputs neither load drive lines significantly. high-impedance state increased drive provide capability drive lines without need interface pullup components. does affect internal operations latch. data retained data entered while outputs high impedance state. ensure high-impedance state during power power down, should tied through pullup resistor; minimum value resistor determined current-sinking capability driver. PI74VCX family Tolerant, allowing operate mixed 1.8V/3.6V systems.
Logic Block Diagram
Seven Other Channels
Seven Other Channels
PS8326
09/14/98
PI74VCX16373 16-Bit Transparent D-Type Latch with 3-State Outputs Truth Table(1)
Inputs Outputs
Product Description
Name Description Output Enable Input (Active LOW) Latch Enable (Active HIGH) Data Inputs 3-State Outputs Ground Power
Product Configuration
Notes: High Signal Level Signal Level Don't Care Irrelevant High Impedance
48-PIN
PS8326
09/14/98
PI74VCX16373 16-Bit Transparent D-Type Latch with 3-State Outputs
Maximum Ratings
(Above which useful life impaired. user guidelines, tested.) Supply Voltage Range, -0.5V 4.6V Input Voltage Range, -0.5V 4.6V Output Voltage Range, (3-Stated) -0.5V 4.6V Output Voltage Range, VO(1) (Active) -0.5V 0.5V Input Diode Current (IIK) -50mA Output Diode Current (IOK) -50mA -50mA Output Source/Sink Current (IOH/IOL) ±50mA Current Supply (ICC GND) ±100mA Storage Temperature Range, TSTG -65°C to150°C
Note: Stresses greater than those listed under MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
Recommended Operating Conditions(2)
Parame cription Supply voltage High- level input voltage Low- level input voltage Input voltage utput voltage Active State State 3.0V 3.6V 2.3V 2.7V 1.8V Conditions perating Data Retention 2.7V 3.6V 2.7V 3.6V ns/V Units
utput current IOH/IOL Dt/Dv Input transistion rise fall rate(3) perating free- temperature
Notes: Absolute maximum must observed. Unused control inputs must held HIGH prevent them from floating. measured between 0.8V 2.0V, 3.0V.
PS8326
09/14/98
PI74VCX16373 16-Bit Transparent D-Type Latch with 3-State Outputs
Electrical Characteristics over Recommended Operating Free-Air Temperature Range
(unless otherwise noted)
Characteristics (2.7V 3.6V)
Parame cription HIGH Level Input Voltage Level Input Voltage -100 HIGH Level Output Voltage Level Output Voltage IOFF DIDD Input Leakage Current STATE Output Leakage Power- Leakage Current Quiescent Supply Current Increase input 0.0V, 3.6V 3.6V (VI,VO) 3.6V (VI,VO) 3.6V 0.6V, Other inputs ±5.0 Conditions Typ. Units
PS8326
09/14/98
PI74VCX16373 16-Bit Transparent D-Type Latch with 3-State Outputs
Characteristics (2.3V 2.7V)
Parame cription HIGH Level Input Voltage Level Input Voltage 100mA HIGH Level Output Voltage 12mA 18mA 100mA Level Output Voltage 12mA 18mA IOFF Input Leakage Current STATE Output Leakage 0.0V, 2.7V 3.6V ±5.0 Conditions Typ. Units
Power- Leakage Current (VI,VO) 3.6V Quiescent Supply Current (VI,VO) 3.6V
Characteristics (1.8V 2.3V)
Parame IOFF cription HIGH Level Input Voltage Level Input Voltage HIGH Level utput Voltage 100mA Level utput Voltage 100mA Input Leakage Current STATE utput Leakage 0.0V, 1.8V 3.6V (VI,VO) 3.6V Conditions ±5.0 Typ. Units
Power- Leakage Current (VI,VO) 3.6V uiescent Supply Current
Note: guaranteed
PS8326
09/14/98
PI74VCX16373 16-Bit Transparent D-Type Latch with 3-State Outputs
Electrical Characteristics
-40°C +85°C, 30pF, 3.3V 0.3V 2.5V 0.2V Symbol tPLH, tPHL tPLH, tPHL tPZH, tPZL tPHZ, tPLZ Parame Prop Delay, DTOQ Prop Delay, Output Enable Time Output Disable Time 1.8V Units
tOSHL, tOSLH Output Output Skew(2)
Notes: 50pF approximatly 300ps maximum specification. Skew defined absolute value difference between actual propagation delay separate outputs same device. specification applies outputs switching same direction, either HIGH (tOSHL) HIGH (tOSLH).
Setup Requirements
30pF, =3.3V 0.3V Symbol Parame Setup Time, Hold Time, Pulse Width, High Typ. =2.5V 0.2V Typ. =1.8V Typ. Units
Dynamic Switching Characteristics
Symbol VOLP Parame Quiet Output Dynamic Peak Conditions 50pF, VDD, +25°C Typical 0.25 0.25 Units
VOLP
Quiet Output Dynamic Valley 50pF, VDD,
VOLP
Quiet Output Dynamic Valley 50pF, VDD,
Capacitance
Symbol COUT Parame Input Capacitance Output Capacitance Power Dissipation Capacitance Conditions 1.8, 2.5V 3.3V, VDD, 1.8V, 2.5V 3.3V VDD, 1.8V, 2.5V 3.3V +25°C Typical Units
PS8326
09/14/98
PI74VCX16373 16-Bit Transparent D-Type Latch with 3-State Outputs Switch Position
Open
Test Circuits Switching Waveforms
Parameter Measurement Information (VDD 1.8V 3.6V)
Open 30pF
(See Note
tPLZ/tPZL tPHZ/tPZH
From Output Under Test
Pulse Width
Low-High-Low Pulse VDD/2
Setup, Hold, Release Timing
Data Input Timing Input VDD/2 VDD/2
High-Low-High Pulse
VDD/2
Propagaton Delay
VDD/2 Input tPLH tPHL
Notes: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output HIGH except when disabled output control. input pulses supplied generators having follow characteristics: MHz, 2ns, 2ns, measured from 90%, unless otherwise specified. outputs measured time with transition measurement.
Output tPHL Opposite Phase Input Transition tPLH
VDD/2 VDD/2
Enable Disable Timing
Output Control
(Active LOW)
VDD/2 tPZL VDD/2 +0.15V tPZH VDD/2 tPHZ -0.15V tPLZ
Output Waveform 2xVDD
(see Note
Output Waveform
(see Note
Pericom Semiconductor Corporation 2380 Bering Drive Jose, 95131 1-800-435-2336 (408) 435-1100 http://www.pericom.com
PS8326 09/14/98

16-Bit Transparent D-Type Latch with 3-State Outputs PI74VCX Fami

Top Searches for this datasheet

Other recent searches