Port PCI-to-PCI Bridge Datasheet Brief Product Features
|
|
|
Top Searches for this datasheet
PI7C7100
Port PCI-to-PCI Bridge
Datasheet Brief
Product Features
three ports compliant with Local Specification, Revision Compliant with PCI-to-PCI Bridge Architecture Specification, Revision 32-Bit Primary Secondary Ports Circular-Delta Architecture Concurrent primary secondary operation independent intra-secondary port channel reduce traffic primary port Provides arbitration sets secondary masters Programmable 2-level priority arbiters Disable control external arbiter Support transactions for: memory commands Type Type configuration conversion (downstream only) Type Type configuration forwarding Type special cycle configuration conversion Supports posted memory write buffers directions Implements delayed transactions configuration, memory read commands Supports positive medium decoding Enhanced address decoding 32-Bit address range 32-Bit memory-mapped address range addressing palette snooping ISA-aware mode legacy support first 64KB address range IEEE 1149.1 JTAG interface support Full scan support 3.3V core logic with tolerant 3.3V signaling interface 256-pin plastic PBGA package (NA256) Supports system transaction ordering rules Hot-Plug "Ready"
Product Description
Pericoms PI7C7100 first triple port PCI-to-PCI Bridge device designed fully compliant with 32-Bit, implementation Local Specification, Revision 2.1. PI7C7100 supports synchronous transactions between devices primary secondary buses both operating MHz. primary secondary buses also operate concurrent mode, resulting additional increase system performance. Concurrent operation offloads isolates unnecessary traffic from primary bus; thereby enabling master target device same secondary communicate even while primary busy.
Product Benefits
Triple port PCI-to-PCI Bridge increases number slots that supported system. Single PI7C7100 device instead PCI-to-PCI Bridge devices conserves board real estate provides less device load primary bus. Concurrent intra-secondary communication increases overall system performance reducing traffic primary bus. Devices secondary busses independently communicate while primary busy. Integrated two-level programmable arbiter support devices each secondary maximizes master device control. internal arbiter bypassed with external arbiter custom applications. Synchronous clock operation primary secondary busses Enhanced bridge performance efficiency through support delayed transactions.
PXXXX
06/01/00
PI7C7100 Port PCI-to-PCI Bridge
Primary Arbiter REQ/GNT Transaction Queue Buffers
PRIMARY INTERFACE
Transaction Queue Data Buffers Arbiter REQ/GNT (Qty.
Configuration Registers
Clock (Qty. PRIMARY SECONDARY CONTROL PRIMARY MASTER/ TARGET INTERFACE
Transaction Queue Data Buffers Arbiter REQ/GNT (Qty.
SECONDARY INTERFACE
PXXXX
MASTER/ TARGET INTERFACE
SECONDARY INTERFACE
Datasheet Brief
PI7C7100 Block Diagram
MASTER/ TARGET INTERFACE
06/01/00
PI7C7100 Port PCI-to-PCI Bridge PI7C7100 Information
P_AD [31:0] P_CBE [3:0] P_PAR P_FRAME# P_IRDY# P_TRDY# P_DEVSEL# P_STOP# P_LOCK# P_IDSEL P_PERR# P_SERR# P_REQ# P_GNT# PRIMARY INTERFACE SECONDARY INTERFACE S1_AD[31:0] S1_CBE [3:0] S1_PAR S1_FRAME# S1_IRDY# S1_TRDY# S1_DEVSEL# S1_STOP# S1_LOCK# S1_IDSEL S1_PERR# S1_SERR# S1_REQ# [7:0] S1_GNT# [7:0] S1_RESET# S1_EN P_RESET# P_M66EN P_CLK P_FLUSH# CONTROL INPUT CLOCK CONTROL
Datasheet Brief
S_CLKOUT [15:0] S_CFN# S_M66EN
S2_AD [31:0] S2_CBE [3:0] S2_PAR TRST# JTAG INTERFACE SECONDARY INTERFACE FULL TEST SCAN S2_FRAME# S2_IRDY# S2_TRDY# S2_DEVSEL# S2_STOP# S2_LOCK# S2_IDSEL S2_PERR# S2_SERR# S2_REQ# [7:0] S2_GNT# [7:0] S2_RESET# S2_EN
SCANEN
PXXXX
06/01/00
PI7C7100 Port PCI-to-PCI Bridge Applications
PI7C7100 extends systems load capability limit beyond that single bus. dual secondary ports this device allows system designers more devices, more option card slots, than single support. Implementing special concurrent feature PI7C7100 enables maximum data through-put between primary secondary buses with minimal system loading. Figure shows PI7C7100 system block diagram traditional bridge application illustrate system performance enhancement resulting from implementing PI7C7100.
Datasheet Brief
System Memory
System Memory
Concurrent Mode. Minimal Traffic
Traffic Primary
Primary Bus, MHz, 32-Bit
Single Load Secondary MHz, 32-Bit
PERICOM
Minimal Latency Between Busses
Loads Secondary
P2P1
Extra Latency P2P2 Between Busses
Line Interface Card
Line Interface Card
Line Interface Card
Line Interface Card
Line Interface Card
Line Interface Card
Line Interface Card
Line Interface Card
Figure Pericom's Three Port Traditional Port System Architecture
Pericom Semiconductor Corporation 2380 Bering Drive Jose, 95131 1-800-435-2336 (408) 435-1100 http://www.pericom.com
PXXXX 06/01/00
Other recent searches
UNR5225G - UNR5225G UNR5225G Datasheet
UNR5226G - UNR5226G UNR5226G Datasheet
SS05015M - SS05015M SS05015M Datasheet
SM5411 - SM5411 SM5411 Datasheet
LR72A - LR72A LR72A Datasheet
HV91xx - HV91xx HV91xx Datasheet
HAT2064R - HAT2064R HAT2064R Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
