Source Driver Features Output output channels 6-bit resolution gr
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NT3965
Source Driver
Features Output output channels 6-bit resolution gray scale inversion with polarity control adjusting Gamma correction Power driving voltage Output dynamic range AVDD-0.1V Power consumption analog circuit General Description NT3965 data driver color panel, SXGA applications. better performance, inversion wide range voltage output designed this chip reducing EMI, data inversion control used. This chip supplies sections voltage-reference Gamma correction. Power interface circuit 3.6V Operating frequency 55MHz Output deviation 20mV Data inverting reducing Cascade function with bi-direction shift control CMOS silicon gate p-type substrate package
Block diagram
OUT1 OUT2 OUT3 OUT384 OUT383
Driver Buffer channels
Digit Analog Converter
REV1
Level Shift
Decoder
Line Latch bits
Decoder
REV2 DIO1
64-bit Shift Register
DIO2
AVDD
AVSS
Version
NT3965 Source Driver
NT3965 Pads configuration (Face down): This figure does specify package.
DIO1 REV1 REV2 AVSS AVDD DIO2
OUT1 OUT2 OUT3 OUT4 OUT5
NT3965
OUT380 OUT381 OUT382 OUT383 OUT384
Version
NT3965 Source Driver
Description
Designation REV1 REV2 OUT1 OUT384 Description
Data input. 6-bit, pixels, color data MSB;
Controls whether D00~D25 data inverted not. When "REV1"=1 these data will inverted. "00" 3F", 38", "2A," Controls whether data D30~D55 inverted not, same REV1. Clock input; latching data onto line latches rising edge. Gamma correction reference voltage. voltage these pins must AVSS< V10< V8<V7<V6; V5<V4<V3<V2<V1< AVDD Output drive signals
DIO1 DIO2
AVDD AVSS
Selects left right shift; SHL="1" DIO2 SHL="0" DIO1 DIO2 SHIFT Input Output Right Output Input Left Start pulse signal input/output When applied high (SHL="1"), start high-pulse DIO1 latched rising edge CLK. Then data latched serially onto internal latches rising edge CLK. After line latches filled with data, clocks, pulse shifted through DIO2 rising edge CLK. This function cascade more devices dot-size expansion. normal applications, DIO2 signal first device connected DIO1 second stage, DIO2 second connected DIO1 third, chain. contrast, when applied low, start pulse inputs DIO2, pulse outputs through DIO1. *Remark: input pulse-width DIO1/2 over clock-cycle. Latches polarity outputs switches data outputs. rising edge, latches "POL" signal control polarity outputs. This also controls switch line registers that switches incoming data outputs *Remark: switch data outputs anytime even line data completely full. Polarity selector dot-inversion control. Available rising edge "POL" value latched rising edge "LD" control polarity even outputs. "POL=1" represents that even outputs positive polarity with voltage range from V1~V5, outputs negative polarity with voltage range from V10. other hand, gets level "POL", even outputs negative polarity outputs positive polarity. POL=1: Even outputs range from outputs range from POL=0: Even outputs range from outputs range from Power supply analog circuit Ground analog circuit Power supply digital circuit Ground digital circuit
Version
NT3965 Source Driver
Power on/off sequence:
This high-voltage driver, damaged large current flow when incorrect power sequence used. recommended sequence should digital power logic signals power (AVDD&AVSS) correction reference voltage(V1~V10). Reverse this sequence shut down, turn signals power simultaneously. Relationship between order input data output channels SHL="1", Start pulse from DIO1, shift right Output OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 Order First data Data D05~D00 D15~D10 D25~D20 D35~D30 D45~D40 D55~D50 SHL="0", Start pulse from DIO2, shift left Output OUT379 OUT380 OUT381 OUT382 OUT383 OUT384 Order First data Data D05~D00 D15~D10 D25~D20 D35~D30 D45~D40 D55~D50
OUT384 Last data D55~D50
OUT6 Last data D55~D50
Relationship between input data output voltage figure below shows relationship between input data output voltage with polarity. range V1~V5 positive polarity, negative polarity. Please refer following page relative resister value voltage calculation method.
Gamma correction diagram Vout AVDD
Positive polarity
Vcom
Negative polarity
AVSS Input Data
Remark: AVDD-0.1 >AVSS+0.1V
Version
NT3965 Source Driver
Gamma correction resistor ratio Name Resistor Name Resistor
Total impedance, Rn=R0 R62, equals 15.85K
Version
NT3965 Source Driver
Output Voltage Input Data Data Output Voltage Output Voltage
Positive polarity
7250/8050 6500/8050 5800/8050 5150/8050 4550/8050 4000/8050 3450/8050 2950/8050 2450/8050 2050/8050 1650/8050 1300/8050 950/8050 600/8050 300/8050 X2450/2750 2200/2750 1950/2750 1700/2750 1500/2750 1300/2750 1100/2750 950/2750 800/2750 650/2750 500/2750 400/2750 300/2750 200/2750 100/2750 1500/1600 1400/1600 1300/1600 1200/1600 1100/1600 1000/1600 900/1600 800/1600
Negative polarity
V10) 800/8050 V10) 1550/8050 V10) 2250/8050 V10) 2900/8050 V10) 3500/8050 V10) 4050/8050 V10) 4600/8050 V10) 5100/8050 V10) 5600/8050 V10) 6000/8050 V10) 6400/8050 V10) 6750/8050 V10) 7100/8050 V10) 7450/8050 V10) 7750/8050 300/2750 550/2750 800/2750 1050/2750 1250/2750 1450/2750 1650/2750 1800/2750 1950/2750 2100/2750 2250/2750 2350/2750 2450/2750 2550/2750 2650/2750 100/1600 200/1600 300/1600 400/1600 500/1600 600/1600 700/1600 800/1600
Version
NT3965 Source Driver
700/1600 600/1600 500/1600 400/1600 300/1600 200/1600 100/1600 900/1600 1000/1600 1100/1600 1200/1600 1300/1600 1400/1600 1500/1600
Output Voltage Input Data (continued) Output Voltage Output Voltage
Data
Positive polarity
3350/3450 3250/3450 3150/3450 3050/3450 2950/3450 2800/3450 2650/3450 2500/3450 2300/3450 2100/3450 1850/3450 1600/3450 1300/3450 800/3450
Negative polarity
100/3450 200/3450 300/3450 400/3450 500/3450 650/3450 800/3450 950/3450 1150/3450 1350/3450 1600/3450 1850/3450 2150/3450 2650/3450
Version
NT3965 Source Driver
Absolute Maximum Ratings*
Digital supply voltage, -0.5V Analog supply voltage, AVDD -0.5V +12V Supply voltage, 0.4AVDD ~AVDD+0.3 Supply voltage, -0.3 0.6AVDD Digital input voltage -0.5V Vcc+0.5V Output voltage, DIO1 DIO2 -0.5V Vcc+0.5V Output voltage,OUT1~OUT384 -0.5V AVDD+0.5V Storage temperature -55OCto 125OC Operating temperature 75OC
*Comments
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only. Functional operation this device these under other conditions above those indicated operational sections this specification implied exposure absolute maximum rating conditions extended periods affect device reliability.
Electrical Characteristics =2.7~3.6V AVDD=10V, AVSS=GND=0V, =-10OC~75OC)
(For digital circuit)
Parameter Supply Voltage Level Input Voltage High Level Input Voltage High Level Output Voltage Level Output Voltage Input Leakage Current Digital Stand-by Current Digital Operating Current Input Loading Input Loading Symbol Min. 0.7xVcc Vcc-0.4 Typ. Max. 0.3xVcc GND+0.4 Unit Conditions Digital power digital circuit digital circuit DIO1, DIO2, Ioh=1mA DIO1, DIO2, Iol=-1mA digital circuit operating stopped Fclk=45 MHz, FLD=50KHz DIO1/2, V1~V10 exclusive DIO1/2
(For analog circuit)
Parameter Supply Voltage Input level Input level Voltage Output Swing Deviation between Pins Output Voltage deviation Voltage Output Offset between Chips Dynamic Range Output Sinking Current Outputs Driving Current Outputs Impedance Gamma Correction Analog Stand-by Current Analog Operating Current Symbol Min. AVDD Vref 0.4AVDD Vref 0.8*Rn Typ. -180 Max. AVDD-0.1 0.6AVDD AVDD-0.1 -150 1.4*Rn Unit OUT1 OUT384 OUT1 OUT384; Vo=0.1V 1.0V AVDD=10V OUT1 OUT384; Vo=9.9V AVDD=10V Rn=15850 ohm, from V1~V5 V6~V10 load, Fclk=33MHz, FLD=50KHz AVDD=8.4V, OUT=4.2V load, Fclk=33MHz, FLD=50KHz AVDD=8.4V,V1=8V, V10=0.2V, Blackwhite line Conditions analog circuit power Gamma correction voltage Gamma correction voltage Vo=0.1V 0.8V AVDD-0.8 AVDD0.1V Vo=0.8V 1.2V AVDD-1.2 AVDD0.8V Vo=1.2V AVDD-1.2V
Version
NT3965 Source Driver
Electrical Characteristics =2.7~3.3V AVDD=6.5 10V, AVSS=GND=0V, -10~75O Parameter frequency frequency pulse width Data set-up time Data hold time Propagation delay DIO2/1 Time that last data Pulse width Time that DIO1/2 set-up time hold time Output stable time Output loading Symbol Fclk Fclk1 Tphl Twld Tlds Tpsu Tphd Min. Typ. Max. Unit Tcph Tcph Tcph Conditions Vcc=3.0V~3.6V Vcc=2.7V~3.0V D55, REVx DIO1/2 D55, REVx DIO1/2 CL=25pF Output
target voltage ,CL=75pF, R=5K ohm,AVDD=8.4V precision ,CL=75pF, R=5K ohm,AVDD=8.4V OUT1 OUT384
Version
NT3965 Source Driver
Timing Diagram
Tcph
DIO1/2 Input Data, REVx
Second data Tphl Last data Tphl
First data
DIO1/2 Output
Last
DIO1/2 Input
TpsuTpdh
Twld Tlds
Positive outputs
High-Z
Even outputs
High-Z
High-Z
Negative
Measure point
Output load condition Output
Vcom
Version
NT3965 Source Driver
Function operation
2CLK min.)
DIO1/2 Input
1CLK min.)
1CLK
Data, REVx
Last Data
First Data
Outputs
Vcom
~V10
Even Outputs
High-Z High-Z High-Z High-Z
~V10
Version
NT3965 Source Driver
Application notice: relationship between CLK, output waveform output voltage written panel, synchronized with falling edge.
Output Circuit Block Diagram
Output Vamp (in)
Vout
Output Circuit Timing Waveform
Vamp(in)
High-Z Vout
Remarks acknowledged timing display data latch completed timing input voltage (Vamp(in) gray-scale level voltage) output amplifier changes.
Version
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