Matrix 80-Channel Driver Provides 80-channel driver Internal seri
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NT3883
Matrix 80-Channel Driver
Provides 80-channel driver Internal serial parallel conversion circuits: 40-bit bi-direction shift register 80-bit latch 80-bit 4-level driver Logic circuit supply voltage range: 4.5V 5.5V
driving voltage range (VDD VEE): 3.5V Applicable duty cycle: 1/16 Interfaces with NT3881B/C/D controller bias voltage supplied externally Available 100-pin CHIP FORM
General Description
NT3883 matrix 80-channel driver fabricated power CMOS technology. This consists 40-bit bi-directional shift registers, 80-bit latch 80-bit 4-level driver. NT3883 converts serial data that received from controller, such NT3881B/C/D, parallel data outputs driving waveforms drive LCD. Expansion character-type liquid crystal display easily obtained according number structure characters.
Configuration
NT3883F
V2.1 November, 1999
NT3883
Configuration
NT3883H
NT3883
Block Diagram
80-Bit 4-Level Drivers
80-Bit Latch
First 40-Bit Shift Register
Second 40-Bit Shift Register
NT3883
Absolute Maximum Ratings*
Power Supply Voltage (VDD-GND) -0.3V 7.0V Power Supply Voltage (VDD-VEE) .VDD 13.5V 0.3V Input Voltage -0.3V 0.3V Operating Temperature -20GC Storage Temperature -55GC 125GC
*Comments
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage this device. These stress ratings only. Functional operation this device these other conditions above those indicated operational sections this specification implied exposure absolute maximum rating conditions extended periods affect device reliability.
Electrical Characteristics (VDD 5.0V, 25GC)
Parameter Input Voltage Symbol Output Voltage Voltage Descending Input Leakage Current Leakage Current Power Supply Current CL1, DL1, DL2*1 Terminal CL1, CL2, DL1, DR1, Min. Typ. Max. Unit -0.4mA +0.4mA 0.1mA 0.05mA each Conditions
open fCL1 1KHz fCL2 1MHz
Note determine Input Output DL1, DL2, configuration follows. Terminal High Output Input Input Output High Output Input Input Output
VDD, VEE; equivalent circuit (for reference) Input/output current excluded. When input intermediate level with CMOS, some excessive
1Kmax. Power Switch 10Kmax. Data Swtich
Current will flow through input circuit power supply. avoid this, input level must fixed high state.
NT3883
Characteristics (VDD 5.0V, 25GC) Parameter
Data Shift Frequency Clock Width Data Hold Time Data Set-up Time High Symbol fCL2 tCWH tCWL tSUD tSUC1 tSUC2 Terminal CL1, DL1~2, DR1~2 DL1~2, DR1~2 CL1, CL1, CL1, Min. Typ. Max. Unit
Clock Set-up Time(CL1CL2)
Clock Set-up Time(CL2 CL1) Clock Rise/Fall Time Data Delay Time
Timing Waveforms
DL1,
SUC1
DR1,
SUC2
SUC2
NT3883
Descriptions
1~30, 51~100 1~30, 51~100 Designation S1~S30, S80~S31 External Connection panel Power supply Power supply Controller Description Segment signal output pins Power logic circuits Clock latch serial data Shift left control 40-bit shift register (see NOTE*4) Shift left control 40-bit shift register (see NOTE*4) Controller Controller NT3882A/NT3 Controller NT3882A/NT3 Controller NT3882A/NT3 Controller NT3882A/NT3 Controller Power supply Clock shift serial data Data input/output 40-bit shift register (see NOTE*4) Data input/output 40-bit shift register (see NOTE*4) Data input/output 40-bit shift register (see NOTE*4) Data input/output 40-bit shift register (see NOTE*4) Alternate signal drivers Power drivers connection
49,50
VEE,
NOTE Relation SL1, SL2, DL1, DR1,
1(High) 0(Low)
1(High) 0(Low)
Shift Direction Left(S40 Right(S1 S40) Left(S80 S41) Right(S41 S80)
Output Input
Input Output
Output Input
Input Output
NT3883
Functional Description
NT3883 matrix segment driver LSI. operates with controller, such NT3881B/C/D, and/or another segment driver NT3882A/3883. NT3883 receives serial data from controller another NT3883, converts parallel data then supplies driving waveforms panel. This signal used latching shift register contents. When high, shift register contents transferred 80-bit 4level driver. When low, last display output data S80) held. Clock pulse inputs 40-bit shift registers. data shifted 80-bit latch falling edge CL2. clock signal must active when operating refresh shift registers' contents. Data input/output register. When connected open, data from controller into register through serially. connected VDD, becomes output register. Data input/output register. When connected GND, register output from DR1. connecting DL2, 40-bit shift registers cascaded 80-bit shift register. connected VDD, becomes input register, this case, data come from DL2. Latched Data 1(High) (Selected) 0(Low) (Non-selected) 1(High) 0(Low) 1(High) 0(Low)
Data input/output register. When connected GND, data from controller into register through serially. connected VDD, becomes output register. Data input/output register. When connected GND, register output from DR2. connecting next NT3882A/3883, cascade structure obtained drive wider panel. connected VDD, becomes input register, this case, data come from next NT3882A/3883. shift direction S40, i.e. shift register, selected SL1. detail function description listed Note*4 Page5. shift direction S80, i.e. shift register, selected SL2. detail function description listed Note*4 Page5. driver output pins. These bits represent data bits 80-bit latch VDD, selected driving voltage source according combination latched data level alternate signal (M). truth table listed follows:
Output Level
NT3883
Application Circuit (for reference only)
Chars Lines PANEL
NT3883
NT3883
NT3881D
other negative voltage
NT3883
Bonding Diagram
NT3883H
(0,0)
Connecting substrate keeping floating recommended. window area 1002m
1002m.
NT3883
Bonding Dimensions
Designation -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1194 -1184 -945 -807 -670 -520 -353 -204 1185 1195 1195 1677 1557 1437 1317 1197 1077 -122 -242 -362 -482 -602 -722 -842 -962 -1082 -1202 -1322 -1442 -1562 -1682 -1812 -1822 -1822 -1822 -1822 -1822 -1822 -1822 -1822 -1822 -1822 -1822 -1822 -1822 -1822 -1812 -1682 -1562 Designation 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1195 1185 -204 -324 -444 -564 -684 -805 -925 -1045 -1184 unit: -1442 -1311 -1202 -1082 -962 -842 -722 -602 -482 -362 -242 -122 1077 1197 1317 1437 1557 1677 1811 1821 1821 1821 1821 1821 1821 1821 1821 1821 1821 1821 1821 1821 1821 1821 1821 1821 1821 1811
NT3883
Ordering Information
Part NT3883H NT3883F Package CHIP FORM 100L
NT3883
Package Information 100L Outline Dimensions
unit: inches/mm
Detail Seating Plane
Detail
Symbol
Dimensions inches 0.130 Max. 0.004 Min. 0.112±0.005 0.014 +0.004 -0.002 0.006 +0.004 -0.002 0.551±0.005 0.787±0.005 0.031±0.006 0.693 NOM. 0.929 NOM. 0.740±0.012 0.976±0.012 0.047±0.008 0.095±0.008 0.006 Max.
Dimensions 3.30 Max. 0.10 Min. 2.85±0.13 0.35 +0.10 -0.05 0.15 +0.10 -0.05 14.00±0.13 20.00±0.13 0.80±0.15 17.60 NOM. 23.60 NOM. 18.80±0.31 24.79±0.31 1.19±0.20 2.41±0.20 0.15 Max.
Notes: Dimensions include resin fins. Dimensions Board surface mount pitch design reference only
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