µPD77210, 77213 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR

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µPD77210, 77213 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR

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INTEGRATED CIRCUIT
µPD77210, 77213
16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR
µPD77210 77213 16-bit fixed-point digital signal processors (DSP). Compared with existing members µPD77111 Family, µPD77210 Family consumes less power ideal battery-driven mobile terminal applications such PDAs cellular telephones. µP77210 Family also compatible with µPD77111 Family binary level. µPD77210 Family consists µPD77210 77213. Unless otherwise specified, µPD77210 Family refers entire family. there some differences function operation among family products, they described under their respective names. functions µPD77210 Family described detail following user's manuals. Refer these manuals when designing your system.
µPD77210 Family User's Manual Architecture: µPD77016 Family User's Manual Instructions:
preparation U13116E
FEATURES
Instruction cycle (operating clock):
µPD77210 µPD77213
Memory
6.25 MIN. (160 MAX.) 8.33 MIN. (120 MAX.)
-Internal instruction memory:
µPD77210 :RAM 31.5 Kwords bits µPD77213 :RAM 15.5 Kwords bits
Kwords bits -Data memory:
µPD77210 :RAM Kwords bits planes data memories)
External memory space Mwords bits (common data memories)
µPD77213 :RAM Kwords bits planes data memories)
Kwords bits planes data memories) External memory space Mwords bits (common data memories) Peripheral -Audio serial interface: channel -Time-division serial interface: channel -16-bit host interface: channel -16-bit general-purpose port -16-bit timer: channels -Peripheral-memory transfer function (Secure Digital) card interface :µPD77213 only
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Document U15203EJ3V0DS00 (3rd edition) Date Published November 2001 CP(K) Printed Japan
mark
shows major revised points.
2001
µPD77210, 77213
Supply voltage -DSP core supply voltage: -I/O supply voltage: 1.425 1.65 (MAX. operating speed MHz), 1.55 1.65 (MAX. operating speed MHz) µPD77210 only
ORDERING INFORMATION
Parts Number Package 161-pin plastic fine pitch 144-pin plastic LQFP (fine pitch) 161-pin plastic fine pitch 144-pin plastic LQFP (fine pitch)
µPD77210F1-DA2 µPD77210GJ-8EN µPD77213F1-xxx-DA2 µPD77213GJ-xxx-8EN
Remark indicates code suffix.
Data Sheet U15203EJ3V0DS
BLOCK DIAGRAM
Peripheral unit External memory External memory
Card
Note
Serial (AUDIO)
Peripheral-memory transfer
memory
memory
Serial (TDM)
Data Sheet U15203EJ3V0DS
Host
Peripheral
memory data addressing unit
memory data addressing unit Data memory unit (40) BSFT
controller
Interrupt controller
Main
Operation unit
Program control unit Port
µPD77210, 77213
Interrupt control Timer
Loop control stack
stack
Instruction memory
control RESET CSTOP HALTS STOPS
Clock control
Note PD77213 only
CLKOUT CLKIN
µPD77210, 77213
FUNCTIONAL BLOCK
+1.5 +3.3
Serial interface (time division serial)
TSORQ TSOEN TSCK TSIEN TSIAK
IVDD
EVDD RESET INTmn
Reset interrupt
CLKIN CLKOUT PLL0 PLL3 STOPS CSTOP HALTS
Clock
Serial interface (audio serial)
ASOEN/LRCLK ASIEN/MCLK ASCK/BCLK SDDAT0 SDCR SDCLK SDMON HA0, HD15
System control
card interface
Note
Port
MA19 MD15 MHOLDRQ MHOLDAK MBSTB MWAIT TIMOUT TDO, TICE TCK, TDI, TMS, TRST
External data memory interface
Host interface
Timer
debugging
Note µPD77213 only Caution Some port pins, host interface pins, serial interface pins, interrupt pins, card interface pins alternate function pins. Remark
Data Sheet U15203EJ3V0DS
FUNCTION LIST
Item Memory space (words bits) Int. instruction Int. instruction Data (X/Y memory) Data (X/Y memory) Ext. instruction memory Ext. data memory (X/Y memory) Data Sheet U15203EJ3V0DS Instruction cycle maximum operating speed) Multiple 15.3 MHz) Integer multiple (external pin) Peripheral Serial interface channels (speech CODEC) Host interface General-purpose port (I/O programmable) 8-bit bits bits 13.3 MHz) Integer multiple (mask option) Integer multiple (external pin) channel (audio CODEC) 16-bit bits (some alternative with host) channels (time-division, audio) 6.25 (160 MHz) each None each None None each None using I/F) 8.33 (120 MHz) None each each None each
µPD77110
35.5 None each
µPD77111
µPD77112
µPD77113A
µPD77114
µPD77115
11.5 None each
µPD77210
31.5
µPD77213
15.5
31.75 each
each
each
each
Integer multiple (external pin)
µPD77210, 77213
Timer
None
channel (16-bit resolution)
channels (16-bit resolution) card core: pins:
Others Supply voltage
core: pins:
card
Package
100-pin TQFP
80-pin TQFP 80-pin FBGA
100-pin TQFP
80-pin FBGA
100-pin TQFP
80-pin TQFP 80-pin FBGA
161-pin FBGA 144-pin LQFP
µPD77210, 77213
CONFIGURATIONS
161-pin plastic fine pitch
(Bottom View) (Top View)
Index mark
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Name
Name EVDD P10/HD10/INT22 P11/HD11/INT32 P12/HD12/INT03 P1/INT10 TICE MD12 MD15 P14/HD14/INT23 P15/HD15/INT33 P13/HD13/INT13 MD14 MD11 EVDD MD10 MD13 EVDD IVDD
Name EVDD MBSTB IVDD TIMOUT MWAIT EVDD TSIEN MA14/SDDAT0Note MHOLDRQ MHOLDAK EVDD ASCK/BCLK ASOEN/LRCLK TSOEN
Name TSORQ MA10 MA12 MA15/ReservedNote MA19/SDCLKNote MA18/SDCRNote EVDD ASIEN/MCLK TSCK TSIAK MA11 MA16/ReservedNote MA17/ReservedNote EVDD IVDD EVDD MA13/SDMONNote EVDD
P5/INT11 P2/INT20 EVDD IVDD IVDD PLL0 STOPS EVDD TRST P7/INT31 P6/INT21 P3/INT30 CLKOUT IVDD PLL3 PLL1 CSTOP I.C. EVDD P8/HD8/INT02 P9/HD9/INT12 P4/INT01 P0/INT00 CLKIN PLL2 HALTS RESET I.C.
Note MA13 MA19 pins µPD77213 alternate function pins.
Data Sheet U15203EJ3V0DS
µPD77210, 77213
144-pin plastic LQFP (fine pitch) (Top View)
MHOLDRQ MA19/SDCLKNote MA18/SDCRNote
MHOLDAK
MD15 MD14 MD13 MD12 MD11 MD10 EVDD
MBSTB MWAIT
TRST I.C. I.C. EVDD RESET STOPS CSTOP HALTS PLL0 PLL1 PLL2 PLL3 IVDD CLKIN IVDD IVDD CLKOUT EVDD P0/INT00 P1/INT10 P2/INT20 P3/INT30 P4/INT01 P5/INT11 P6/INT21 P7/INT31
EVDD
EVDD
TICE
IVDD
EVDD
EVDD Note MA17/Reserved Note MA16/Reserved Note MA15/Reserved Note MA14/SDDAT0 Note MA13/SDMON MA12 MA11 MA10 EVDD IVDD EVDD TSIAK TSORQ TSIEN TSCK TSOEN ASIEN/MCLK ASCK/BCLK
P15/HD15/INT33 EVDD
EVDD
EVDD
P9/HD9/INT12 P10/HD10/INT22
P11/HD11/INT32 P12/HD12/INT03
P13/HD13/INT13 P14/HD14/INT23
Note MA13 MA19 pins µPD77213 alternate function pins.
Data Sheet U15203EJ3V0DS
TIMOUT ASOEN/LRCLK EVDD
P8/HD8/INT02
IVDD
µPD77210, 77213
Name
EVDD
Name
Name ASCK/BCLK ASIEN/MCLK TSOEN TSCK TSIEN TSORQ TSIAK EVDD IVDD EVDD MA10 MA11 MA12 MA13/SDMON
Note
Name EVDD MA18/SDCRNote MA19/SDCLKNote MHOLDRQ MHOLDAK MWAIT MBSTB EVDD IVDD EVDD MD10 MD11 MD12 MD13 MD14 MD15 TICE EVDD
P8/HD8/INT02 P9/HD9/INT12 P10/HD10/INT22 P11/HD11/INT32 P12/HD12/INT03 P13/HD13/INT13 P14/HD14/INT23 P15/HD15/INT33 EVDD IVDD EVDD TIMOUT ASOEN/LRCLK EVDD
TRST I.C. I.C. EVDD RESET STOPS CSTOP HALTS PLL0 PLL1 PLL2 PLL3 IVDD CLKIN IVDD IVDD CLKOUT EVDD P0/INT00 P1/INT10 P2/INT20 P3/INT30 P4/INT01 P5/INT11 P6/INT21 P7/INT31
MA14/SDDAT0
Note
MA15/ReservedNote MA16/Reserved
Note
MA17/Reserved EVDD
Note
Note MA13 MA19 pins µPD77213 alternate function pins.
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Name
ASCK ASIEN ASOEN BCLK CLKIN CLKOUT CSTOP EVDD HALTS HD15 HA0, I.C. IVDD INTmn LRCLK MBSTB MCLK MHOLDAK MHOLDRQ :Audio Serial Clock Input/Output :Audio Serial Data Input :Audio Serial Input Enable :Audio Serial Data Output :Audio Serial Output Enable :Bit Clock Input/Output :Clock Input :Clock Output :Clear Stop Mode :Power Supply Pins :Ground :Halt Status Signal Output :Host Data :Host Chip Select :Host Data Access :Host Read :Host Read Enable :Host Write Enable :Host Write :Internal Connection :Power Supply Core :Interrupt (m,n=0 :Left Right Clock Input/Output :External Data Memory Strobe :Master Clock Input :External Data Memory Hold Acknowledge :External Data Memory Hold Request :External Data Memory Read Output :External Data Memory Write Output TSORQ TSOEN TSIEN TSIAK SDDAT0 SDMON STOPS TICE TIMOUT TRST TSCK PLL0-PLL3 Reserved RESET SDCLK SDCR MWAIT :External Data Memory Access Wait Input :Non-Connection :Port :PLL Multiple Rate :Reserved :Reset Card Clock Output Card Command Output/Response Input Card Data Input/Output Card Access Monitor :Stop Status Signal Output :Test Clock Input :Test Data Input :Test Data Output :Test In-Circuit Emulator :Timer Time Monitor Output :Test Mode Select :Test Reset :Time Division Multiplex Serial Clock Input :Time Division Multiplex Serial Data Input :Time Division Multiplex Serial Input Acknowledge :Time Division Multiplex Serial Input Enable :Time Division Multiplex Serial Data Output :Time Division Multiplex Serial Output Enable :Time Division Multiplex Serial Output Request
MA19 :External Data Memory Address
MD15 :External Data Memory
Data Sheet U15203EJ3V0DS
µPD77210, 77213
CONTENTS
FUNCTIONS.13
Description Functions Connection Unused Pins 1.2.1 Connection functional pins 1.2.2 Connection non-functional
FUNCTIONAL OUTLINE
Program Control Unit.23 2.1.1 control 2.1.2 Interrupt control 2.1.3 Loop control stack 2.1.4 stack 2.1.5 Clock control.23 2.1.6 Instruction memory Operation Unit 2.2.1 General-purpose registers 2.2.2 Multiply accumulator (MAC) 2.2.3 Arithmetic logic unit (ALU) 2.2.4 Barrel shifter (BSFT).24 Data Memory Unit.24 2.3.1 Data memory 2.3.2 Data addressing unit.25 Peripheral Unit.25 2.4.1 Serial interface (SIO) 2.4.2 Host interface (HIO).25 2.4.3 General-purpose port (PIO) 2.4.4 External memory interface (MIO).26 2.4.5 Timers (TIM1 TIM2) 2.4.6 Interrupt controller (INTC).26 2.4.7 controller (PMT) 2.4.8 card interface (SDCIF).26 2.4.9 Debug interface (IEIO).26
CLOCK GENERATOR.27 RESET FUNCTION
Hardware Reset
FUNCTION BOOT-UP ROM.28
Boot Reset 5.1.1 Memory boot.28 5.1.2 Host boot 5.1.3 Serial boot Reboot.29 5.2.1 Memory reboot
Data Sheet U15203EJ3V0DS
µPD77210, 77213
5.2.2 Host reboot 5.2.3 Serial reboot
STANDBY MODE.
Halt Mode Stop Mode
MEMORY MAP.
Instruction Memory 7.1.1 Instruction memory 7.1.2 Interrupt vector table. Data Memory 7.2.1 Data memory 7.2.2 Internal peripherals
GENERAL-PURPOSE PORT INTERRUPT
General-purpose Port Pins Interrupt
INSTRUCTION
Outline Instruction Instruction Operation.
ELECTRICAL SPECIFICATIONS. PACKAGE DRAWINGS. RECOMMENDED SOLDERING CONDITIONS.
Data Sheet U15203EJ3V0DS
µPD77210, 77213
FUNCTIONS
Because numbers differ depending package, column package used tables below. Description Functions Power supply pins
Name 144-pin LQFP IVDD 18,21,23,57, 88,123 EVDD 8,26,37,47,59, 71,86,98,108, 110,121,133, 161-pin FBGA A7,A8,B7,H1, J14, A6,A11,C1, C14,F1,F14, J1,K14,M1, M14,P6,P10, 1,9,19,22,24, 27,36,38,48, 58,60,72,73, 87,89,99,109, 122,124,134, A5,C13,D4,D5, D7,D8,D9,D10, E4,E11,G4, G11,H4,J11, K11,L3,L4,L6, L7,L9,L11 Ground These ground pins. Power supply core (+1.5 These pins supply power core. Power supply (+3.3 These pins supply power external interface pins. Function Alternate
Remark Please supply voltage IVDD EVDD pins simultaneously.
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Clock system control pins
Name 144-pin LQFP CLKIN 161-pin FBGA Input Clock input This inputs clock operate µPD77210 Family. CLKOUT Output Internal system clock output This outputs internal system clock that clock input from CLKIN which multiplied circuit. PLL0 PLL3 A9,B9,C7,B8 Input multiple setting input These pins clock multiple circuit. PLL3: PLL2: PLL1: PLL0 0000: 0011: 0110: 1001: 1100: 1111: HALTS Output HALT mode status output This asserted active halt mode stop mode. STOPS Output Stop mode status output This asserted active stop mode. CSTOP Input Stop mode clear signal input Stop mode cleared when this asserted active. 0001: 0100: 0111: 1010: 1101: 0010: 0101: 1000: 1011: 1110: Function Alternate
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Reset interrupt pins
Name 144-pin LQFP RESET 161-pin FBGA Input Internal system reset signal input This initializes µPD77210 Family. INT00 INT01 INT02 INT03 INT10 INT11 INT12 INT13 INT20 INT21 INT22 INT23 INT30 INT31 INT32 INT33 Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Maskable external interrupt input These pins input external interrupts. P8/HD8 P12/HD12 P9/HD9 P13/HD13 P10/HD10 P14/HD14 P11/HD11 P15/HD15 Function Alternate
Data Sheet U15203EJ3V0DS
µPD77210, 77213
External data memory interface
Name 144-pin LQFP MA19Note 107, 111, 161-pin FBGA M6,N6,N7,P8, M7,M8,P9,N8, L8,N9,M9,N10, M10,P11,L10, M11,N11,N12, M13,M12 MD15 119,120, 132, J12,H13,G13, H14,H12,H11, G14,F13,G12, E13,F11,E14, D13,F12,E12, Output (3S) Write output This outputs write strobe signal external data memory. Output (3S) Read output This outputs read strobe signal external data memory. MHOLDAK Output Hold acknowledge signal This goes when external device granted external data memory (3S) 16-bit data These pins input/output data when external data memory accessed. Output (3S) Address external data memory These pins output address when external data memory accessed. Function Alternate SDCLK, SDCR, SDDAT0, SDMON
µPD77210 Family.
MHOLDRQ Input Hold request signal external device inputs level this when uses external data memory
µPD77210 Family.
MWAIT Input Wait signal input This inserts wait cycles when µPD77210 Family accesses external data memory. Inserts wait cycles. Does insert wait cycles. MBSTB Output strobe signal This goes while µPD77210 Family uses external data memory bus.
Note MA13 MA19 pins µPD77213 alternate function pins. Remark Those pins marked "3S" above table enter high-impedance state under following conditions: MA19, MRD, MWR: When released (MHOLDAK level) MD15: When external data memory accessed when released (MHOLDAK level)
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Timer
Name 144-pin LQFP TIMOUT 161-pin FBGA Output Time monitor This asserted active when timer times out. Function Alternate
Serial interface
Name 144-pin LQFP ASCK/ BCLK 161-pin FBGA Audio serial clock input/output ASCK:Audio serial clock input BCLK:Serial clock Output (3S) ASOEN/ LRCLK Input Audio serial data input Audio serial output enable/left right clock input output ASOEN:Audio serial output enable input LRCLK:Left right clock ASIEN/ MCLK Input Audio serial input enable/master clock input output ASIEN:Audio serial input enable input MCLK:Master clock input master mode) TSCK Input Output (3S) TSORQ TSOEN TSIEN TSIAK Input Output Input Input Output Time-division serial data input Time-division serial output request Time-division serial output enable Time-division serial input enable Time-division serial input acknowledge Clock input time division serial Time-division serial data output Audio serial data output Function Alternate
Remark Those pins marked "3S" above table enter high-impedance state when data transmission completed when hardware reset (RESET) signal input.
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Host interface
Name 144-pin LQFP 161-pin FBGA Input Host address This specifies register that accessed host interface pins (HD7 HD0, HD15 HD0). host interface status register (HST) accessed. host transmit data register (HDT (out)) accessed read (HRD host receive data register (HDT (in)) accessed write (HWR Input Host address This specifies register that accessed 8-bit mode. This invalid 16-bit mode. Bits HST, (in), (out) accessed. Bits HST, (in), (out) accessed. F4,F2,F3,G1, G3,G2,H3,H2 Input Input Input Output Output (3S) Chip select input Host read input Host write input Host read enable output Host write enable output 8-bit host data These pins constitute host data 8-bit host mode. Access 16-bit data input/output controlled pin, data accessed times such that divided into blocks 8bit data. 16-bit mode, lower bits data input/output. HD15 C2,C3,D1,D2, D3,E3,E1,E2 (3S) Host data These pins constitute host data 16-bit host mode. They input/output 16-bit data with HD7. P15/ INT02, INT12, INT22, INT32, INT03, INT13, INT23, INT33 Function Alternate
Remark Those pins marked "3S" above table enter high-impedance state while host interface being accessed.
Data Sheet U15203EJ3V0DS
µPD77210, 77213
port
Name 144-pin LQFP 161-pin FBGA General-purpose port Function Alternate INT00 INT10 INT20 INT30 INT01 INT11 INT21 INT31 INT02/HD8 INT12/HD9 INT22/HD10 INT32/HD11 INT03/HD12 INT13/HD13 INT23/HD14 INT33/HD15
Debugging interface
Name 144-pin LQFP 161-pin FBGA Output (3S) TICE TRST Output Input Input Input Input debugging This interface pins used when debugger used. Function Alternate
Remark Those pins marked "3S" above table enter high-impedance state while debugging interface being accessed.
Data Sheet U15203EJ3V0DS
µPD77210, 77213
card interface (µPD77213 only)
Name 144-pin LQFP SDCLK 161-pin FBGA Output card clock output Leave this open. SDCR (3S) cord command/response Input: Response Output: Command Leave pull-up. SDDAT0 (3S) card data input/output Input: Read data Output: Write data Leave pull-up. SDMON Output card interface access monitor This outputs high level when card interface being accessed. card interface being accessed card interface being accessed Reserved M11, N11, Reserved future function expansion. This becomes high impedance when card interface being used. MA15 MA17 MA13 MA14 MA18 Function Alternate MA19
Remark Those pins marked "3S" above table enter high-impedance state when card interface being accessed. Others
Name 144-pin LQFP I.C. 161-pin FBGA B11, Internally connected. Leave these pins open. A1,A2,A13, A14,B1,B2, B13,B14,E5, N1,N2,N13, N14,P1,P2, P13,P14 connection. Leave these pins open. Function Alternate
Caution signal input these pins these pins read, correct operation µPD77210 Family guaranteed.
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Connection Unused Pins 1.2.1 Connection functional pins Connect unused pins shown table below.
Name STOPS, HALTS CSTOP CLKOUT HA0, HCS, HRD, HRE, TIMOUT ASCK, TSCK ASI, ASIEN, TSIEN ASOEN, TSOEN, LRCLK ASO, TSORQ TSIAK MA19 MD15 MRD, MHOLDRQ MBSTB, MHOLDAK MWAIT TDO, TICE TMS, TRST
Note Note
Output Input Output Input Input Output Output Input Input Input Input Leave open.
Recommended Connection
Connect pull-down resistor. Leave open. Connect EVDD pull-up resistor pull-down resistor. Connect EVDD pull-up resistor pull-down resistor. Connect EVDD pull-up resistor pull-down resistor. Connect EVDD pull-up resistor. Leave open. Leave open. Connect EVDD pull-up resistor pull-down resistor.
Connect pull-down resistor.
Output Output Output Output Output Input Output Input Input Output Input Input
Leave open.
Leave open. Connect EVDD pull-up resistor pull-down resistor. Leave open. Connect EVDD pull-up resistor. Leave open. Connect EVDD pull-up resistor. Connect pull-down resistor. Leave open. Leave open (this internally pulled up). Leave open (this internally pulled down).
Notes These pins left opened HCS, HRD,and fixed high level. However, connect these pins recommended HALT STOP modes when power consumption must lowered. These pins leave opened external data memory accessed program. However, connect these pins recommended HALT STOP modes when power consumption must lowered. Caution Unused alternate-function pins should handled accordance with processing specified function initial setting.
Data Sheet U15203EJ3V0DS
µPD77210, 77213
1.2.2 Connection non-functional
name I.C. Leave open. Leave open. Recommended Connection
Data Sheet U15203EJ3V0DS
µPD77210, 77213
FUNCTIONAL OUTLINE
Program Control Unit This unit controls execution µPD77210 Family executing instructions controlling branching, loop, interrupts, clock, standby mode. 2.1.1 control three-stage pipeline architecture employed that instructions, except branch instructions some others, executed with system clock. 2.1.2 Interrupt control interrupt control circuit services interrupt requests input interrupt controller external (INTmn) internal peripherals (such serial interface, host interface, timer, controller). interrupt each interrupt source individually enabled disabled. addition, multiple interrupts also supported. 2.1.3 Loop control stack loop function without hardware overhead realized. 4-level loop stack provided support multiple loops. 2.1.4 stack 15-level stack that stacks program counter supports multiple interrupts/subroutine calls. 2.1.5 Clock control divider internally provided clock generator that externally input clock multiplied divided supplied operating clock µPD77210 Family. multiple using external pins (PLL0 PLL3) within range division ratio using register range clock control register (CLKC) controls power (ON/OFF) PLL, selects clock source, controls output divider, controls output CLKOUT pin. types standby modes available that power consumption reduced when µPD77210 Family standing mode: Current consumption falls several upon execution HALT instruction. This mode released interrupt hardware reset. mode: Current consumption falls hundreds
Note
upon execution STOP instruction.
This mode released hardware reset inputting signal CSTOP pin. Note When stopped
Data Sheet U15203EJ3V0DS
µPD77210, 77213
2.1.6 Instruction memory instruction RAM, words allocated interrupt vectors. µPD77210 provided with instruction 31.5 Kwords. µPD77213 provided with instruction 15.5 Kwords instruction Kwords. boot-up that boots instruction also provided, instruction initialized rewritten means memory boot (booting from internal external data space), host boot (booting host interface), serial boot (booting serial interface). Operation Unit This unit performs multiplication, addition, logic, shift operations, consists 40-bit multiply accumulator, 40-bit data ALU, 40-bit barrel shifter, eight 40-bit general-purpose registers. 2.2.1 General-purpose registers These eight 40-bit registers input/output operands load/store data to/from data memory. Each register consists three parts: (bits (bits 16), (bits 32). Depending type operation, RnL, RnH, used either register combination. 2.2.2 Multiply accumulator (MAC) multiply accumulator performs multiplication 16-bit data items addition subtraction between result multiplication 40-bit data item, then outputs 40-bit data. shifter (MSFT: shifter) provided preceding stage MAC, that 40-bit data that added subtracted from multiplication result arithmetically shifted bits right before addition subtraction. 2.2.3 Arithmetic logic unit (ALU) accepts 40-bit data items input, performs arithmetic logical operation, then outputs 40-bit data. 2.2.4 Barrel shifter (BSFT) BFST accepts 40-bit data items input, shifts data left right arbitrary number bits, then outputs 40-bit data. data shifted right arithmetically, which case sign data extended, logically which case inserted starting from MSB. Data Memory Unit data memory unit consists planes data memory spaces pairs data addressing units. 2.3.1 Data memory data memory planes data memory data memory) provided. data memory space includes 64-word peripheral area. µPD77210 data consisting Kwords planes. µPD77213 data consisting Kwords planes, data consisting Kwords planes. addition, They also have external data memory interface that used connect external Mword data memory device.
Data Sheet U15203EJ3V0DS
µPD77210, 77213
2.3.2 Data addressing unit independent data addressing unit provided each data memory spaces. Each data addressing unit four data pointers (DPn), four index registers (DNn), module register (DMX DMY), address ALU. Peripheral Unit peripheral unit serial interfaces, host interface, general-purpose ports, timers, external memory interface, card interface (µPD77213 only). these internal peripherals mapped data memory spaces accessed memory-mapped I/Os program. 2.4.1 Serial interface (SIO) serial interface channels, audio serial interface (ASIO) time-division serial interface (TDMSIO), provided. audio serial interface used either modes: audio mode standard mode. standard mode compatible with existing µPD77111 Family. audio mode compatible with µPD77115. features audio mode follows: Mode: Master mode slave mode Master mode: Supports master clock input (MCLK), clock output (BCLK), clock output (LRCLK), Slave mode: clock input (BCLK) clock input (LRCLK) Frame format: 64-bit audio formats (LRCLK format) Handshake: Handshaking with external devices dedicated frame signal (LRCLK) with internal circuitry polling, wait, interrupt standard mode following features: clock: length: Supplied from external source each channel. clock shared input output each channel. bits, with first selected each channel. Handshaking with external device using dedicated status signal with internal circuitry polling, wait, interrupt. time-division serial interface divides serial input/output signal into time slots allows several devices share serial bus. Because frame signals considered. time slot extended from 128. 2.4.2 Host interface (HIO) This parallel port that inputs/outputs data from/to external host controller. used either 8-bit parallel mode 16-bit parallel mode. µPD77210 Family, 16-bit registers mapped memory input data, output data, status. Handshaking with external device performed using dedicated status signal, internal circuitry handshaking done means polling, wait, interrupts. 8-bit parallel mode compatible with existing members µPD77111 Family. 16-bit parallel mode, some port pins used host interface pins.
Data Sheet U15203EJ3V0DS
µPD77210, 77213
2.4.3 General-purpose port (PIO) This 16-bit port that either input output mode 1-bit units. external pins alternate between interrupt pins host interface pins. setting mode bits port host interface mode, host interface 16-bit parallel mode. 2.4.4 External memory interface (MIO) This interface accesses external Mwords data memory area either modes: direct access access modes. access mode, access made memory-mapped register. direct access mode, data paging register (DPR) 0x3F page area accessed access window. address external memory consists bits with 8-bit value index register added bits access mode, address automatically updated when memory-mapped register accessed. address updated increment addressing mode which address simply incremented, twodimensional addressing mode which offset added each line length. number wait cycles inserted when external memory accessed specified register (MWAIT), within range addition, wait cycles also inserted using MWAIT pin. 2.4.5 Timers (TIM1 TIM2) µPD77210 Family timer channels. These timers used interval timers, event counters, watchdog timers, free-run timers. clock input timers selected from system clock, serial clock (ASCK TSCK), external interrupt (INT00, INT10, INT20, INT30), output each timer. count value bits clock input prescaler divided 128. 2.4.6 Interrupt controller (INTC) interrupt controller functions selecting masking interrupt signals. controls interrupt signal input core. 2.4.7 controller (PMT) controller realizes data transfer between peripherals memory (peripheral-memory transfer) background. mitigates software overhead generated interrupt processing data input/output SIO, HIO, MIO, SDCIF (µPD77213 only). Data Kwords addresses 0x0000 0x37FF internal data transferred means DMA. 2.4.8 card interface (SDCIF) µPD77213 supports Card interface. This interface access card. supports transfer input data internal data RAM. card accessed using dedicated routine system ROM. 2.4.9 Debug interface (IEIO) µPD77210 Family following functions that conform JTAG (Joint Test Action Group) interface debug interface. device conforming JTAG access port dedicated testing tested independently internal logic. µPD77210 Family registers control circuit in-circuit emulation, addition instruction registers, bypass registers, boundary scan registers that required JTAG Recommendation.
Data Sheet U15203EJ3V0DS
µPD77210, 77213
CLOCK GENERATOR
clock generator generates internal system clock based external clock input from CLKIN supplies clock µPD77210 Family. configuration clock generator illustrated below.
Standby mode Halt Stop
CLKIN
controller
(m:10
Output divider
Internal system clock
(n:1
CLKOUT
CLKC register
PLL0 PLL3 Peripheral
stopped immediately after reset. clock input from CLKIN directly supplied
µPD77210 Family internal circuitry bootup commences. started boot routine booting
carried output clock (except case non-boot external memory boot). case nonboot external memory boot, when booting finished, after started setting CLKC register from user program, clock source must switched PLL, which case must locked. Note that required between when started when locked. multiplication rate specified external pins PLL0 PLL3. also lock range modes: MHz. mode used specified during booting. CLKC register used control turning on/off PLL, select clock source (external clock/multiplied clock/divided non-divided output), control resetting output divider, division ratio, enable/disable CLKOUT output. When output divider selected, high-level width clock output CLKOUT equivalent cycle normal operation (which means that clock does have duty factor 50%). halt mode, output divider circuit automatically selected clock source. When divider circuit selected, clock changed even halt mode set. stop mode, system clock supplied internal circuitry masked. Because stopped automatically, recover from stop mode without lock time. necessary CLKC register program stop PLL.
Data Sheet U15203EJ3V0DS
µPD77210, 77213
RESET FUNCTION
device initialized when level specified width input RESET pin. Hardware Reset internal circuitry µPD77210 Family initialized when RESET asserted active (low level) specific period. When RESET then deasserted inactive (high level), booting instruction performed accordance with status port pins (P0, P3), then processing executed starting from instruction address 0x200 (reset entry) instruction memory.
FUNCTION BOOT-UP
instruction booted using internal boot-up when power applied when contents instruction memory rewritten program. Boot Reset Immediately after release hardware reset, boot program first reads general-purpose port pins boot mode (memory boot/host boot/serial boot) determined patterns these port pins. Once booting processing been completed, processing executed starting from instruction address 0x200 (reset entry) instruction memory.
Non-bootNote memory initial boot memory initial boot memory initial boot External memory initial boot Host boot Serial boot Boot Mode
Note This setting used when µPD77210 Family must reset upon restoration from standby mode after reset boot been executed once.
lock range
5.1.1 Memory boot instruction code stored data memory transferred instruction RAM. Depending data memory from which instruction code transferred, memory boot (booting from data memory), memory boot (booting from data memory), memory boot (booting from data memories), external memory boot (booting from external data memory space) performed.
Data Sheet U15203EJ3V0DS
µPD77210, 77213
5.1.2 Host boot boot parameter instruction code obtained host interface transferred instruction RAM. 5.1.3 Serial boot boot parameter instruction code obtained serial interface transferred instruction RAM. Reboot contents instruction rewritten calling following reboot entries program.
Reboot Mode Entry Address Number Instruction Steps Transfer Source Start Address Parameter Transfer Destination Transfer Destination Start Address Memory reboot memory memory memories External memory Host reboot Serial reboot DP3, Transfer Destination Page (DPR)
5.2.1 Memory reboot instruction code stored into data memory transferred instruction RAM. Depending data memory from which instruction code transferred, memory reboot (rebooting from data memory), memory reboot (rebooting from data memory), memory reboot (rebooting from data memories), external memory reboot (rebooting from external data memory space) performed. Perform memory rebooting setting following parameters calling entry address corresponding rebooting method. R7L: Number instruction steps rebooted DP3: First address memory storing instruction code reboot from external memories) DP7: First address memory storing instruction code reboot from memories) R6L: Transfer source data page register (DPR) (Specify 0x00 case internal data area.) Index register (for external memory rebooting) DP2: Transfer destination address instruction rebooted reboot from external memories) DP6: Transfer destination address instruction rebooted reboot from memories) R5L: Transfer destination page register (DPR) (Specify 0x80 case internal instruction area.)
Data Sheet U15203EJ3V0DS
µPD77210, 77213
5.2.2 Host reboot instruction code obtained host interface transferred instruction RAM. entry address 0x5. Host rebooting executed setting following parameters then calling this address. R7L: Number instruction steps rebooted R6L: Host status register (HST) DP2: Transfer destination address instruction rebooted (offset 0x8000 case internal instruction area) R5L: Transfer destination data page register (DPR) (Specify 0x80 internal instruction area.) 5.2.3 Serial reboot instruction code obtained serial interface (TDMSIO) then transferred instruction RAM. entry address 0x6. Host rebooting executed setting following parameters then calling this address. R7L: Number instruction steps rebooted R6L: Serial status register (SST) (Specify 0x0EC0.) DP2: Transfer destination address instruction rebooted (offset 0x8000 case internal instruction area) R5L: Transfer destination data page register (DPR) (Specify 0x80 internal instruction area.)
Data Sheet U15203EJ3V0DS
µPD77210, 77213
STANDBY MODE
µPD77210 Family either standby modes. Each mode executing corresponding instruction. power consumption reduced these modes. Halt Mode halt mode executing HALT instruction. this mode, functions except clock circuit stopped and, therefore, current consumption reduced. device released from this mode interrupt hardware reset. release device from halt mode issuing interrupt, contents internal registers memories retained. takes system clocks release µPD77210 Family from halt mode released interrupt). When releasing device from halt mode using hardware reset, external clock must selected clock source advance that contents memories retain. halt mode, clock circuit µPD77210 Family supplies clock divided ratio specified CLKC register internal system clock. same applies clock output CLKOUT pin. Stop Mode Stop mode when STOP instruction executed. this mode, supply clock internal system stopped. stopped before stop mode set, functions, including clock circuit PLL, stopped. result, only leakage current flows and, therefore, current consumption minimized. this case, external clock must selected clock source advance. device released from stop mode hardware reset CSTOP pin. release device from stop mode using CSTOP pin, contents internal registers memories retained. When releasing device from stop mode using hardware reset, external clock must selected clock source advance that contents memories retain.
Data Sheet U15203EJ3V0DS
µPD77210, 77213
MEMORY
µPD77210 Family employs Harvard architecture that separates instruction memory space from data memory space. Instruction Memory 7.1.1 Instruction memory instruction memory space consists Kwords bits. area addresses 0x8000 0xFFFF paging area that supports memory space Kwords more specifying page using instruction paging register (IPR). instruction µPD77213 exists paging area accessed IPR=0x0 0x1. paging area µPD77210 reserved future expansion.
PD77210
0xFFFF 0xFFFF
PD77213
Paging area
Paging area Kwords)
Paging area Kwords)
Instruction Kwords)
Note
0x8000 0x7FFF
0x8000 0x7FFF
(IPR=0x0) (IPR=0x1) System area
Instruction (31.5 Kwords)
0x4000 0x3FFF Instruction (15.5 Kwords)
0x0200 0x01FF 0x0000
Boot-up (512 words)
0x0200 0x01FF 0x0000
Boot-up (512 words)
Note higher words instruction (0xFFF8 0xFFFF) constitute system area. Caution Programs data cannot allocated system area, neither accessed. these addresses accessed, correct operation accessed, correct operation device guaranteed. device guaranteed. paging area which page exists cannot accessed. this kind paging area
Data Sheet U15203EJ3V0DS
µPD77210, 77213
7.1.2 Interrupt vector table Addresses 0x200 0x23F instruction memory assigned entry points (vectors) interrupts. Four instruction addresses assigned each interrupt source. Four interrupt sources assigned each interrupt vector. There vectors. identifying source vector, µPD77210 interrupt sources µPD77213 interrupt sources. Each these interrupt sources masked using interrupt control register (ICR0 ICR11).
Vector 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 Reset Reserved Reserved Reserved INT00 INT10 INT20 INT30 input Reserved Reserved Reserved Reserved INT01 INT11 INT21 INT31 TSIEN Interrupt Source Reserved Reserved Reserved Reserved INT02 INT12 INT22 INT32 (TSI input) 0x224 output TSOEN (TSO output) 0x228 input ASIEN (ASI input) 0x22C output ASOEN (ASO output) 0x230 input input) 0x234 output output) 0x238 TIMER TIMER input) 0x23C TIMER TIMER output) Reserved Reserved Reserved Reserved SDDAT inputNote (busy release) SDDAT outputNote SDCR output Note Reserved Reserved Reserved Reserved INT03 INT13 INT23 INT33 SDCR input Note
Note
These interrupt sources µPD77213 only. When using µPD77210, they reserved. Reset interrupt used entry vector. recommended that vector interrupt source that used branch abnormality processing routine.
Cautions
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Data Memory 7.2.1 Data memory data memory space consists planes: memory spaces, each which consists Kwords bits. area 0x8000 0xFFFF paging area that supports memory space Kwords more specifying page using data paging register (DPR). same manner regardless whether memory space accessed. Page 0x3F window external data memory. Data µPD77213 exists paging area accessed DPR=0x0. Page 0x80 shared 0x0000 0x7FFF internal instruction RAM. lower bits 32-bit instruction constitute data memory, while higher bits data memory. Because some pins µPD77213 shared with card interface, area that accessed when card interface being used restricted. address pins MA13 MA19 shared with card interface. When card interface being used, therefore, only 13-bit address area MA12 Kwords) accessed.
PD77210
0xFFFF
Paging area 0xFFFF
PD77213
Paging area
Paging area Kwords)
Note
External data memory window Kwords)
Paging area Kwords)
Data Kwords)
Note
External data memory window Kwords)
0x8000 0x7FFF
(DPR=0x3F)
0x8000 0x7FFF System
(DPR=0x0)
(DPR=0x3F)
Data Kwords)
0x4000 0x3FFF 0x3800 0x37FF
0x5000 0x4FFF 0x4000 0x3FFF 0x3800 0x37FF
Data Kwords) Peripheral Kwords)
Peripheral Kwords)
Data Kwords)
0x0000 0x0000
Data Kwords)
Notes paging register value other than 0x3F (external data memory window) 0x80 (internal instruction area), programs data cannot stored addresses paging area, these addresses accessed. higher words data (0xFFF8 0xFFFF) constitute system area. Caution Programs data cannot allocated system area, neither accessed. these addresses accessed, correct operation accessed, correct operation device guaranteed. device guaranteed. paging area which page exists cannot accessed. this kind paging area
Data Sheet U15203EJ3V0DS
µPD77210, 77213
7.2.2 Internal peripherals internal peripherals mapped internal data memory space. Cautions register names shown above table reserved words either assembler these names assembler therefore, user must define them. same register accessed regardless whether memory space memory space accessed, provided that address same. Different registers cannot accessed simultaneously from memory spaces. Memory-Mapped Peripherals (1/3)
Memory Address Register Name Function Peripheral Name 0x3800 0x3801 0x3802 0x3803 0x3804 0x3805 0x3806 0x3807 0x3808 0x380F 0x3810 0x3811 0x3812 0x3813 0x381F 0x3820 0x3821 0x3822 0x383F 0x3840 0x3841 0x3842 0x3843 0x3844 0x3845 0x3846 0x3847 0x3848 0x3849 0x384A 0x384B 0x384C 0x384D 0x384F 0x3850 0x3851 0x3852 0x3853 TSDT/SDT1 SST1 TSST TFMT TTXL TTXH TRXL TRXH Reserved area ASDT/SDT2 SST2 ASST Reserved area Reserved area MSHW MCST MWAIT MIDX MADRLI MADRHI MOFSI MLENI MADRLO MADRHO MOFSO MLENO Reserved area PMSA0 PMS0 PMC0 PMP0 serial data register/Serial data register Serial status register serial status register frame format register transfer slot register (low) transfer slot register (high) receive slot register (low) receive slot register (high) Caution access this area. Audio serial data register/Serial data register Serial status register Audio serial status register Caution access this area. Host interface data register Host interface status register Caution access this area. Memory data register Memory setup/hold width setting register Memory control/status register Memory wait register Direct access index register Memory input start address register (low) Memory input start address register (high) Memory input line offset register Memory input line length register Memory output start address register (low) Memory output start address register (high) Memory output line offset register Memory output line length register Caution access this area. start address register size register control register address pointer ASIO(SIO2) TSIO(SIO1)
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Memory-Mapped Peripherals (2/3)
Memory Address Register Name Function Peripheral Name 0x3854 0x3855 0x3856 0x3857 0x3858 0x3859 0x385A 0x385B 0x385C 0x385D 0x385E 0x385F 0x3860 0x3861 0x3862 0x3863 0x3864 0x3865 0x3866 0x3867 0x3868 0x3869 0x386A 0x386B 0x386C 0x386D 0x386E 0x386F 0x3870 0x3871 0x3872 0x3873 0x3874 0x3875 0x3876 0x3877 0x3878, 0x3879 0x387A, 0x387B PMSA1 PMS1 PMC1 PMP1 PMSA2 PMS2 PMC2 PMP2 PMSA3 PMS3 PMC3 PMP3 PMSA4 PMS4 PMC4 PMP4 PMSA5 PMS5 PMC5 PMP5 PMSA6 PMS6 PMC6 PMP6 PMSA7 PMS7 PMC7 PMP7 PDT0 PCD0 PDT1 PCD1 PDT2 PCD2 PDT3 PCD3 Reserved area POWC start address register size register control register address pointer start address register size register control register address pointer start address register size register control register address pointer start address register size register control register address pointer start address register size register control register address pointer start address register size register control register address pointer start address register size register control register address pointer Port data register Port command register Port data register Port command register Port data register Port command register Port data register Port command register Caution access this area. Power control register Peripheral STOP mode
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Memory-Mapped Peripherals (3/3)
Memory Address Register Name Function Peripheral Name 0x387C 0x387F 0x3880 0x3881 0x3882 0x3883 0x3884 0x3885 0x3886 0x3887 0x3888 0x3889 0x388A 0x388B 0x388C 0x388F 0x3890 0x3891 0x3892 0x3893 0x3894 0x3895 0x3896 0x3897 0x389F 0x38A0 0x38A1 0x38A2 0x38A3 0x38A4 0x38A5 0x38A6 0x38A7 0x38A8 0x38A9 0x38AF 0x38B0 0x38B1 0x38BF 0x38C0 0x38C1 0x38C2 0x38CF 0x38D0 0x38D1-0x3FFF Reserved area ICR0 ICR1 ICR2 ICR3 ICR4 ICR5 ICR6 ICR7 ICR8 ICR9 ICR10 ICR11 Reserved area TIR0 TCR0 TCSR0 Reserved area TIR1 TCR1 TCSR1 Reserved area CEFR CPR0 CAR0 CLIR0 CUIR0 CPR1 CAR1 CLIR1 CUIR1 Reserved area CLKC Reserved area Reserved area ADCR
Note
Caution access this area. Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Caution access this area. Timer initial register Timer count register Timer control/status register Caution access this area. Timer initial register Timer count register Timer control/status register Caution access this area. Collect enable flag register Collect page register Collect address register Collect instruction data register (high) Collect instruction data register (low) Collect page register Collect address register Collect instruction data register (high) Collection instruction data register (low) Caution access this area. Clock control register Caution access this area. Instruction paging register Data paging register Caution access this area. Additional control register Caution access this area.
INTC
TIM0
TIM1
CLKC Page register
Additional
Reserved area
Note µPD77213 only. access 0x38D0 µPD77210.
Data Sheet U15203EJ3V0DS
µPD77210, 77213
GENERAL-PURPOSE PORT INTERRUPT
General-purpose Port Pins general-purpose port pins alternate with interrupt host interface pins. configuration general-purpose port illustrated below.
Port
Note
Port
Host Interrupt controller
Note alternate with host interfave pins.
Interrupt general-purpose port functions interrupt signal input port always input interrupt controller. interrupt controller recognizes interrupt detecting falling edge. output general-purpose port host interface also used interrupt input. Pins HRD, HWR, ASOEN, ASIEN, TSOEN, TSIEN connected interrupt controller used interrupt pins.
Data Sheet U15203EJ3V0DS
µPD77210, 77213
INSTRUCTION
Outline Instruction instruction consists bits. instructions, with some exceptions such branch instructions, executed with system clock. instruction cycle µPD77210 6.25 instruction cycle
µPD77213 8.33 following nine types instructions available.
Trinomial instructions These instructions specify operation MAC. operands, three general-purpose registers specified. Binomial instructions These instructions specify operation MAC, ALU, BSFT. operands, general-purpose registers specified. Some these instructions allow immediate value specified instead general-purpose register. Monomial instructions These instructions specify operation ALU. operand, general-purpose register specified. Load/store instructions These instructions specify 16-bit data transfer between memory general-purpose register. operand, general-purpose register specified. Register-to-register transfer instructions These instructions specify transfer between general-purpose register another register. Immediate value setting instructions These instructions immediate value general-purpose registers each register address operation unit. Branch instructions These instructions specify branching program. Hardware loop instructions These instructions specify repetitive execution instruction. Control instructions These instructions specify program control.
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Instruction Operation Describe operation operation field each instruction accordance with description method operation representation format instruction. more elements available, select them. Correspondence between representation format selectable register representation format selectable register follows:
Representation Format ro', dpx_mod dpy_mod dp_imm *xxx R0EH R7EH DMX, DPn, DPn++, DPn-, DPn##, DPn%%, !DPn## DPn, DPn++, DPn-, DPn##, DPn%%, !DPn## DPn## Contents memory address (Example) contents register 1000, *DP0 indicates contents memory address 1000. Selectable Register
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Modifying data pointer data pointer modified only after memory access. result modification becomes valid starting from instruction that executed immediately after. data pointer cannot modified without memory access.
Example DPn++ DPn- DPn## Operation Nothing executed (value changed). (Value corresponding added.) Example: DPn%% ((DPL DNn) (DMX ((DPL DNn) (DMY !DPn## Reverses bits then accesses DPn. After memory access, DPn##
Instructions that described simultaneously Those instructions that described simultaneously indicated Status overflow flag (OV) status overflow flag indicated following symbols: change
Caution overflow does occur after operation, overflow flag reset status remains same before operation.
overflow occurs.
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Instruction
Flag Control Instruction Name Mnemonic Operation Instructions That Described Simultaneously
Immediate Value
Instruction Group
Load/Store
Monomial
Trinomial
Binomial
Transfer
Branch
Loop
Multiply Multiply Trinomial operation Signed/unsigned multiply Unsigned/unsigned multiply
rh*rh' rh*rh' rh*rl positive integer format.) rl*rl' positive integer format.)
rh*rh' rh*rh' rh*rl rl*rl'
1-bit shift multiply 16-bit shift multiply Multiply Immediate
rh*rh' rh*rh'
ro/2 rh*rh' ro/2 rh*rh' rh*rh' (where (where ro^ro' ro^imm
rh*rh'
Immediate
Arithmetic right shift Immediate arithmetic right shift Binomial operation Logical right shift Immediate logical right shift Logical left shift Immediate logical left shift Immediate Immediate Exclusive Immediate exclusive Less than
ro^ro' ro^imm
(ro, ro')
ro') {ro" 0x0000000001} else {ro" 0x0000000000}
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Instruction Group
Described Simultaneously
Immediate Value
Load/Store
Monomial
Trinomial
Binomial
Transfer
Control
Branch
Loop
Clear Increment Decrement Absolute value
(ro) (ro)
0x0000000000 {ro' -ro} else {ro'
complement complement Clip
CLIP (ro)
0x007FFFFFFF) {ro' 0x007FFFFFFF} elseif 0xFF80000000) {ro' 0xFF80000000} else {ro'
Monomial operation
Round
ROUND (ro)
0x007FFF0000) {ro' 0x007FFF0000} elseif 0xFF80000000) {ro' 0xFF80000000} else {ro' 0x8000) 0xFFFFFF0000} log2 (1/ro) (sign (ro') sign (ro)) {ro' (ro' else {ro' (ro' (sign (ro') {ro'
Exponent Substitution Accumulated Accumulated Division
(ro)
Data Sheet U15203EJ3V0DS
Flag
Instruction Name
Mnemonic
Operation
Instructions That
µPD77210, 77213
Instruction Group
Described Simultaneously
Immediate Value
Load/Store
Monomial
Trinomial
Binomial
Transfer
Control
Branch
Loop
Parallel load/store
Notes
*dpx_mod *dpy_mod *dpx_mod *dpy_mod *dpx_mod *dpy_mod *dpx_mod *dpy_mod
*dpx, *dpy *dpx, *dpy *dpx *dpy *dpx *dpy dest *dpx, dest' *dpy dest *dpx, *dpy source *dpx source, dest *dpy *dpx source, *dpy source' dest *addr *addr source dest source dest source
Partial load/store
Notes
dest *dpx_mod dest' *dpy_mod
Load/store
dest *dpx_mod *dpy_mod source *dpx_mod source dest *dpy_mod *dpx_mod source *dpy_mod source' Direct addressing load/store
Note
dest *addr *addr source dest *dp_imm *dp_imm source dest source (where 0xFFFF) (where 0xFFFF) (where 0xFFFF) (where 0xFFFF)
Immediate index load/store
Registerto-register transfer
Note
Register-to-register transfer
Note
Immediate value setting Immediate value setting
Notes mnemonics, either both described. After transfer, modification specified performed. dest, dest' {ro, reh, rl}, source, source' {re, dest {ro, reh, rl}, source {re, rl}, addr X-0xFFFF: memory), Y-0xFFFF: memory)} dest {ro, reh, rl}, source {re, Select registers (except general-purpose registers) dest source.
Data Sheet U15203EJ3V0DS
Flag
Instruction Name
Mnemonic
Operation
Instructions That
µPD77210, 77213
Instruction Group
Described Simultaneously
Immediate Value
Load/Store
Monomial
Trinomial
Binomial
Transfer
Control
Branch
Loop
Jump Register-to-register jump Subroutine call
CALL
Branch
Register-to-register subroutine call
CALL
Restores interrupt enable flag. count During repeat count During loop (while LEA) LEA)
Return
Interrupt return
RETI
Repeat
count
Start
Loop Hardware loop
LOOP count (Instruction lines more)
Start
Loop
LPOP
LSR3 LSR2 LSR1 stops. stops, PLL, stopped user
operation Halt Control Stop
HALT STOP
Condition Forget interrupt
cond) FINT
Condition judgment Discards interrupt request.
Data Sheet U15203EJ3V0DS
Flag
Instruction Name
Mnemonic
Operation
Instructions That
µPD77210, 77213
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings +25°C)
Parameter Supply voltage Symbol IVDD EVDD Input voltage Output voltage Storage temperature Operating ambient temperature Tstg Condition core pins EVDD Rating Unit
Caution
Product quality suffer absolute maximum rating exceeded even momentarily parameter. That absolute maximum ratings rated values which product verge suffering physical damage, therefore product must used under conditions that ensure that absolute maximum ratings exceeded.
Recommended Operating Conditions
Parameter Operating voltage Symbol IVDD Condition core (operating speed Max.) core (operating Note speed Max.) EVDD Input voltage pins MIN. 1.425 TYP. 1.50 MAX. 1.65 Unit
1.55
1.60
1.65
EVDD
Note
µPD77210 only
Capacitance +25°C, IVDD EVDD
Parameter Input capacitance Output capacitance capacitance Symbol Condition MHz, Pins other than those tested: MIN. TYP. MAX. Unit
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Characteristics (Unless otherwise specified, 70°C, with IVDD EVDD within recommended operating condition range)
Parameter High level input voltage Symbol VIHN VIHC VIHS Condition Pins other than below CLKIN RESET, P15, TSCK, TSIEN,TSOEN, ASCK, ASIEN, ASOEN Pins other than below CLKIN RESET, P15, TSCK, TSIEN,TSOEN, ASCK, ASIEN, ASOEN -100 EVDD MIN. EVDD EVDD EVDD TYP. MAX. EVDD EVDD EVDD Unit
level input voltage
VILN VILC VILS
EVDD EVDD EVDD
High level output voltage level output voltage High level input leakage current level input leakage current High impedance leakage current Pull-up current Pull-down current Internal supply current [fclkin MHz, IVDD VIHN VIHC VIHS EVDD, load, 25°C]
ILHN
EVDD EVDD
ILLN
EVDD TDI, TMS, EVDD TRST, EVDD During operating, fclk MHz, multiple rate halt mode, fclk MHz, multiple rate division rate stop modeNote fclk stop
Note
IPUI IPDI
-200
Note
IDDH
20Note
IDDS
µPD77210 µPD77213
Notes value when with Dual Load instruction instruction executed. roughly estimated 0.35 mA/MHz. value when special program that brings about frequent switching inside device executed. roughly estimated mA/MHz. value when division rate 1/1. roughly estimated mA/MHz IDDS using divided clock. value stop mode value when stopped.
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Common Test Criteria Switching Characteristics
RESET, P15, TSCK, TSIEN, TSOEN, ASCK, ASIEN, ASOEN
EVDD EVDD EVDD
Test Points
EVDD EVDD EVDD
Input (other than above)
EVDD EVDD EVDD
Test Points
EVDD EVDD EVDD
Output
EVDD
Test Points
EVDD
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Characteristics 70°C, with IVDD EVDD within recommended operating condition range) Clock Timing requirements
Parameter CLKIN cycle time
Note
Symbol tcCX twCXH twCXL trfCX
Condition
MIN. 62.5 12.5 12.5
TYP.
MAX.
Unit
CLKIN high level width CLKIN level width CLKIN rise/fall time Internal clock cycle time
Over MHz(µPD77210 only) Under 6.25
requirements lock-up time lock frequency Note tLPLL tcPLL
8.33
When boot:P3 Note When boot:P3
Notes CLKIN cycle time must accord with lock frequency. therefore necessary satisfy both CLKIN cycle time condition 62.5 (MIN.) lock frequency condition multiplied frequency range MHz. µPD77213, only when external memory boot being used.
Switching characteristics
Parameter Internal clock cycle
Note
Symbol tcCO twCO
Condition
MIN.
TYP. tcCX
MAX.
Unit
CLKOUT cycle time CLKOUT width
High level width level width
6.25
CLKOUT rise/fall time CLKOUT delay time
trfCO tdCO
Note Multiple ratio, Division ratio (PLL, divider)
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Clock timing
tcCX twCXH twCXL trfCX trfCX
CLKIN
tcC, tcPLL
Internal clock tdCO twCO tcCO twCO trfCO trfCO
CLKOUT
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Reset, Interrupt, System Control, Timer Timing requirements
Parameter RESET level width CSTOP high level width CSTOP recovery time INTmn level width INTmn recovery time Symbol tw(RL) tw(CSTOPH) trec(CSTOP) (INTL) trec (INT) Condition MIN. tcCX
Note
TYP.
MAX.
Unit
Note
Note
Note
Note
Notes When reset timing, specified input clock. When STOP HALT mode, specified divided clock. Interrupt input TSIEN, TSOEN, ASIEN, ASOEN pins other than interrupt pins. interrupt pins function alternately pins P15. Remark INTmn
Switching characteristics
Parameter STOPS output delay time HALTS output delay time TIMOUT output delay time TIMOUT output width Symbol tdSTP tdHLT tdTIM twTIM Condition MIN. TYP. MAX. 6.25 6.25 6.25 Unit
Reset timing
tw(RL) RESET
WAKEUP timing
tw(CSTOPH) CSTOP trec(CSTOP)
Interrupt timing
trec(INT) tw(INTL) INTmn
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Standby mode status output timing
Internal clock
Internal status
Execution STOP HALT Instruction
Fetch Next Instruction STOP HALT
CSTOP tdSTP STOPS
tdHLT HALTS
tdHLT
Remarks Internal clock cycle changed stopped fixed level when STOP HALT mode. STOPS become level asynchronously CSTOP rising edge.
Timer time status output timing
Internal clock
Internal status
Detect Time
twTIM tdTIM tdTIM
TIMOUT
Data Sheet U15203EJ3V0DS
µPD77210, 77213
External Data Memory Access Timing requirements
Parameter setup time hold time MHOLDRQ setup time MHOLDRQ hold time MWAIT setup time MWAIT hold time Symbol tsuMDI thMDI tsuHRQ thHRQ tsuWAIT thWAIT Condition MIN. 17.5 11.25 11.25 TYP. MAX. Unit
Switching characteristics
Parameter output delay time output delay time output delay time output delay time MBSTB output delay time MHOLDAK output delay time Symbol tdMA tdMRD tdMWR tdMDO tdBS tdHAK Condition MIN. TYP. MAX. 6.25 6.25 6.25 6.25 6.25 6.25 Unit
Data Sheet U15203EJ3V0DS
µPD77210, 77213
External data memory access timing (Read)
Internal colck tdMA
tdMA
MA19 tsuMDI MD15 tdMRD tsuWAIT thWAIT tsuWAIT thWAIT tdMRD thMDI
MWAIT tdBS MBSTB tdBS
Remark µPD77213, possible shift fall timing cycle unit, setting MSHW register. External data memory access timing (Write)
Internal clock
tdMA
tdMA
MA19 tdMDO tdMDO Hi-Z MD15 Hi-Z
tdMDO
tdMWR
tdMWR
tsuWAIT
thWAIT
tsuWAIT
thWAIT
MWAIT tdBS
tdBS MBSTB
Remark possible shift rise/fall timing cycle unit, setting MSHW register.
Data Sheet U15203EJ3V0DS
µPD77210, 77213
arbitration timing
Internal colck
(Bus busy)
busy
idle
release tsuHRQ
idle
(Bus busy) thHRQ
tsuHRQ thHRQ MHOLDRQ tdHAK MHOLDAK tdMA,tdMDO,tdMRD,tdMWR MA19, MD15, MRD, Hi-Z tdMA,tdMDO,tdMRD,tdMWR tdHAK
Data Sheet U15203EJ3V0DS
µPD77210, 77213
General-purpose Port Timing requirements
Parameter Port input setup time Port input hold time Symbol tsuPI thPI Condition MIN. 11.25 6.25 TYP. MAX. Unit
Switching characteristics
Parameter Port output delay time Symbol tdPO Condition MIN. TYP. MAX. 6.25 Unit
General-purpose port timing
Internal clock
tdPO (output) tsuPI thPI (input)
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Host Interface Timing requirements
Parameter level width, recovery time level width, recovery time setup time hold time setup time HA,HCS hold time Symbol twHRD Condition MIN. TYP. MAX. Unit
twHWR
tsuHDI thHDI tsuHA thHA
6.25 6.25
Switching characteristics
Parameter output delay time output delay time output delay time Symbol tdRE tdWE tdHD Condition MIN. TYP. MAX. 11.25 11.25 11.25 Unit
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Host read interface timing
Interanal clock
HCS, HA0, thHA tsuHA tdHD Hi-Z tdRE tdHD Hi-Z twHRD twHRD
HD15
tdRE
Host write interface timing
Internal clock
HCS, HA0, thHA tsuHA thHDI tsuHDI HD15 tdWE twHWR twHWR
tdWE
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Serial Interface (Standard Serial mode/ serial mode) Timing requirements
Parameter ASCK cycle time Symbol tcSC Condition MIN. 12.5 12.5 TYP. MAX. Unit
ASCK high /low level width ASCK rise/fall time Serial input setup time Serial input hold time
twSC trfSC tsuSER thSER
Switching characteristics
Parameter Serial output delay time Symbol tdSER Condition MIN. TYP. MAX. 17.5 Unit
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Serial output timing
tcSC twSC ASCK, TSCK twSC trfSC trfSC
tdSER
tdSER
TSORQ tsuSER tsuSER thSER ASOEN, TSOEN tdSER ASO, Hi-Z tdSER thSER Last thSER
Note When mode, output value delay according setting value.
Serial output timing (during successive output)
tcSC twSC ASCK, TSCK twSC trfSC trfSC
tdSER
tdSER
TSORQ tsuSER thSER ASOEN, TSOEN tdSER ASO, thSER Last Hi-Z
Last
Note When mode, output value delay dummy cycle (high impedance) inserted,
according setting value.
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Serial input timing
tcSC twSC ASCK, TSCK twSC trfSC trfSC
tdSER
tdSER
TSIAK tsuSER tsuSER thSER ASIEN, TSIEN tsuSER ASI, thSER thSER
Note When mode, input value delay according setting value.
Serial input timing (during successive input)
tcSC twSC ASCK, TSCK twSC trfSC trfSC
tdSER
tdSER
TSIAK tsuSER thSER ASIEN, TSIEN
tsuSER
ASI,
thSER
Last-1
Last
Note When mode, input value delay skip cycle input, according setting value.
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Serial Interface (Audio Serial mode) Timing requirements
Parameter MCLK cycle time Symbol tcMC Condition Master mode MIN. 12.5 25.0 12.5 25.0 TYP. MAX. Unit
MCLK high/low level width MCLK rise/fall time BCLK cycle time
twMC trfMC tcBC
Master mode Master mode Slave mode
BCLK high/low level width BCLK rise/fall time Serial input setup time
twBC trfBC tsuASER
Slave mode Slave mode Slave mode Master mode
Serial input hold time
thASER
Slave mode Master mode
Switching characteristics
Parameter BCLK cycle time Symbol tcBC Condition Master mode MIN. -12.5 +25.0 17.5 TYP. MAX. Unit
BCLK high/low level width BCLK rise/fall time Serial output delay time
twBC trfBC tdASER
Master mode Master mode Master mode Slave mode
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Audio serial clock timing
tcMC twMC twMC trfMC trfMC
MCLK
Audio serial master mode timing
tcBC twBC BCLK (output) tdASER LRCLK (output) tdASER tsuASER thASER tdASER twBC trfBC trfBC
Audio serial slave mode timing
tcBC twBC BCLK (input) tsuASER LRCLK (input) tdASER tsuASER thASER tsuASER twBC trfBC trfBC
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Caution noise superimposed serial clock, serial interface deadlocked. Bear mind following points when designing your system: Reinforce wiring power supply ground noise superimposed power ground lines, same effect noise were superimposed serial clock). Shorten wiring between device's ASCK, TSCK, BCLK pins, clock supply source. cross signal lines serial clock with other signal lines. route serial clock line vicinity line through which high alternating current flows. Supply clock ASCK, TSCK, BCLK pins device from clock source oneto-one basis. supply clock several devices from clock source. Exercise care that serial clock does overshoot undershoot. particular, make sure that rising falling serial clock waveform clear.
Make sure that serial clock rises falls linearly. serial clock must bound. Noise must superimposed serial clock.
serial clock must rise fall step-wise.
Data Sheet U15203EJ3V0DS
µPD77210, 77213
card Interface (µPD77213 only) Timing requirements
Parameter SDCR input setup time SDCR input hold time SDDAT input setup time SDDAT input hold time Symbol tsuSDCR thSDCR tsuSDD thSDD Condition Input response Input response Input data Input data MIN. TYP. MAX. Unit
Switching characteristics
Parameter SDCLK cycle time SDCLK high level width SDCLK level width Symbol tcSDC twSDC(H) twSDC(L) Condition MIN. TYP.
Note
MAX.
Unit
tcSDC twSDC(H) Output command Output command Output data Output data
SDCLK rise/fall time SDCR output delay time SDCR output valid time SDDAT output delay time SDDAT output valid time
trfSDC tdSDCR tvSDCR tdSDD tvSDD
Note n:SD card clock division ratio
Data Sheet U15203EJ3V0DS
µPD77210, 77213
SDCR timing
tcSDC twSDC(L) twSDC(H) trfSDC trfSDC
SDCLK
tdSDCR SDCR (Output) tsuSDCR thSDCR SDCR (Input)
tvSDCR
SDDAT timing
tcSDC twSDC(L) twSDC(H) trfSDC trfSDC
SDCLK
tdSDD SDDAT0 (Output) tsuSDD thSDD SDDAT0 (Input)
tvSDD
Remark SDMON functions alternately external data memory interface MA13. When accessing peripheral register related card interface, SDMON (MA13) becomes high level, MA12 pins become level. timing these pins, refer External Data Memory Access.
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Debugging Interface (JTAG) Timing requirements
Parameter cycle time Symbol tcTCK Condition MIN. Note 12.5 12.5 12.5 12.5 TYP. MAX. Unit
high/low level width rise/fall time input setup time input hold time Input setup time Input hold time TRST level width
twTCK trfTCK tsuTDI thTDI tsuJIN thJIN twTRST
Note When using debugger, value tcCX (MIN.).
Switching characteristics
Parameter output delay time Output output delay time Symbol tdTDO tdJOUT Condition MIN. TYP. MAX. 17.5 17.5 Unit
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Debugging interface timing
tcTCK twTCK twTCK trfTCK trfTCK
twTRST
TRST tsuTDI thTDI
TMS,
Valid
Valid
Valid
tdTDO
tsuJIN thJIN
Capture state
Valid
tdJOUT
Update state
Remark details JTAG, refer IEEE1149.1.
Data Sheet U15203EJ3V0DS
µPD77210, 77213
PACKAGE DRAWINGS
144-PIN PLASTIC LQFP (FINE PITCH) (20x20)
detail lead
NOTE
Each lead centerline located within 0.08 true position (T.P.) maximum material condition.
ITEM MILLIMETERS 22.0±0.2 20.0±0.2 20.0±0.2 22.0±0.2 1.25 1.25 0.22±0.05 0.08 (T.P.) 1.0±0.2 0.5±0.2 0.17 +0.03 -0.07 0.08 1.4±0.05 0.10±0.05 MAX. S144GJ-50-8EN-1
Data Sheet U15203EJ3V0DS
µPD77210, 77213
161-PIN PLASTIC FBGA (10x10)
INDEX MARK
ITEM
MILLIMETERS 10.00±0.10 10.00±0.10 0.20 1.23±0.10 0.30±0.05 0.93 0.65 0.40±0.05 0.08 0.10 0.20 0.775 0.775 P161F1-65-DA2
Data Sheet U15203EJ3V0DS
µPD77210, 77213
RECOMMENDED SOLDERING CONDITIONS
µPD77210 Family should soldered mounted under following recommended conditions. details recommended soldering conditions, refer document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended below, contact your sales representative.
Surface Mounting Type Soldering Conditions
µPD77210F1-DA2:161-pin plastic fine pitch µPD77213F1-xxx-DA2:161-pin plastic fine pitch
Soldering method Soldering conditions Recommended condition symbol IR35-107-2
Infrared reflow
Package peak temperature: Time: sec. Max. higher). Count: times less Exposure limit: days Note (after that prebaking necessary hours)
µPD77210GJ-8EN:144-pin plastic LQFP (fine pitch) µPD77213GJ-xxx-8EN:144-pin plastic LQFP (fine pitch)
Soldering method Soldering conditions Recommended condition symbol IR35-103-2
Infrared reflow
Package peak temperature: Time: sec. Max. higher). Count: times less Exposure limit: days Note (after that prebaking necessary hours) temperature: Max. Time: sec. Max. (per row)
Partial heating
Note After opening pack, store less less allowable storage period. Caution different soldering methods together (except partial heating).
Data Sheet U15203EJ3V0DS
µPD77210, 77213
Regional Information
Some information contained this document vary from country country. Before using product your application, pIease contact office your country obtain list authorized representatives distributors. They will verify:
Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements
addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics Hong Kong Ltd. Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-3067-5800 Fax: 01-3067-5899 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics (France) S.A. Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 091-504-2787 Fax: 091-504-2860
Electronics Singapore Pte. Ltd.
Novena Square, Singapore Tel: 253-8311 Fax: 250-3583
Electronics Taiwan Ltd. Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 Fax: 08-63
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
Brasil S.A.
Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829
J01.2
Data Sheet U15203EJ3V0DS
µPD77210, 77213
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Data Sheet U15203EJ3V0DS
µPD77210,77213
export these products from Japan regulated Japanese government. export some these products prohibited without governmental license. export re-export some these products from country other than Japan also prohibited without license from that country. Please call sales representative.
License needed:
µPD77210F1-DA2, µPD77210GJ-8EN
customer must judge µPD77213F1-xxx-DA2, µPD77213GJ-xxx-8EN
information this document current November, 2001. information subject change without notice. actual design-in, refer latest publications NEC's data sheets data books, etc., most up-to-date specifications semiconductor products. products and/or types available every country. Please check with sales representative availability additional information. part this document copied reproduced form means without prior written consent NEC. assumes responsibility errors that appear this document. does assume liability infringement patents, copyrights other intellectual property rights third parties arising from semiconductor products listed this document other liability arising from such products. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. assumes responsibility losses incurred customers third parties arising from these circuits, software information. While endeavours enhance quality, reliability safety semiconductor products, customers agree acknowledge that possibility defects thereof cannot eliminated entirely. minimize risks damage property injury (including death) persons arising from defects semiconductor products, customers must incorporate sufficient safety measures their design, such redundancy, fire-containment, anti-failure features. semiconductor products classified into following three quality grades: "Standard", "Special" "Specific". "Specific" quality grade applies only semiconductor products developed based customer-designated "quality assurance program" specific application. recommended applications semiconductor product depend quality grade, indicated below. Customers must check quality grade each semiconductor product before using particular application. "Standard": Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade semiconductor products "Standard" unless otherwise expressly specified NEC's data sheets data books, etc. customers wish semiconductor products applications intended NEC, they must contact sales representative advance determine NEC's willingness support given application. (Note) "NEC" used this statement means Corporation also includes majority-owned subsidiaries. "NEC semiconductor products" means semiconductor product developed manufactured defined above).

µPD77210, 77213 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR

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