µPD77115 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR DESCRIP

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µPD77115 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR DESCRIP

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INTEGRATED CIRCUIT
µPD77115
16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR
DESCRIPTION
µPD77115 16-bit fixed-point digital signal processor (DSP). This based specific circuit audio application. details functions µPD77115, refer following User's Manuals:
µPD77111 Family User's Manual Architecture µPD77016 Family User's Manual Instructions
U14623E U13116E
FEATURES
Instruction cycle (operating clock) 13.3 MIN. MAX.) Memory Internal instruction Internal data Peripherals Audio serial interface Secure Digital (SD) card interface 16-bit timer 16-bit host interface 8-bit port 11.5K words bits words bits banks
Supply voltage core voltage (MAX. operation speed MHz) (MAX. operation speed MHz) voltage
Power consumption TYP. (2.0 operation)
ORDERING INFORMATION
Part Number Package 80-pin plastic FBGA 80-pin plastic TQFP (fine pitch)
µPD77115F1-CN1 µPD77115GK-9EU
information this document subject change without notice. Before using this document, please confirm that this latest version.
devices/types available every country. Please check with local representative availability additional information.
Document U14867EJ4V0DS00 (4th edition) Date Published November 2001 CP(K) Printed Japan
mark
shows major revised points.
©NEC Corporation 2000
Peripheral units Audio serial interface
Data Sheet U14867EJ4V0DS
BLOCK DIAGRAM
Data memory unit memory data addressing unit memory data addressing unit
memory
memory
card interface
Main
Port Program control unit Loop control stack Instruction memory
ALU(40)
BSFT
Host interface
stack
Interrupt control
Operation unit control
Timer
INT1 INT4
RESET
WAKEUP
CLKOUT
CLKIN
PLL0 PLL3Note
Note PLL0 PLL3 pins multiplexed with pins.
Debug interface
µPD77115
µPD77115
FUNCTION GROUPS
IVDD Audio Serial Interface SOEN/LRCLK SCK/BCLK SIEN/MCLK
EVDD RESET INT1 INT4 CLKIN CLKOUT Reset, Interrupt Clock
Card Interface
SDDAT SDCR SDCLK
WAKEUP
System Control
Port
P3,P4/PLL0 P7/PLL3 HA0,HA1 HD15 TDO,TICE TCK,TDI,TMS,TRST
Host Interface
(16) Debug Interface
Remark pins multiplexed with PLL0 PLL3 pins.
Data Sheet U14867EJ4V0DS
Data Sheet U14867EJ4V0DS
FUNCTION LIST
Item Memory space (words bits) Int. instruction Int. instruction Data (X/Y memory) Data (X/Y memory) Ext. instruction memory Ext. data memory (X/Y memory) Instruction cycle maximum operating speed) Multiple 15.3 MHz) Integer multiple (external pin) Peripheral Serial interface channels (speech CODEC) Host interface General-purpose port (I/O programmable) Timer None channel (16-bit resolution) Others Supply voltage core: pins: Package 100-pin TQFP 80-pin TQFP 80-pin FBGA 100-pin TQFP 80-pin FBGA 100-pin TQFP 80-pin TQFP 80-pin FBGA card channels (16-bit resolution) card core: pins: 8-bit bits bits 13.3 MHz) Integer multiple (mask option) Integer multiple (external pin) channel (audio CODEC) 16-bit bits (some alternative with host) channels (time-division, audio) 6.25 (160 MHz) each None each None None each None using I/F) 8.33 (120 MHz) None each each None each
µPD77110
35.5 None each
µPD77111
µPD77112
µPD77113A
µPD77114
µPD77115
11.5 None each
µPD77210
31.5
µPD77213
15.5
31.75 each
each
each
each
Integer multiple (external pin)
µPD77115
161-pin FBGA 144-pin LQFP
µPD77115
CONFIGURATIONS
80-pin plastic fine pitch
µPD77115F1-CN1
(Bottom View) (Top View)
Index mark
Name EVDD EVDD IVDD INT2 RESET I.C. I.C. SDCR WAKEUP INT1 I.C. SIEN/MCLK SCK/BCLK
Name SDDAT INT3 TRST TICE SOEN/LRCLK P5/PLL1 P7/PLL3 SDCLK INT4 IVDD P6/PLL2 P4/PLL0
Name EVDD CLKOUT EVDD CLKIN HD15 HD14 HD11
Name EVDD EVDD HD12 EVDD IVDD HD13 HD10 I.C.
Data Sheet U14867EJ4V0DS
µPD77115
80-pin plastic TQFP (fine pitch) (Top view)
µPD77115GK-9EU
SDDAT SDCR EVDD SDCLK IVDD WAKEUP INT1 INT2 INT3 INT4 RESET
TRST I.C.
EVDD
SIEN/MCLK SCK/BCLK SOEN/LRCLK P7/PLL3 P6/PLL2 P5/PLL1 P4/PLL0 EVDD HD15 HD14
TICE I.C. I.C. IVDD EVDD CLKIN CLKOUT EVDD
EVDD HD13 HD12 HD11 HD10 EVDD IVDD I.C.
Data Sheet U14867EJ4V0DS
µPD77115
Name SIEN/MCLK SCK/BCLK SOEN/LRCLK P7/PLL3 P6/PLL2 P5/PLL1 P4/PLL0 EVDD HD15 HD14 Name EVDD HD13 HD12 HD11 HD10 EVDD IVDD I.C. Name EVDD CLKOUT CLKIN EVDD IVDD I.C. I.C. TICE Name I.C. TRST RESET INT4 INT3 INT2 INT1 WAKEUP IVDD SDCLK EVDD SDCR SDDAT EVDD
Data Sheet U14867EJ4V0DS
µPD77115
NAME
CLKIN CLKOUT EVDD HA0, HD15 I.C. INT1 INT4 IVDD RESET SCK/BCLK SDCLK SDCR SDDAT SIEN/MCLK SOEN/LRCLK TICE TRST WAKEUP Clock Input Clock Output Power Supply Pins Ground Host Data Access Host Chip Select Host Data Host Read Host Read Enable Host Write Enable Host Write Internally Connected Interrupt Power Supply Core Non-Connection Port Reset Serial Clock Input/ Output Card Clock Output Card Command Output/ Response Input Card Data Input/ Output Serial Data Input Serial Input Enable/ Master Clock Input Serial Data Output Serial Output Enable/ Left Right Clock Input/ Output Test Clock Input Test Data Input Test Data Output Test In-Circuit Emulator Test Mode Select Test Reset Wakeup from STOP Mode
P4/PLL0 P7/PLL3 Port/ Setting Input
Data Sheet U14867EJ4V0DS
µPD77115
CONTENTS FUNCTION. Function Description. Connection Unused Pins FUNCTION OUTLINE Program Control Unit. Arithmetic Unit Data Memory Unit. Peripheral Unit. RESET FUNCTION. Hardware Reset Initializing PLL. FUNCTIONS BOOT-UP Boot Reset Reboot. Signature Operation. STANDBY MODES. HALT Mode STOP Mode MEMORY Instruction Memory. Data Memory. INSTRUCTIONS Outline Instructions. Instruction Operation ELECTRICAL SPECIFICATIONS PACKAGES RECOMMENDED SOLDERING CONDITIONS
Data Sheet U14867EJ4V0DS
µPD77115
FUNCTION
Because numbers differ depending package, refer diagram package used.
Function Description
Power supply
Name 80-pin FBGA IVDD EVDD A4,D7,H7 A1,A3,E8,F1, G9,H2,H4 B4,C4,D9,E3, E6,H1,H5,H9, J2,J8 80-pin TQFP 37,53,72 12,21,30,43,51, 75,80 8,18,22,31, 38,42,52,54, 73,76 Power core (+2.5 Power pins Function Shared
Ground
System control
Name 80-pin FBGA CLKIN CLKOUT 80-pin TQFP 11,10,9,7 Input Output Input System clock input Internal system clock output multiple rate setting PLL3 PLL0: 0000 x16, 0001 0100 0101 1000 1001 1100 x12, 1101 x13, 1111 RESET WAKEUP Input Input Function Shared
PLL0 PLL3 E2,D2,E1,D4
0010 0011 0110 0111 1010 x10, 1011 x11, 1110 x14,
Internal system reset signal input Stop mode release signal input. When this asserted active, stop mode released.
Interrupt
Name 80-pin FBGA INT1 INT4 B6,A5,C5,D6 80-pin TQFP 70,69,68,67 Input External maskable interrupt input. Detected falling edge. Function Shared
Data Sheet U14867EJ4V0DS
µPD77115
Serial interface
Name 80-pin FBGA SCK/BCLK 80-pin TQFP Serial clock input/output Standard serial interface(input) BCLK Audio serial interface(I/O) Serial output enable Left Right clock input/output SOEN Standard serial interface(input) LRCLK Audio serial interface(I/O) Serial data output Function Shared
SOEN/LRCLK
Output (3S) Input
SIEN/MCLK
Serial input enable Master clock input SIEN Standard serial interface MCLK Audio serial interface (Master clock input when master mode) Serial data input
Input
Remark pins marked "3S" under heading "I/O" into high-impedance state completion data transfer input hardware reset (RESET) signal. card interface
Name 80-pin FBGA SDCLK SDCR 80-pin TQFP Output (3S) card clock output card command/response Input Response Output Command pulled card data input/output Input Read data Output Write data pulled Function Shared
SDDAT
(3S)
Remark pins marked "3S" under heading "I/O" into high-impedance state when card interface being accessed.
Data Sheet U14867EJ4V0DS
µPD77115
Host interface
Name 80-pin FBGA 80-pin TQFP Input Specifies register accessed HD15 HD0. Accesses host interface status register (HST). Accesses host transmit data register (HDT (out)) when read (HRD host receive data register (HDT (in)) when written (HWR Specifies register accessed HD15 HD0. Accesses bits HST, (in), (out). Accesses bits HST, (in), (out). When 8-bit mode, this signal becomes valid. When 16-bit mode, this signal becomes invalid. HD15 H8,G7,H6,J7, F5,G6,J6,J5, G5,F4,J4,G4, H3,J3,G3,G2 41,40,36,35, 34,33,32,29, 28,27,26,25, 24,23,20,17 Input Input Input Output Output (3S) Chip select input Host read input Host write input Host read enable output Host write enable output 16-bit host data Function Shared
Input
Remark pins marked "3S" under heading "I/O" into high-impedance state when host interface being accessed. ports
Name 80-pin FBGA 80-pin TQFP General-purpose port PLL0 PLL1 PLL2 PLL3 Function Shared
Data Sheet U14867EJ4V0DS
µPD77115
Debugging interface
Name 80-pin FBGA TICE TRST 80-pin TQFP Output Output Input Input Input Input debugging Function Shared
Others
Name 80-pin FBGA I.C. A8,A9,B9,J9 80-pin TQFP 39,58,59,62 Internally connected. Leave this unconnected. No-connect pins. Leave these pins unconnected. Function Shared
A2,B1,J1
2,19,78
Caution signal input these pins attempt made read these pins, normal operation µPD77115 guaranteed.
Data Sheet U14867EJ4V0DS
µPD77115
Connection Unused Pins
1.2.1 Connection function pins When mounting, connect unused pins follows:
INT1 INT4 SCK/BCLK SIEN/MCLK SOEN/LRCLK SDCLK SDCR SDDAT HA0, HCS, HRD, HRE, HD15 TDO, TICE TMS, TRST CLKOUT WAKEUP
Note
Input Input Input Output Output Input Input Output Input Output Input Input Output Input Connect EVDD GND. Connect EVDD. Leave unconnected. Leave unconnected Connect GND. Connect EVDD. Connect EVDD GND.
Recommended Connection
Connect EVDD pull-up resistor, connect pull-down resistor.
Connect EVDD pull-up resistor, connect pull-down resistor.
Connect pull-down resistor. Leave unconnected. Leave unconnected. (internally pulled up). Leave unconnected. (internally pulled down). Leave unconnected. Connect EVDD.
Note
These pins left unconnected HCS, HRD, fixed high level. However, connect these pins recommended halt stop modes when power consumption must lowered.
1.2.2 Connection no-function pins
I.C. Leave unconnected. Leave unconnected. Recommended Connection
Data Sheet U14867EJ4V0DS
µPD77115
FUNCTION OUTLINE Program Control Unit
This unit used execute instructions, control branching, loops, interrupts, clock, standby mode DSP. 2.1.1 control three-stage pipeline architecture employed almost instructions, except some instructions such branch instructions, executed system clock. 2.1.2 Interrupt control Interrupt requests input from external pins (INT1 INT4) generated internal peripherals (serial interface host interface) serviced. interrupts also supported. 2.1.3 Loop control task loop function without hardware overhead provided. loop stack with four levels provided support multiple loops. 2.1.4 stack 15-level stack that stores program counter supports multiple interrupts subroutine calls. 2.1.5 provided clock generator that multiply external clock input supply operating clock DSP. multiple pins(PLL0 PLL3). standby modes available lowering power consumption while use. HALT mode execution HALT instruction. current consumption drops several normal operation mode recovered interrupt hardware reset. STOP mode: execution STOP instruction. current consumption drops several normal operation mode recovered hardware reset WAKEUP pin. 2.1.6 Instruction memory words instruction allocated interrupt vectors. boot-up that boots instruction provided, instruction initialized rewritten host boot (boot host interface). µPD77115 11.5K-word instruction RAM. interrupt each interrupt source enabled disabled. Multiple
Data Sheet U14867EJ4V0DS
µPD77115
Arithmetic Unit
This unit performs multiplication, addition, logical operations, shift, consists 40-bit multiply accumulator, 40-bit data ALU, 40-bit barrel shifter, eight 40-bit general-purpose registers. 2.2.1 General-purpose registers These eight 40-bit registers used input/output data arithmetic operations, load store data from/to data memory. general-purpose register made three parts: (bits (bits 16), (bits 32). Depending type operation, RnL, RnH, used register different combinations. 2.2.2 Multiply accumulator (MAC) multiplies 16-bit values, adds subtracts multiplication result from 40-bit value, outputs 40-bit value. provided with shifter (MSFT: ShiFTer) stage preceding input stage. This shifter arithmetically shift 40-bit value added subtracted from multiplication result bits right 2.2.3 Arithmetic logic unit (ALU) This unit inputs 40-bit values, executes arithmetic logical operation, outputs 40-bit value. 2.2.4 Barrel shifter (BSFT: Barrel ShiFTer) barrel shifter inputs 40-bit value, shifts left right number bits, outputs 40-bit value. data arithmetically shifted right shifted right, which case data sign-extended, logically shifted right, which case inserted from MSB.
Data Sheet U14867EJ4V0DS
µPD77115
Data Memory Unit
data memory unit consists banks data memory data addressing units. 2.3.1 Data memory have banks data memory data memory data memory). 64-word peripheral area assigned data memory space. µPD77115 words banks data RAM. 2.3.2 Data addressing unit independent data addressing unit provided each data memory data memory spaces. Each data addressing unit four data pointers (DPn), four index registers (DNn), modulo register (DMX DMY), address ALU.
Peripheral Unit
serial interface, host interface, general-purpose port, wait cycle register provided. these internal peripherals mapped data memory data memory spaces, accessed from program memory-mapped I/Os. 2.4.1 Audio Serial interface (ASIO) serial interface provided. This serial interface mode which audio serial standard serial. standard serial compatible other µPD77111 family DSP. audio serial interfaces have following features: Mode Master mode Slave mode Master mode MCLK (input), BCLK (output), LRCLK (output), support Slave mode MCLK (unused), BCLK (input), LRCLK (input) Frame format bits audio format (LRCLK format), first input/output. Handshake Handshaking with external devices implemented with dedicated frame signal (LRCLK). Handshaking with internal units, polling, wait, interrupt used. standard serial interfaces have following features: Serial clock Supplied from external source each interface. same clock used input output interface. Frame length bits, first selectable each input output Handshake Handshaking with external devices implemented with dedicated status signal. With internal units, polling, wait, interrupt used. 2.4.2 Host interface (HIO) This 16-bit parallel port that inputs data from outputs data external host controller. DSP, 16-bit register mapped memory input data, output data, status. Handshaking with external device implemented using dedicated status signal dedicated status register. Handshaking with internal units achieved means polling, wait, interrupts.
Data Sheet U14867EJ4V0DS
µPD77115
2.4.3 General-purpose port (PIO) This 8-bit port that input output mode 1-bit units. 2.4.4 card interface (SDCIF) This interface access card. supports transfer input data internal data RAM. card accessed using dedicated routine system ROM. 2.4.5 Timer This 16-bit timer unit. count source selected from system clock, card clock, serial clock INT4 input. Timer unit generates interrupt interface internal units.
RESET FUNCTION
When level specified width input RESET pin, device initialized.
Hardware Reset
RESET asserted active (low level) specified period, internal circuitry initialized. RESET then deasserted inactive (high level), boot processing instruction performed according status port pins P1). After boot processing, processing executed starting from instruction address 0x200 instruction memory (reset entry). power-ON reset function available.
Initializing
Initializing starts during boot program reset. pins (PLL0 PLL3) that specify multiple rate must kept stable duration clocks before duration clocks after reset been cleared (the clock input from CLKIN). takes locked. Until lacked, internal operated CLKIN clock. clock internal operating clock, clock control register (internal peripheral) user program.
FUNCTIONS BOOT-UP
rewrite contents instruction memory power application from program, boot instruction using internal boot-up ROM. µPD77115 function verify contents internal instruction RAM.
Boot Reset
After hardware reset been cleared, boot program first reads general-purpose ports and, depending their pattern, determines boot mode (host boot boot). After boot processing, processing executed starting from instruction address 0x200 (reset entry) instruction memory. pins that specify boot mode must kept stable duration clocks before duration clocks after reset been cleared (the clock input from CLKIN).
Data Sheet U14867EJ4V0DS
µPD77115
Boot Mode Does execute boot branches address 0x200Note. Executes host byte boot then branches address 0x200. Setting prohibited Executes host word boot then branches address 0x200.
Note This setting used when must reset recover from standby mode after reset boot been executed once. boot parameter instruction code obtained host interface, transferred instruction RAM. data transfer support byte mode word mode.
Reboot
calling reboot entry address from program, contents instruction rewritten. instruction code obtained host interface transferred instruction RAM. data transfer support byte mode word mode. entry address 0x6. Host reboot executed calling this address after setting following parameter: Number instruction steps rebooting DP3: First address instruction memory loaded
Signature Operation
µPD77115 signature operation function that contents internal instruction verified. signature operation performs specific arithmetic operation data instruction booted returns result register. Perform signature operation advance device when operating normally, repeat signature operation later check whether data correct comparing operation result with previous result. results identical, there problem. entry address 0x9. Execute operation calling this address after setting following parameter. operation result stored register R7L: Number instruction steps operation DP3: First address instruction memory operation
Data Sheet U14867EJ4V0DS
µPD77115
STANDBY MODES
standby modes available. executing corresponding instruction, each mode power consumption reduced.
HALT Mode
this mode, execute HALT instruction. this mode, functions other than clock circuit stopped reduce current consumption. release HALT mode, interrupt hardware reset. When releasing HALT mode using interrupt, contents internal registers memory retained. takes several system clocks release HALT mode when HALT mode released using interrupt. HALT Mode, clock circuit µPD77115 supplies following clock internal system clock. clock output from CLKOUT also follows. clock output from CLKOUT pin, however, high-level width that equivalent cycle normal operation (i.e., duty factor 50%). µPD77115: internal system clock integer from specified register)
STOP Mode
STOP mode, execute STOP instruction. STOP mode, functions, including clock circuit PLL, stopped power consumption minimized with only leakage current flowing. release STOP mode, hardware reset WAKEUP pin. When releasing STOP mode using WAKEUP pin, contents internal registers memory retained, takes several release mode.
Data Sheet U14867EJ4V0DS
µPD77115
MEMORY
Harvard architecture, which instruction memory space data memory space separated employed.
Instruction Memory
6.1.1 Instruction memory
0xFFFF
System
0xA000 0xBFFF Instruction words)
0x8000 0x7FFF System 0x1000 0x0FFF Instruction (3.5K words) 0x0240 0x023F Vector area words) 0x0200 0x01FF Boot-up (512 words) 0x0000
Caution Programs data cannot placed addresses reserved system, these addresses accessed. these addresses accessed, normal operation device cannot guaranteed.
Data Sheet U14867EJ4V0DS
µPD77115
6.1.2 Interrupt vector table Addresses 0x200 0x23F instruction memory entry points (vectors) interrupts. Four instruction addresses assigned each interrupt source.
Vector 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C INT1 INT2 INT3 INT4 input output SDDAT input SDDAT output input output SDCR input Timer Reset Reserved Interrupt Source
Cautions
Although reset interrupt, handled like interrupt entry vector. recommended that unused interrupt source vectors used branch error processing routine.
Data Sheet U14867EJ4V0DS
µPD77115
Data Memory
6.2.1 Data memory
0xFFFF
System
0x6000 0x5FFF Data words) 0x4000 0x3FFF System 0x3840 0x383F 0x3800 Peripheral words) 0x37FF System 0x3000 0x2FFF Data words) 0x2000 0x1FFF System 0x1000 0x0FFF Data words) 0x0000
Caution Programs data cannot placed addresses reserved system, these addresses accessed. these addresses accessed, normal operation device cannot guaranteed.
Data Sheet U14867EJ4V0DS
µPD77115
6.2.2 Internal peripherals internal peripherals mapped internal data memory space.
Memory Address 0x3800 0x3801 0x3802 0x3803 0x3804 0x3805 0x3806 0x3807 0x3808 0x380F 0x3810 0x3811 0x3812 0x3813 0x3814 0x3815 0x3816 0x3817 0x381F 0x3820 0x3821 0x3822 0x3823 0x3824 0x382D 0x382E 0x382F 0x3830 0x3831 0x3832 0x3833 0x3834 0x383F Register Name SDT/ASDT ASST Reserved area Reserved area SDDR SDCMD_IDX SDCMD_AGH SDCMD_AGL SDCTL SDRPR SDSBR Reserved area TCSR TENR Reserved area CLKCNTL Reserved area PSAR Reserved area Serial data register Serial status register Audio serial status register Caution access this area. Port data register Port command register Host data register Host status register Caution access this area. card data register card command register index card command register argument high card command register argument card control register card response register card status busy register Caution access this area. Timer initialize value register Timer count register Timer control status register Timer count enable register Caution access this area. Clock control register Caution access this area. start address register size register pointer register control register Caution access this area. SDCIF Timer SDCIF Function Peripheral Name ASIO
Cautions
register names listed this table reserved words assembler language. Therefore, when using these names assembler user must define them. same register accessed, long address same, regardless whether memory space memory space accessed. Even different registers cannot accessed same time from both memory spaces.
Data Sheet U14867EJ4V0DS
µPD77115
INSTRUCTIONS Outline Instructions
instruction consists bits. Almost instructions, except some such branch instructions, executed with system clock. maximum instruction cycle µPD77115 13.3 following nine types instructions available: Trinomial operation instructions These instructions specify operation MAC. operands, three general-purpose registers specified. Binomial operation instructions These instructions specify operation MAC, ALU, BSFT. operands, general-purpose registers specified. immediate value specified some these instructions, instead general-purpose register, input. Uninominal operation instructions These instructions specify operation ALU. operands, general-purpose register specified. Load/store instructions These instructions transfer 16-bit values between memory general-purpose register. general-purpose register specified transfer source destination. Register-to-register transfer instructions These instructions transfer data from general-purpose register another. Immediate value setting instructions These instructions write immediate value general-purpose register registers address operation unit. Branch instructions These instruction specify branching program execution. Hardware loop instructions These instruction specify repetitive execution instruction. Control instructions These instructions used control program.
Data Sheet U14867EJ4V0DS
µPD77115
Instruction Operation
operation written operation field each instruction accordance with operation representation format that instruction. more parameters written, select them. Representation formats selectable registers following table shows representation formats selectable registers.
Representation Format r0', dpx_mod dpy_mod dp_imm *xxx R0EH R7EH DMX, DPn, DPn++, DPn- DPn##, DPn%%, !DPn## DPn, DPn++, DPn- DPn##, DPn%%, !DPn## DPn##imm Contents memory with address <Example> contents register 1000, *DP0 indicates contents address 1000 memory. Selectable Register
Data Sheet U14867EJ4V0DS
µPD77115
Modifying data pointer data pointer modified after memory been accessed. result modification becomes valid starting from instruction that immediately follows. data pointer cannot modified.
Example DPn++ DPn- DPn## Operation Nothing done (value changed.) (Adds value corresponding DP7.) Example: DPn%% ((DPL DNn) (DMX ((DPL DNn) (DMY !DPn## Reverses bits then accesses memory. After memory access,
DPn##imm
Instructions that simultaneously written Instructions that simultaneously written indicated Status overflow flag (OV) status overflow flag indicated following symbol: affected when overflow occurs Caution overflow does occur result operation, overflow flag reset retains status before operation.
Data Sheet U14867EJ4V0DS
µPD77115
Instruction
Instructions Simultaneously Written Instruction Instruction Name Mnemonic Operation
Trinomial Bino- Unino- Load/ Transmial minal store Immediate value Branch Control
Flag
Loop
Trinomial operation
Multiply Multiply Sign unsign multiply
positive integer format.) positive integer format.) (ro>>1)
Unsign unsign multiply
1-bit shift multiply
16-bit shift multiply (ro>>16) Binomial operation Multiply Immediate
(where (where
Immediate
Arithmetic right shift Immediate arithmetic right shift Logical right shift Immediate logical right shift Logical left shift Immediate logical left shift Immediate Immediate Exclusive Immediate exclusive
Data Sheet U14867EJ4V0DS
µPD77115
Instructions Simultaneously Written Instruction Instruction Name Mnemonic Operation
Trinomial Bino- Unino- Load/ Transmial minal store Immediate value Branch Control
Flag
Loop
Binomial operation
Less than
(ro, ro')
ro') {ro" 0x0000000001} else {ro" 0x0000000000} 0x0000000000 {ro' -ro} else {ro' 0x007FFFFFFF) {ro' 0x007FFFFFFF} elseif 0xFF80000000} {ro' 0xFF80000000} else {ro'
Uninominal operation
Clear Increment Decrement Absolute value
(ro) (ro)
complement complement Clip
CLIP (ro)
Round
ROUND (ro)
0x007FFF0000) {ro' 0x007FFF0000} elseif 0xFF80000000} {ro' 0xFF80000000} else {ro' 0x8000) 0xFFFFFF0000}
log2
Exponent Substitution Accumulated addition Accumulated subtraction Division
(ro)
(sign (ro') sign (ro)) {ro' (ro' else {ro' (ro' ro)<<1} (sign (ro')==0) {ro'
Data Sheet U14867EJ4V0DS
µPD77115
Instructions Simultaneously Written Instruction Instruction Name Mnemonic Operation
Trinomial Bino- Unino- Load/ Transmial minal store Immediate value Branch Control
Flag
Loop
Load/ store
Parallel load/storeNotes
*dpx_mod =*dpy_mod *dpx_mod *dpy_mod *dpx_mod *dpy_mod *dpx_mod *dpy_mod
*dpx, *dpy *dpx, *dpy *dpx *dpy *dpx *dpy dest *dpx, dest *dpy dest *dpx, *dpy source *dpx source, dest *dpy *dpx source, *dpy source' dest *addr *addr source dest source dest source
Partial load/ storeNotes
dest *dpx_mod dest *dpy_mod dest *dpx_mod *dpy_mod source *dpx_mod source dest *dpy_mod *dpx_mod source *dpy_mod source'
Direct addressing load/storeNote Immediate value index load/storeNote Register- Register-toto-register register transfer transferNote Immediate value setting Immediate value setting
dest *addr *addr source dest *dp_imm *dp_imm source dest source (where 0xFFFF) (where 0xFFFF) (where 0xFFFF) (where 0xFFFF)
Notes mnemonics, either them both written. After transfer, modification specified performed. Select dest, dest' {ro, reh, rl}, source, source' {re, rl}. X-0xFFF memory) Select dest {ro, reh, rl}, source {re, rl}, addr Y-0xFFFF memory) Select dest {ro, reh, rl}, source {re, rl}. Select register other than general-purpose registers dest source.
Data Sheet U14867EJ4V0DS
µPD77115
Instructions Simultaneously Written Instruction Instruction Name Mnemonic Operation
Trinomial Bino- Unino- Load/ Transmial minal store Immediate value Branch Control
Flag
Loop
Branch
Jump Register indirect jump Subroutine call
Recovery interrupt enable flag
CALL
CALL Register indirect subroutine call Return
Interrupt return
RETI
Hardware loop
Repeat
count
Start During repeat
count count
Loop
LOOP count (instruction more lines)
Start During repeat
Loop
LPOP
LSR3 LSR2 LSR1 stops. CPU, PLL, stop Condition test Discard interrupt request
Control
operation Halt Stop
HALT STOP
Condition Forget interrupt
cond) FINT
Data Sheet U14867EJ4V0DS
µPD77115
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings +25°C)
Parameter Supply voltage Symbol IVDD EVDD Input voltage Output voltage Storage temperature Operating ambient temperature Tstg Condition core pins EVDD Rating -0.5 +3.6 -0.5 +4.6 -0.5 +4.1 -0.5 +4.1 +150 Unit
Caution Product quality suffer absolute maximum rating exceeded even momentarily parameter. That absolute maximum ratings rated values which product verge suffering physical damage, therefore product must used under conditions that ensure that absolute maximum ratings exceeded. Recommended Operating Conditions
Parameter Operating voltage Symbol IVDD EVDD Input voltage Condition core pins MIN. TYP. MAX. EVDD Unit
Capacitance +25°C, IVDD EVDD
Parameter Input capacitance Output capacitance capacitance Symbol Condition MHz, Pins other than those tested: MIN. TYP. MAX. Unit
Data Sheet U14867EJ4V0DS
µPD77115
Characteristics (Unless otherwise specified, 85°C, with IVDD EVDD within recommended operating condition range)
Parameter High-level input voltage Symbol VIHN VIHS Condition Pins other than below RESET, INT1 INT4, SCK, SIEN, SOEN CLKIN MIN. EVDD EVDD TYP. MAX. EVDD EVDD Unit
VIHC
EVDD +0.25
EVDD
Low-level input voltage
Pins other than below CLKIN -2.0 -100
EVDD EVDD -0.25
High-level output voltage
EVDD EVDD EVDD -250
Low-level output voltage High-level input leakage current Low-level input leakage current Pull-up current Pull-down current Internal supply current [VIHN VIHS EVDD, load]
Other than TDI, TMS, TRST EVDD Other than TDI, TMS, TRST TDI, TMS, EVDD TRST, EVDD During operating, IVDD halt mode, divided eight, IVDD stop mode, 60°C
IPUI IPDI IDDNote
IDDH
IDDS
Note TYP. values when ordinary program executed. MAX. values when special program that brings about frequent switching inside device executed.
Data Sheet U14867EJ4V0DS
µPD77115
Common Test Criteria Switching Characteristics
EVDD EVDD EVDD EVDD EVDD EVDD
RESET, INT1 INT4, SCK, SIEN, SOEN
Test points
CLKIN
EVDD+0.25 EVDD EVDD-0.25
Test points
EVDD+0.25 EVDD EVDD-0.25
Input (other than above)
EVDD EVDD EVDD
Test points
EVDD EVDD EVDD
Output
EVDD
Test points
EVDD
Data Sheet U14867EJ4V0DS
µPD77115
µPD77115
Characteristics 85°C, with IVDD EVDD within recommended operating condition range) Clock Timing requirements
Parameter CLKIN cycle time
Note
Symbol tcCX
Condition
MIN.
TYP.
MAX.
Unit
lock rangeNote
IVDD IVDD
CLKIN high-level width CLKIN low-level width CLKIN rise/fall time Internal clock cycle time requirementsNote
twCXH twCXL trfCX IVDD IVDD
12.5 12.5 13.3
Notes Multiple This range which locked (stably oscillates). Input tcCX within this range. Input tcCX that value (tcCX satisfies this condition. Multiple, Division ratio Switching characteristics
Parameter Internal clock cycle
Note
Symbol
Condition External clock operation clock operation HALT mode
MIN.
TYP. tcCX (tcCX (tcCX
MAX.
Unit
CLKOUT cycle time CLKOUT width
tcCO twCO During normal operation even number number (other than
HALT mode CLKOUT rise/fall time CLKOUT delay time trfCO tdCO IVDD IVDD
Note Multiple, Division ratio, HALT division ratio
Data Sheet U14867EJ4V0DS
µPD77115
µPD77115
Clock timing
tcCX twCXH twCXL trfCX trfCX
CLKIN
tcC, tcC(R)
Internal clock
tcCO tdCO twCO twCO trfCO trfCO
CLKOUT
Data Sheet U14867EJ4V0DS
µPD77115
µPD77115
Reset, Interrupt Timing requirements
Parameter RESET low-level width WAKEUP low-level width INT1 INT4 low-level width INT1 INT4 recovery time Symbol (RL) (WAKEUPL) (INTL) Condition MIN.
Note
TYP.
MAX.
Unit
tcCNote
trec (INT)
Note
Note that integer times that during normal operation HALT mode.
Reset timing
tw(RL) RESET
WAKEUP timing
tw(RL) RESET
Interrupt timing
trec(INT) tw(INTL) INT1 INT4
Data Sheet U14867EJ4V0DS
µPD77115
µPD77115
Serial Interface (Audio Serial mode) Timing requirements
Parameter MCLK cycle time MCLK high-/low-level width MCLK rise/fall time BCLK cycle time BCLK high-/low-level width BCLK rise/fall time LRCLK setup time setup time hold time Symbol tcMC twMC trfMC tcBC twBC trfBC tsu(BC-LR) tsuSI thSI Condition Master mode Master mode Master mode Slave mode Slave mode Slave mode Slave mode MIN. tcMC Note TYP. MAX. Unit
Note maximum value tcMC Switching characteristics
Parameter BCLK cycle time Symbol tcBC Condition Master mode, 64-bit mode Master mode, 32-bit mode BCLK high-/low-level width BCLK rise/fall time LRCLK delay time output delay time twBC trfBC td(BC-LR) tdSO Master mode Master mode Master mode tcBC MIN. TYP. 1/64 1/32 MAX. Unit
Data Sheet U14867EJ4V0DS
µPD77115
µPD77115
Audio Serial clock timing
tcMC twMC twMC trfMC trfMC
MCLK
Audio Serial Master mode timing
tcBC twBC BCLK (OUTPUT) td(BC-LR) LRCLK (OUTPUT) tdSO tsuSI thSI td(BC-LR) twBC trfBC trfBC
Audio Serial Slave mode timing
tcBC twBC BCLK (INPUT) tsu(BC-LR) LRCLK (INPUT) tdSO tsuSI thSI tsu(BC-LR) twBC trfBC trfBC
Data Sheet U14867EJ4V0DS
µPD77115
µPD77115
Serial Interface (Standard Serial mode) Timing requirements
Parameter cycle time high-/low-level width rise/fall time SOEN setup time Symbol tcSC twSC trfSC tsuSOE IVDD IVDD SOEN hold time thSOE IVDD IVDD SIEN setup time tsuSIE IVDD IVDD SIEN hold time thSIE IVDD IVDD setup time tsuSI IVDD IVDD hold time thSI IVDD IVDD Condition MIN. 2tcC TYP. MAX. Unit
Switching characteristics
Parameter output delay time Symbol tdSO Condition IVDD IVDD hold time thSO MIN. TYP. MAX. Unit
Data Sheet U14867EJ4V0DS
µPD77115
µPD77115
Serial output timing
tcSC twSC tsuSOE tsuSOE thSOE thSOE SOEN tdSO Hi-Z tdSO Last thSO twSC trfSC trfSC
Serial output timing (during successive output)
tcSC twSC tsuSOE thSOE SOEN tdSO Last Last twSC trfSC trfSC
thSO
Data Sheet U14867EJ4V0DS
µPD77115
µPD77115
Serial input timing
tcSC twSC tsuSIE tsuSIE thSIE SIEN thSIE twSC trfSC trfSC
tsuSI
thSI
Serial input timing (during successive input)
tcSC twSC tsuSIE thSIE SIEN tsuSI thSI twSC trfSC trfSC
Last-1
Last
Data Sheet U14867EJ4V0DS
µPD77115
µPD77115
Caution noise superimposed serial clock, serial interface deadlocked. Bear mind following points when designing your system: Reinforce wiring power supply ground noise superimposed power ground lines, same effect noise were superimposed serial clock). Shorten wiring between device's pin, clock supply source. cross signal lines serial clock with other signal lines. route serial clock line vicinity line through which high alternating current flows. Supply clock device from clock source one-to-one basis. supply clock several devices from clock source. Exercise care that serial clock does overshoot undershoot. particular, make sure that rising falling serial clock waveform clear.
Make sure that serial clock rises falls linearly. serial clock must bound. Noise must superimposed serial clock.
serial clock must rise fall step-wise.
Data Sheet U14867EJ4V0DS
µPD77115
µPD77115
Host Interface Timing requirements
Parameter delay time Symbol tdHR Condition IVDD IVDD width HCS, HA0, HA1, read hold time HCS, HA0, write hold time HRD, recovery time delay time twHR thHCAR MIN. TYP. MAX. Unit
thHCAW
trecHS tdHW IVDD IVDD
3tcC IVDD IVDD
width hold time setup time
twHW thHDW tsuHDW
Switching characteristics
Parameter HRE, output delay time Symbol tdHE Condition IVDD IVDD HRE, hold time thHE IVDD IVDD valid time tvHDR IVDD IVDD hold time thHDR MIN. TYP. MAX. Unit
Data Sheet U14867EJ4V0DS
µPD77115
µPD77115
Host read interface timing
CLKIN
HCS, HA0, thHCAR tdHR thHDR Hi-Z tdHE tvHDR Hi-Z twHR trecHS
HD15
thHE
Host write interface timing
CLKIN
HCS, HA0, thHCAW tdHW thHDW tsuHDW HD15 tdHE twHW trecHS
thHE
Data Sheet U14867EJ4V0DS
µPD77115
µPD77115
General-purpose Port Timing requirements
Parameter Port input setup time Port input hold time Symbol tsuPI thPI IVDD IVDD Condition MIN. TYP. MAX. Unit
Switching characteristics
Parameter Port output delay time Symbol tdPO Condition IVDD IVDD MIN. TYP. MAX. Unit
General-purpose port timing
CLKIN
tdPO (Output) tsuPI thPI (Input)
Data Sheet U14867EJ4V0DS
µPD77115
µPD77115
card Interface Timing requirements
Parameter SDCR input setup time SDCR input hold time SDDAT input setup time SDDAT input hold time Symbol tsuSDCR thSDCR tsuSDD thSDD Condition Input Response Input Response Input data Input data MIN. TYP. MAX. Unit
Switching characteristics
Parameter SDCLK cycle time SDCLK high- level width SDCLK low-level width SDCLK rise/fall time SDCR output delay time SDCR output valid time SDDAT output delay time SDDAT output valid time Symbol tcSDC twSDCH twSDCL trfSDC tdSDCR tvSDCR tdSDD tvSDD Output Command Output Command Output data Output data Condition MIN. TYP. MAX. Unit
Data Sheet U14867EJ4V0DS
µPD77115
µPD77115
SDCR timing
tcSDC twSDCL twSDCH trfSDC trfSDC
SDCLK
tdSDCR SDCR (Output) tsuSDCR thSDCR SDCR (Input)
tvSDCR
SDDAT timing
tcSDC twSDCL twSDCH trfSDC trfSDC
SDCLK
tdSDD SDDAT (Output) tsuSDD thSDD SDDAT (Input)
tvSDD
Data Sheet U14867EJ4V0DS
µPD77115
µPD77115
Debugging Interface (JTAG) Timing requirements
Parameter cycle time high-/low-level width rise/fall time TMS, setup time Symbol tcTCK twTCK trfTCK tsuDI IVDD IVDD TMS, hold time thDI IVDD IVDD Input setup time tsuJIN IVDD IVDD Input hold time thJIN IVDD IVDD TRST setup time tsuTRST Condition MIN. TYP. MAX. Unit
Switching characteristics
Parameter output delay time Symbol tdDO Condition IVDD IVDD Output output delay time tdJOUT IVDD IVDD MIN. TYP. MAX. Unit
Data Sheet U14867EJ4V0DS
µPD77115
µPD77115
Debugging interface timing
tcTCK twTCK twTCK trfTCK trfTCK
tsuTRST
TRST tsuDI thDI
TMS,
Valid
Valid
Valid
tdDO
tsuJIN thJIN
Capture state
Valid
tdJOUT
Update state
Remark details JTAG, refer IEEE1149.1.
Data Sheet U14867EJ4V0DS
µPD77115
PACKAGES
80-PIN PLASTIC FBGA (9x9)
Index mark
ITEM MILLIMETERS 9.00±0.10 8.40 8.40 9.00±0.10 1.30 (T.P.) 0.35±0.1 0.36 0.96 1.31±0.15 0.10
0.50+0.05 -0.10
0.08 C1.0 R0.3 0.20 0.20 S80F1-80-CN1-1
Data Sheet U14867EJ4V0DS
µPD77115
80-PIN PLASTIC TQFP (FINE PITCH) (12x12)
detail lead
NOTE Each lead centerline located within 0.10 true position (T.P.) maximum material condition.
ITEM
MILLIMETERS 14.0±0.2 12.0±0.2 12.0±0.2 14.0±0.2 1.25 1.25 0.22±0.05 0.10 (T.P.) 1.0±0.2 0.5±0.2 0.145±0.05 0.10 1.0±0.05 0.1±0.05 MAX. S80GK-50-9EU-1
Data Sheet U14867EJ4V0DS
µPD77115
RECOMMENDED SOLDERING CONDITIONS
recommended solder this product under following conditions. details recommended soldering conditions, refer information document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E). soldering methods conditions other than those recommended, consult NEC. Surface-Mount Type PD77115GK-9EU: 80-pin plastic TQFP (fine-pitch)
Soldering Process Infrared reflow Soldering Conditions Package peak temperature: 235°C, Time: seconds (210°C MIN), Number times: MAX, Number days: 3Note (after that, prebaking necessary hours 125°C)) Package peak temperature: 215°C, Time: seconds (200°C MIN), Number times: MAX, Number days: 3Note (after that, prebaking isnecessary hours 125°C) temperature: 300°C MAX, Time: seconds (per side device) Symbol IR35-103-2
VP15-103-2
Partial heating method
PD77115F1-CN1: 80-pin plastic FBGA
Soldering Process Infrared reflow Soldering Conditions Package peak temperature: 235°C, Time: seconds (210°C MIN), Number times: MAX, Number days: 3Note (after that, prebaking necessary hours 125°C)) Package peak temperature: 215°C, Time: seconds (200°C MIN), Number times: MAX, Number days: 3Note (after that, prebaking isnecessary hours 125°C) Symbol IR35-103-2
VP15-103-2
Note Number days storage after pack been opened. storage conditions 25°C, MAX. Caution Apply wave soldering only pins careful bring solder into direct contact with package.
Data Sheet U14867EJ4V0DS
µPD77115
Regional Information
Some information contained this document vary from country country. Before using product your application, pIease contact office your country obtain list authorized representatives distributors. They will verify:
Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements
addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics Hong Kong Ltd. Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-3067-5800 Fax: 01-3067-5899 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics (France) S.A. Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 091-504-2787 Fax: 091-504-2860
Electronics Singapore Pte. Ltd.
Novena Square, Singapore Tel: 253-8311 Fax: 250-3583
Electronics Taiwan Ltd. Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 Fax: 08-63
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
Brasil S.A.
Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829
J01.2
Data Sheet U14867EJ4V0DS
µPD77115
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Data Sheet U14867EJ4V0DS
µPD77115
information this document current November, 2001. information subject change without notice. actual design-in, refer latest publications NEC's data sheets data books, etc., most up-to-date specifications semiconductor products. products and/or types available every country. Please check with sales representative availability additional information. part this document copied reproduced form means without prior written consent NEC. assumes responsibility errors that appear this document. does assume liability infringement patents, copyrights other intellectual property rights third parties arising from semiconductor products listed this document other liability arising from such products. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. assumes responsibility losses incurred customers third parties arising from these circuits, software information. While endeavours enhance quality, reliability safety semiconductor products, customers agree acknowledge that possibility defects thereof cannot eliminated entirely. minimize risks damage property injury (including death) persons arising from defects semiconductor products, customers must incorporate sufficient safety measures their design, such redundancy, fire-containment, anti-failure features. semiconductor products classified into following three quality grades: "Standard", "Special" "Specific". "Specific" quality grade applies only semiconductor products developed based customer-designated "quality assurance program" specific application. recommended applications semiconductor product depend quality grade, indicated below. Customers must check quality grade each semiconductor product before using particular application. "Standard": Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade semiconductor products "Standard" unless otherwise expressly specified NEC's data sheets data books, etc. customers wish semiconductor products applications intended NEC, they must contact sales representative advance determine NEC's willingness support given application. (Note) "NEC" used this statement means Corporation also includes majority-owned subsidiaries. "NEC semiconductor products" means semiconductor product developed manufactured defined above).

µPD77115 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR DESCRIP

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