LINE SCAN BUFFER with 16BIT COMPATIBLE INPUTS LINE SCAN BUFFER with 16

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LINE SCAN BUFFER with 16BIT COMPATIBLE INPUTS LINE SCAN BUFFER with 16

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M66307SP/FP M66307SP/FP
LINE SCAN BUFFER with 16BIT COMPATIBLE INPUTS LINE SCAN BUFFER with 16-BIT COMPATIBLE INPUTS
M66307SP/FP integrated circuit consisting line buffer with static memory, manufactured silicon gate CMOS process, which satisfies A3-paper 400DPI requirements. converts stored data from 16-bit into serial data outputs transfer rate 10Mbps synchronously with external data request clock arbitrary continuous clock.
CONFIGURATION (TOP VIEW)
DATA INPUTS
VCC(5V)
DATA INPUTS
WRITE CONTROL INPUT CHIP SELECT INPUT COMMAND/DATA CONTROL INPUT RESET INPUT RESET INTERRUPT REQUEST INTR OUTPUT CLOCK INPUT CLK/ CLOCK ENABLE CLKE INPUT
FEATURES
ACKNOWLEDGE INPUT REQUEST DREQ OUTPUT
M66307SP/FP
16-bit compatible Writing data DMAC possible 320-word (5,120-bit) static Data output rate 10Mbps Built-in function fixed data specified length beginning output data (Fixed data: Continuous High data) output format selected between FIFO LIFO. output method selected from two: Synchronized with arbitrary continuous clock system side; frequency clock output (CLK/ OUT) divided Synchronized with data request clock (CLK peripheral equipment side. devices cascaded. Toggle configuration 32-bit configuration High fan-out outputs (CLK/ OUT, DATA OUT). Io=±24mA (±4mA INTR DREQ ±8mA BUSY/ORDY)
DACK
EXTENDED INPUT TOGGLE INPUT CLK/ CLOCK
OUTPUT BUSY/ OUTPUT READY OUTPUT
DATA DATA OUTPUT BUSY/ORDY
(0V)GND
Outline 32P4B 32P2W-A
clock input (CLK/ contains Schmitt trigger. reset (RESET), Write (WR) toggle input (TOG) contain negative noise reduction circuits.
APPLICATION
Image-handling general equipment
BLOCK DIAGRAM
DACK
Write control circuit Command registers Data buffer
Fixed data length register
Write/send address control circuit
Parallel-serial converter
Output control circuit
DREQ
DREQ words register Mode register word CMOS SRAM Expansion control circuit
Output control circuit
INTR BUSY/ORDY
Output control circuit
DATA
CLK/ CLKE RESET
Clock control circuit Reset control circuit
Frequency divider
Clock signal select circuit
Output control circuit
CLK/
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LINE SCAN BUFFER with 16-BIT COMPATIBLE INPUTS
FUNCTION
M66307 outputs serial data from system peripheral equipment. Containing internal 320-word (5,120-bit) line buffer, output number words(up words) stored data from data time. data output synchronously with arbitrary continuous clock system side data request clock (CLK from peripheral equipment. data output first, FIFO (First-in, First-out)
LIFO (Last-in, First-out) programmed user. When programmed, clock output format defaulted FIFO, respectively. addition above basic functions, M66307 such programmable functions that fixed data specified length beginning output data, store line fixed data using single substitute command, repetitively output data stored line buffer.
OPERATION
Interface M66307 M66307 interface sections, system side peripheral equipment side
shown Figure words data stored from system side output peripheral equipment after parallel-serial conversion.
Address
Control Data System interface section
D0~D15
RESET
DACK DREQ INTR BUSY
CLKE
DATA
CLK/ ORDY Peripheral equipment interface section
Notes Connect address directly decoder. Select either (indicated broken line) Connect DACK DREQ (indicated broken line) when transfer used. Make sure unused active inputs pulled-up VCC.
Fig. Interface M66307
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LINE SCAN BUFFER with 16-BIT COMPATIBLE INPUTS
following describes operation M66307 using operation flowchart Fig. M66307 three modes: "static mode", "write mode", "send mode". static mode, M66307 standby state. M66307 remains this mode until write mode operation mode setting command after reset input until write mode after (operation) stop command stored. write mode, M66307 stores words data from 16-bit system bus. send mode, M66307 serially outputs data stored write mode. write send modes operation mode setting command. Static mode static mode, M66307 first initialized. This initialization involves selecting setting divide ratio when selected, specifying expansion/normal, data store cycle cycle, presence fixed beginning data specified length added beginning data output, polarity (High Low) fixed data. Once above programmed, M66307 executes functions according specification until changed. After initialization completed, M66307 must programmed specification output formats LSB/ LIFO/FIFO. addition, when "addition fixed data specified length beginning data output" specified initialization, length fixed beginning data must programmed; similarly, when "data store cycle" specified, number words line transferred must programmed. Once programmed, specified format continued until changed. initialization these settings only made static mode. When want change specification middle operation, place M66307 static mode using stop command reprogram setting. When initializing device setting output format after rest input, your setting same default value, programming omitted. (See note Fig. When above settings completed, M66307 ready data transfer from system peripheral equipment. Write mode When settings static mode completed, write mode. this mode, signals write internal memory enabled, data stored internal memory each write cycle executed controller. When storing line fixed data, note that once word length line stored command, M66307 operates same line fixed data stored. write mode, data output (DATA OUT) outputs
polarity "fixed data" that been initialization. (See Fig. Send mode After storing data write mode completed, send mode. this mode, M66307 serially outputs data stored write mode according setting addition fixed beginning data settings LSB/MSB LIFO/FIFO. While data output, M66307 outputs Busy/Output Ready signal (BUSY/ORDY). When line length data output, BUSY/ORDY cleared interrupt request signal (INTR) output. next line, restart from setting write mode. want output same data line, same data repetitively output without storing using transmit repeat request command. When want stop M66307 middle operation change some settings, stop command. stop command valid both write send modes. When operation stopped, initialize M66307 reprogram output specification, length fixed beginning data, number transfer words, When reprogram, same settings before operation stopped continued.
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LINE SCAN BUFFER with 16-BIT COMPATIBLE INPUTS
Reset C/D=1 Initialization Static mode
C/D=1
number DREQ words. length fixed beginning data. output format.
C/D=1
write mode
C/D=1
operation stop
Fixed data line output?
Write mode
C/D=1
line fixed data length.
C/D=0 Storing data from data DACK=0 Storing data line length completed? C/D=1 send mode (BUSY/ORDY output)
Outputting data
C/D=1 Outputting data line length completed? transmit repeat request (INTR output)
Send mode
Repetitive output
Completed?
Fig. Operation flowchart M66307
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LINE SCAN BUFFER with 16-BIT COMPATIBLE INPUTS
DESCRIPTIONS
D0~D15 Name Data inputs Write control input Chip select input acknowledge input Command/ data control input Reset input Input Input Input Normally connected 16-bit bus. Data command stored M66307 High transition. This signal normally connected write control signal control bus. When Low, this signal allows data command stored from M66307. normally connected address directly decoder. When this signal High, cannot access M66307. When Low, this signal allows data stored transfer. normally connected acknowledge output (DACK) controller.For systems where transfer used, this must pulled-up VCC. This signal discriminates whether information data when accessed M66307 command data. When High, signal indicates that information command; when Low, indicates data. normally connected address directly decoder. When Low, this signal initializes command registers various circuits M66307. result, active output signals High; clock outputs (CLK, OUT) High; data output (DATA OUT) Low. This signal requests cycles. When data store cycle defined initialization number transfer words specified, this output when M66307 into write mode. When number cycles completed, returns High. This signal requests interrupt when written data sent (Low output). This request cleared access toggle input(TOG) [when extended toggle used] (High output). When Low, this signal informs that commands other than STOP M66307, informs peripheral equipment that M66307 sending data. When M66307 send mode, this signal Low; when transmission completed, returns High. When Low, this signal enables clock input (CLK/ IN); when High, disables clock input. When clock input CLKE invalid that this must pulled-up pulled-down GND. generally used data request clock from peripheral equipment; generally used continuous clock system side. Selection between specified initialization command. Select when data output timing must matched timing peripheral equipment. Select when timing need matched data sent stroke using clock from system. divided into five smaller frequencies when peripheral equipment slow read data. (Note: continuous clock necessarily system clock.) This signal only valid when extended toggle used (using M66307s) selected clock input. This input sets write send modes. Each time this signal Low, write mode reversed send mode send mode reversed write mode. impossible control mode inversion with this function operation mode setting command together. data stored internal memory fixed data serially output synchronously with clock input (CLK/ according settings output format (LSB/MSB, LIFO/FIFO). Peripheral devices take data with "rise" clock pulses. This signal used extended system using M66307s. Connect master DATA slave slave must pulled-up VCC. (See application example.) normal use, pull pull down GND. Function
DACK
Input
Input
RESET
Input
DREQ
request output
Output
INTR BUSY/ ORDY
Output Interrupt request output BUSY/ OUTPUT READY output Clock enable input Clock input Output
CLKE CLK/
Input Input
Toggle input
Input
DATA CLK/
Data output
Output
Clock output Extended input
Output Input
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LINE SCAN BUFFER with 16-BIT COMPATIBLE INPUTS
Outline commands
When accesses M66307 write with High shown Table M66307 reads information data into register command. When Table Access Write DACK
accesses M66307 write with Low, M66307 reads information into internal memory data. There eight kinds commands classified upper four (D15 D12).
Function M66307 cannot accessed. Command stored internal command register. Data stored internal memory. (During cycle) (During cycle)
denotes
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LINE SCAN BUFFER with 16-BIT COMPATIBLE INPUTS
Register configuration
M66307 command registers shown Figure mode register consists total eight flags (F0-F7) seven bits (B0-B6). Each flag default values (=0) reset input. There some commands that have register. These include line fixed data setting command, transmit repeat request command, stop command.
Group Group
Group Group
Initialization command DREQ words setting command Fixed beginning date length setting command Output format setting command Operation mode setting command line fixed data setting command Transmit repeat request command Stop command
Command organization
commands broadly classified into four groups shown Fig. shows relationship between three modes M66307 (static, write send modes) storable commands. Command Mode Static Write Send complete (BUSY="H") Send (BUSY="L") Group Group Group Group
Send
Note Command store valid within Fig. Command store
Description commands
Command Upper name (D15~D12) Initialization command DREQ words setting command Fixed beginning data length setting command Output format setting command Operation mode setting command 1000 Contents This command initializes hardware setting system selecting clock input setting specification extension, specification DREQ output, specification fixed data output, logical polarity "fixed data." When set, M66307 outputs from DREQ when setting write mode. When [N+1] words written controller (MPU), outputs High from DREQ pin. This command sets length fixed beginning data from 4,095. When fixed beginning data length setting register, "fixed data" output from DATA each time send mode entered. When "fixed data" [n+1] bits output, M66307 starts outputting data stored memory. Clock output (CLK/ OUT), clock synchronization, output even while fixed data being output. Note that even when output format LIFO, data internal memory output after outputting fixed data completed. This command sets output format LIFO FIFO first first. This command stored 4-bit (B3, register shown Figure write send modes this register. send mode setting command when extended 32-bit system used mode inverting command when extended toggle system used two-word commands. Store second word after storing first word. DREQ mask bit. write mode setting B3=1 when DREQ mode (F4=1), M66307 does output from DREQ pin. When DREQ mode, B3=1 when setting write mode before storing line fixed data setting command. impossible control mode inversion with this command extended toggle input (TOG) together. When this command stored, obtain same effect writing "fixed data" number words. When send mode, "fixed data" equivalent [(fixed beginning data value+1)+(one line fixed data setting word value+1)x16] bits output along with sync clock (CLK/ OUT). This command allows resend same data that already been sent. This command becomes executable after transmission completed. When using extended system, store second word operation mode setting command following transmit repeat request command. This command stops operation M66307. This command valid modes. initializes registers circuits except initialization register, output format setting register, DREQ words setting register, fixed beginning data length register, thereby placing M66307 into static mode. addition stopping operation, this command used when want store commands that only valid static mode (e.g., group group commands).
0111 0110
0100 0000
line fixed data setting command Transmit repeat request command Stop command
0011
0010
1111
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LINE SCAN BUFFER with 16-BIT COMPATIBLE INPUTS
FLAG Mode register
0=CLK
Valid when D11=1- Divide retio setting (See Table Toggle extension flag(1=toggle; 0=normal use) Invalid when D4=1-32-bit extension flag (1=32; 0=16-bit bus) DREQ mode flag(1=DREQ mode; 0=not DREQ mode) Fixed beginning data output flag (1=output; 0=not output) Fixed data polarity flag (1=High; 0=Low)
Initialization command D15D14D13D12 D11D10
DREQ words register Fixed beginning data length register
DREQ words setting command (valid when F4=1)
Number transfer words
Fixed beginning data length setting command (valid when F3=1) E11E10
Number fixed beginning data output bits
Mode register
Output format setting command
LIFO/FIFO flag (1=LIFO; 0=FIFO output) LSB/MSB-first flag (1=LSB; 0=MSB-first output)
line fixed data setting command
line fixed data output line length
Transmit repeat request command (Note Operation mode setting bits (See Table
Mode register
Operation mode setting command
Stop command
Table Divide Ratio Setting Divide ratio 1/16
Table Operation Mode Setting Item Write mode Send mode Write mode Exten- bits First word Send mode Second word First word Toggle Mode inversion Second word Normal
Store first
word, then store second word. DREQ mask (Refer description commands.)
Note default values flags (F0-F7) bits (B0-B6) zero (0). When using extended system, store second word operation mode setting command following transmit repeat request command. impossible control mode inversion with operation mode setting command extended toggle input (TOG) together. Fig. Register configuration M66307
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LINE SCAN BUFFER with 16-BIT COMPATIBLE INPUTS
Operation timing
Storing commands data from system M66307 Figures show timings which commands data from system stored M66307 after reset input stop command issued.
Output format Fixed beginning Write mode Intialization data length DACK D0~D15 DREQ DATA Static mode
1WORD
(N-1)WORD
NWORD
Fixed data Write mode
Note Number transfer words 320; fixed data length 4,096
Fig. Storing commands data cycle
Intialization DACK D0~D15 DREQ DATA
Number Fixed beginning Output format DREQ words data length Write mode (N-1)
1WORD
(N-1)WORD
NWORD
Static mode cycle
Fixed data
Write mode cycle
Note Number transfer words 320; fixed data length 4,096 Fig. Storing commands cycle storing data cycle
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LINE SCAN BUFFER with 16-BIT COMPATIBLE INPUTS
Sending data from M66307 peripheral equipment After data line stored from system into M66307, M66307 serially sends data peripheral equipment. There methods send data shown Fig. Figures show send timings four send method.
Without fixed beginning data output With fixed beginning data output Sending method Without fixed beginning data output With fixed beginning data output
FIFO LIFO FIFO LIFO FIFO LIFO FIFO LIFO
Fig. Fig. Fig.
Fig.
Fig. Various methods sending data
Send mode DACK D0~D15 CLK/ DATA Fixed data BUSY/ORDY INTR DREQ Note DATA outpus fixed data with more. Transfer words i=transfer words (0-N); j=bits (0-F) Fig. Send timing M66307 (CLK without fixed beginning data output, FIFO, MSB) (Note)
Write mode
(Fixed data)
Fixed data
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LINE SCAN BUFFER with 16-BIT COMPATIBLE INPUTS
Send mode DACK Note D0~D15 CLK/ DATA Fixed data BUSY/ORDY INTR DREQ Note DATA outputs fixed data with more. N:Transfer words; n:fixed beginning data length (register value) Dij: i=transfer words (0-N); j=bits (0-F) Fig. Send timing M66307 (CLK with fixed begnning data output, FIFO, MSB) (Note) (Y+1) (Y+2)
Write mode
(Fixed data)
Fixed data
Send mode D0~D15 CLK/ DATA Fixed data BUSY/ORDY INTR
Note same input/output conditions Figure shown here. Fig. Send timing M66307 without fixed data output, FIFO, MSB)
Write mode
Fixed data
Send mode D0~D15 CLK/ DATA Fixed data (Note)
(Fixed
Write mode
data) Fixed data
FIFO, Output formats FIFO, LIFO, LIFO,
Note same input/output conditions Figure shown here. Fig. Send timing M66307 (CLK without fixed data output)
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LINE SCAN BUFFER with 16-BIT COMPATIBLE INPUTS
ABSOLUTE MAXIMUM RATINGS
Symbol Tstg Supply voltage Input voltage Output voltage Power dissipation Storage temperature Ta=25°C Parameter Condition Rating -0.3~+7.0 -0.3~VCC+0.3 0~VCC -65~+150 Unit
RECOMMENDED OPERATING CONDITIONS (Ta=0~70°C unless otherwise noted)
Symbol Topr Supply voltage Supply voltage Input voltage Output voltage Ambient temperature Parameter Min. Limits Typ. Max. Unit
ELECTRICAL CHARACTERISTICS (Ta=0~70°C, VCC=5V±10% unless otherwise noted)
Symbol ICC1 ICC2 Input voltage Input voltage Positive threshold voltage Negative threshold voltage Hysteresis width Output voltage Output voltage Output voltage Output voltage Output voltage Output voltage Input current Parameter D0~D15, C/D, DACK, Test condition Min. -0.3 -0.3 DATA OUT, CLK/ BUSY/ORDY DREQ, IOH=-24mA IOL=+24mA IOH=-8mA IOL=+8mA IOH=-4mA IOL=+4mA VI=0~VCC VI=0 Output open VI=0 Output open VCC-0.8 0.55 VCC-0.8 0.55 VCC-0.8 0.55 Limits Typ. Max. VCC+0.3 VCC+0.3 Unit
RESET, CLKE, CLK/
Supply current write send modes) Supply current static mode) Input capacitance
Notes current that flows into defined positive (unsigned). typical values VCC=5V Ta=25°C.
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LINE SCAN BUFFER with 16-BIT COMPATIBLE INPUTS
TIMING REQUIREMENTS (Ta=0~70°C, VCC=5V±10%, GND=0V unless otherwise noted)
Symbol tC(I)/(CI) tW±(I)/(CI) tSU(CE-CI) th(CI-CE) tW(W) tSU(D-W) th(W-D) tSU(A-W) th(W-A) tSU(DAC-W) th(W-DAC) trec(W) trec(W-CI) trec(CI-W) tW(R) trec(R-W) tW(T) trec(CI-T) trec(T-CI) trec(W-T) trec(T-W) Parameter Clock cycle time Clock pulse width Clock enable setup time before clock Clock enable hold time after clock Write cycle time Write pulse width Data setup time before rising edge write signal Data hold time after rising edge write signal Address setup time before falling edge write signal Address hold time after rising edge write signal acknowledge input setup time before falling edge write signal acknowledge input hold time after rising edge write signal Write recovery time Clock recovery time after rising edge write signal Write recovery time after falling edge clock Reset pulse width Write recovery time after reset Mode inversion pulse width Mode inversion recovery time after falling edge clock Clock recovery time after rising edge mode inversion Mode inversion recovery time after rising edge write signal Write recovery time after rising edge mode inversion Test condition Min. Limits Typ. Max. Unit
Note delay clock input (CLK/ rise time (tr) fall time (tf) cause erroneous operation. 20ns less recommended.
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LINE SCAN BUFFER with 16-BIT COMPATIBLE INPUTS
SWITCHING CHARACTERISTICS (Ta=0~70°C, VCC=5V±10%)
Symbol tPLH(CI-DO) Propagation time between clock DATA tPHL(CI-DO) tPLH(CI-CO) tPHL(CI-CO) tPHL(CI-INT) tPLH(CI-BUS) tPLH(I-DO) Propagation time between clock DATA tPHL(I-DO) tPLH(I-O) Propagation time between clock CLK/ tPHL(I-O) tPHL(I-INT) tPLH(I-BUS) tPLH(W-DO) Propagation time between write DATA tPHL(W-DO) tPLH(W-INT) tPHL(W-BUS) tPHL(W-DRE) Propagation time between write DREQ tPLH(W-DRE) tPLH(T-DO) tPLH(T-INT) tPHL(T-BUS) tPHL(T-DRE) Propagation time between mode inversion DATA Propagation time between mode inversion INTR Propagation time between mode inversion BUSY/ORDY Propagation time between mode inversion DREQ CL=50pF CL=150pF CL=50pF CL=50pF CL=50pF CL=50pF Propagation time between write INTR Propagation time between clock INTR Propagation time between clock INTR Parameter CL=50pF CL=150pF CL=50pF CL=150pF CL=50pF CL=150pF CL=50pF CL=150pF CL=50pF Test condition Min. Limits Typ. Max. Unit
Propagation time between clock CLK/
Propagation time between clock BUSY/ORDY CL=50pF CL=50pF CL=150pF CL=50pF CL=150pF CL=50pF CL=150pF CL=50pF CL=150pF CL=50pF
Propagation time between clock BUSY/ORDY CL=50pF CL=50pF CL=150pF CL=50pF CL=150pF CL=50pF
Propagation time between write BUSY/ORDY CL=50pF
Note test waveform Input pulse level Input pulse rise time Input pulse fall time Reference voltage Input voltage Output voltage
0~3V 1.3V 1.3V
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LINE SCAN BUFFER with 16-BIT COMPATIBLE INPUTS
TIMING DIAGRAMS Write Timing
Storing commands data from
tsu(A-W) th(W-A)
tsu(A-W) tW(W)
th(W-A)
D0~D15 tsu(D-W) th(W-D)
Storing data from DMAC
DACK tsu(DAC-W) tW(W) th(W-DAC)
D0~D15 tsu(D-W) Write recovery time th(W-D)
trec(W)
Output timing during write
Write mode Number transfer words
DREQ tPHL(W-DRE) DATA Fixed data tPHL(W-DO), tPLH(W-DO) tPLH(W-DRE)
Note above shows timing when DREQ mode flag initialization number transfer words set. When DREQ mode flag set, DREQ tied High.
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LINE SCAN BUFFER with 16-BIT COMPATIBLE INPUTS
Send Timing
Clock input:
Send mode tC(CI) trec(W-CI) tW+(CI) tW-(CI) tPHL(CI-CO) DATA Fixed data tPLH, tPHL(CI-DO) BUSY/ORDY tPHL(W-BUS) INTR tPHL(CI-INT) tPLH(CI-BUS) tPLH(CI-CO) Fixed data trec(CI-W)
Write mode
tPLH(W-INT)
Send mode trec(W-CI) tsu(CE-CI) CLKE th(CI-CE) tsu(CE-CI) th(CI-CE)
Write mode
trec(CI-W)
DATA Fixed data Fixed data
Clock input
Send mode tW+( tPHL( DATA Fixed data tPLH,tPHL( I-DO) BUSY/ORDY INTR tPHL(W-BUS) tPLH( I-BUS) tPLH( Fixed data tW-( Write mode
tPHL( I-INT)
tPLH(W-INT)
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Reset Timing
tW(R)
RESET
trec(R-W)
Timing when using extended toggle
Write mode setting
tW(T)
tPLH(T-DO), tPHL(T-DO) DATA Fixed data
trec(T-W)
DREQ
tPHL(T-DRE)
INTR
tPLH(T-INT)
Send mode setting
tW(T)
trec(W-T) trec(T-CI)
BUSY/ORDY
tPHL(T-BUS)
tW(T) trec(CI-T) th(CI-CE) trec(T-CI) tsu(CE-CI)
CLKE
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Application Examples Connection diagram
Connection example memory data transfer
Control signal
Address
Data
Image memory memory management unit
M66307
D0~D15 DACK DREQ INTR
N.C.
Connection example transfer
Decoder
Control signal
Address
Data
Image memory memory management unit
Decoder
DMAC DACK DREQ
M66307
D0~D15 DACK DREQ INTR
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Connection diagram when using extended toggle
Toggle configuration (When using data request clock (CLK peripheral equipment side)
DACK RESET
D0~D15 D8~D15
(Slave)
D0~D7 DACK DREQ
D8~D15
(Master)
D0~D7 DACK DREQ CLKE ORDY CLK/ DATA
INTR CLKE
INTR CLKE
INTR DREQ
Fig. Wiring diagram toggle configuration Toggle configuration (when using continuous clock from system side)
DACK RESET D0~D15 D8~D15
(Slave)
chip
D0~D7 DACK DREQ
D8~D15
(Master)
D0~D7 DACK DREQ CLK/ DATA
INTR CLKE
INTR CLKE
INTR ORDY DREQ
Fig. Wiring diagram toggle configuration
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Toggle Operation Flowchart
Reset Master Initial setting DREQ words, fixed beginning data length, output format set. Toggle input mode inversion command set. Data from data stored. Write mode
mode Slave
Static mode
Static mode
Refer Common instructions (iv), given below.
Toggle input mode inversion command set. Data from data stored, data output. Toggle input mode inversion command set. Data from data stored, data output. Toggle input mode inversion command set. Send mode
Write mode
Write mode
Send mode
Toggle Operation Instructions Common instructions operation mode using mode inversion command toggle input (TOG). (ii) When setting operation mode with toggle input (TOG) DREQ mode (flag one-line fixed data setting command. (iii) settings master slave determined during initial setting. When flag M66307 Slave M66307 Master (iv) After reset first mode setting, slave send mode. However, transmission impossible because there data line memory. data written this stage. impossible control mode inversion using operation mode setting command extended toggle input (TOG) together.
When used: Toggle operation feasible when circuit connected shown Fig. When used: Toggle operation feasible when circuit connected shown Fig. (ii) initial setting, clock input cannot selected. (iii) Divider clock output feasible.
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3.Connection diagram when using extended 32-bit
32-bit configuration (when using data request clock (CLK peripheral equipment side)
DACK RESET D16~D31 D0~D15 D8~D15
(Slave)
D0~D7 DACK DREQ
D8~D15
(Master)
D0~D7 DACK DREQ CLKE ORDY CLK/ DATA
INTR CLKE INTR DREQ BUSY
INTR CLKE
Fig. Wiring diagram 32-bit configuration 32-bit configuration (when using continuous clock from system side)
DACK RESET D16~D31 D0~D15 D8~D15
(Slave)
chip
D0~D7 DACK DREQ
D8~D15
(Master)
D0~D7 DACK DREQ CLK/ DATA
INTR CLKE INTR DREQ BUSY
INTR CLKE
ORDY
Fig. Wiring diagram 32-bit configuration
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LINE SCAN BUFFER with 16-BIT COMPATIBLE INPUTS
32-bit Operation Flowchart
mode Master Initial setting DREQ words, fixed beginning data length, output format set. Slave
Reset
Static mode
Static mode
Write mode set.
Data from data stored.
Write mode
Write mode
Send mode set.
Data output data bus.
Send mode
Send mode
Write mode set.
Data from data stored.
Write mode
Write mode
Send mode set.
32-bit Operation Instructions Common instructions Store same value both master slave (ii) settings master slave determined during initial setting. When flag M66307 Slave M66307 Master (iii) upper bits sent master lower bits sent slave that transmits data first determined which FIFO LIFO output setting command set. When 32-bit parallel data stored three times, serial output data transmitted, shown table, according output format determined output setting command.
used: Thirty-two-bit operation feasible when circuit connected shown Fig. When used: Thirty-two-bit operation feasible when circuit used shown Fig. (ii) initial setting, clock input cannot used. (iii) Divider clock output feasible. Output format FIFO LIFO Serial output data D0(1)~D31(1), D0(2)~D31(2), D0(3)~D31(3) D0(3)~D31(3), D0(2)~D31(2), D0(1)~D31(1)
D31(1)~D0(1), D31(2)~D0(2), D31(3)~D0(3) D31(3)~D0(3), D31(2)~D0(2), D31(1)~D0(1)
D0(n) D31(n): 32-bit parallel data stored n-th position.

LINE SCAN BUFFER with 16BIT COMPATIBLE INPUTS LINE SCAN BUFFER with 16

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