MAX1127 Evaluation MAX1127 evaluation kit) fully assembled tested

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MAX1127 Evaluation MAX1127 evaluation kit) fully assembled tested

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19-3398; 7/04
MAX1127 Evaluation
MAX1127 evaluation kit) fully assembled tested circuit board that contains components necessary evaluate performance MAX1126/MAX1127 quad 12-bit analog-to-digital converter (ADC). MAX1126/MAX1127 accept differential analog input signals. generates these signals from user-provided single-ended input sources. digital outputs produced easily sampled with user-provided, high-speed logic analyzer data-acquisition system. also features on-board deserializer ease integration with standard logic analysis systems. operates from 1.8V 3.3V power supplies (1.5V optional FPGA) includes circuitry that generates clock signal from signal provided user. comes with MAX1127 installed. Order free samples pin-compatible MAX1126 evaluate this part. Low-Voltage Power Operation Optional On-Board Clock-Shaping Circuitry Serial SLVS/LVDS Outputs On-Board LVPECL Differential Output Drivers On-Board Deserializer LVDS Test Mode Assembled Tested Also Evaluates MAX1126
Features
Sample Rate 65Msps (MAX1127)
Evaluates: MAX1126/MAX1127
Part Selection Table
PART MAX1126EGK MAX1127EGK SPEED (Msps) PART MAX1127EVKIT
Ordering Information
TEMP RANGE +70°C PACKAGE
Note: evaluate MAX1126, request free MAX1126EGK sample with MAX1127EVKIT.
Component Suppliers
SUPPLIER Central Semiconductor Diodes Panasonic Vishay/Vitramon Zetex PHONE 843-946-0238 631-435-1110 805-446-4800 714-373-7366 847-803-6100 203-268-6261 631-543-7100 843-626-3123 631-435-1824 805-446-4850 714-737-7323 847-390-4405 203-452-5670 631-864-7630 WEBSITE www.avxcorp.com www.centralsemi.com www.diodes.com www.panasonic.com www.component.tdk.com www.vishay.com www.zetex.com
Note: Indicate that using MAX1127 when contacting these component suppliers.
Maxim Integrated Products
pricing, delivery, ordering information, please contact Maxim/Dallas Direct! 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
MAX1127 Evaluation Evaluates: MAX1126/MAX1127
Component List
DESIGNATION C1-C12, C59-C64, C81-C85 C13-C20 C21-C28 DESCRIPTION 0.1µF ±20%, ceramic capacitors (0402) C1005X5R1A104M installed (0603) 39pF ±5%, ceramic capacitors (0402) C1005C0G1H390J 1.0µF ±20%, 6.3V ceramic capacitors (0402) C1005X5R0J105M 220µF ±20%, 6.3V tantalum capacitors case) TPSC227M006R0250 installed case) 10µF ±20%, ceramic capacitors (1210) C3225X5R1A106M 2.2µF ±20%, 6.3V ceramic capacitor (0603) C1608X5R0J225M 0.01µF ±5%, ceramic capacitors (0603) C1608C0G1E103J 0.1µF ±20%, 6.3V ceramic capacitors (0201) C0603X5R0J104M Dual Schottky diode (SOT23) Zetex BAS70-04 Central Semiconductor CMPD6263S Vishay BAS70-04 Diodes BAS70-04 Green surface-mount LEDs (SS) Panasonic LNJ308G8LRA PC-mount connectors Dual row, 40-pin headers 2-pin headers installed None None DESIGNATION JU1-JU9, JU11, JU12, JU15- JU18 JU10 JU13 DESCRIPTION Jumper, 3-pin headers installed (SIP-3) Jumper, dual row, 8-pin header Digital logic n-channel MOSFET (SOT23), mark Central Semiconductor 2N7002
C29-C44, C77-C80, C92, C45, C46, C47, C55, C86-C89 C48, C49, C50, C51, C52, C53, C57, C90,
R1-R16, R22-R25, R82-R93 R17-R21, R58-R75 R26-R36, R76-R81 R37-R44 R45-R50 R52, R53, R94, R96, T1-T4 TP1-TP9 TP10-TP12 U3-U8
installed (0603)
49.9 resistors (0603) installed (0402) resistors (0402) resistors (0603) 100k potentiometer, turn, 3/8in 4.02k resistors (0603) potentiometer, turn, 3/8in resistor (0603) 13.0k resistor (0603) 4.7k resistors (0603) resistors (1206) resistor (0603) Momentary pushbutton switch 800MHz transformers Mini-Circuits ADT1-1WT Test points (black) installed Maxim MAX1127EGK (68-pin QFN) Maxim MAX9111ESA (8-pin Maxim MAX9375EUA (8-pin µMAX) Xilinx XC2V80-5FG256C (FGBGA-256) Xilinx XC2V80-5FG256I (FGBGA-256) Xilinx XC18V01SO20C (20-pin Shunts MAX1127 board
C58, C65-C76
C94-C121
J1-J5 J12-J15 J8-J11
MAX1127 Evaluation
Quick Start
Recommended Equipment
power supplies: Clock (CVDD) Analog (AVDD) Digital (OVDD) Buffers (VPECL) Optional Deserializer core (VD1.5) 1.5V, 200mA Deserializer (VD3.3) 3.3V, 200mA Signal generator with low-phase noise jitter clock input signal (e.g., 8662A, 8644B) Four signal generators analog signal inputs (e.g., 8662A, 8644B) Logic analyzer data-acquisition system (e.g., 16500C, TLA621) Analog bandpass filters (e.g., Allen Avionics, Microwave) input signal clock signal Digital voltmeter 1.8V, 100mA 1.8V, 500mA 1.8V, 150mA 3.3V, 350mA Connect output analog bandpass filters connectors labeled analog input signals also monitored J8-J11. Note: four channels operated independently simultaneously. Connect logic analyzer either header (SLVS- LVDS-compatible signals), J12-J15 (deserialized 3.3V CMOS-compatible signals). Output Locations section header connections. Connect 1.8V, 500mA power supply AVDD. Connect ground terminal this supply GND. Connect 1.8V, 150mA power supply OVDD. Connect ground terminal this supply GND. Connect 1.8V, 100mA power supply CVDD. Connect ground terminal this supply GND. Note: When using MAX9111, CVDD must 3.3V Connect 3.3V, 350mA power supply VPECL. Connect ground terminal this supply GND. Connect 1.5V, 200mA power supply VD1.5. Connect ground terminal this supply GND. Connect 3.3V, 200mA power supply VD3.3. Connect ground terminal this supply GND. Turn power supplies. Enable signal generators. clock signal generator output 48.75MHz 65MHz signal, with amplitude 2.6VP-P higher. analog input signal generators output desired frequency with amplitude 1VP-P. signal generators should phase locked. Enable logic analyzer. Collect data using logic analyzer.
Evaluates: MAX1126/MAX1127
Procedure
MAX1127 fully assembled tested surface-mount board. Follow steps below verify board operation. turn power supplies enable signal generators until connections completed: Verify that shunts installed following locations: JU1-JU5 (1-2) channels enabled (2-3) Single termination (2-3) LVDS outputs (2-3) Two's-complement output (2-3) Normal operation JU10, JU11, JU12 (2-3) 48.75MHz 65MHz clock frequency range JU13 (3-4) Internal reference enabled JU15-JU18 (2-3) Deserializer outputs enabled Connect clock signal generator input clock bandpass filter. Connect output clock bandpass filter connector labeled Connect analog input signal generators inputs desired analog bandpass filters.
Detailed Description
MAX1127 fully assembled tested circuit board that contains components necessary evaluate performance MAX1126 (40Msps) MAX1127 (65Msps), 12-bit serial SLVS/LVDS output ADCs. comes with MAX1127, which evaluated with maximum clock frequency (fCLK) 65MHz. MAX1127 accepts differential input signals; however, on-board transformers (T1-T4) convert readily available single-ended source output required differential signal. input signals MAX1127 measured using differential oscilloscope probe headers J8-J11.
MAX1127 Evaluation Evaluates: MAX1126/MAX1127
Output level translators (U3-U8) buffer convert SLVS/LVDS output signals MAX1127 higher voltage LVPECL signals that captured wide variety logic analyzers. SLVS/LVDS outputs accessible header LVPECL outputs accessible header designed four-layer board optimize performance MAX1127. Separate analog, digital, clock, buffer power planes minimize noise coupling between analog digital signals; coplanar transmission lines used analog clock inputs differential coplanar transmission lines used digital LVDS outputs. differential outputs properly terminated with termination resistors between true complementary digital outputs. trace lengths differential SLVS/LVDS lines matched within thousandths inch minimize layout-dependent data skew. control power-management features data converter. Table shunt positions.
Clock
default, MAX1127 directly connects user-provided AC-coupled clock signal MAX1127 clock input. this mode, diode limits amplitude clock signal. Overdriving clock input (J5) increase slew rate differential signal, thereby reducing clock jitter. MAX1127 also features optional on-board clock-shaping circuit that generates clock signal with variable duty cycle from AC-coupled sine-wave signal applied clock connector (J5). this circuitry, trace printed circuit (PC) board install resistors R35. frequency signal should exceed 65MHz MAX1127. sinusoidal input signal frequency (fCLK) determines sampling rate ADC. Optional Clock-Shaping Circuit differential line receiver (U2) processes clockinput signal generates required CMOS clock signal. When using this circuitry, voltage CVDD must least 3.3V signal's duty cycle adjusted with potentiometer R54. With 3.3V clock supply voltage (CVDD), clock signal with duty cycle (recommended) achieved adjusting until voltage 1.32V produced across test points TP7. clock signal observed TP8. Frequency-Mode Selection When driving MAX1127 with anything other than default 65MHz clock signal, phased-
Power Supplies
best performance, MAX1127 requires separate analog, digital, clock, buffer power supplies. 1.8V power supplies used power analog digital portion MAX1127. clock circuitry powered 1.8V power supply using MAX9111, Optional Clock-Shaping Circuit section). separate 3.3V power supply used power output buffers (U3-U8) kit. MAX1127 Power-Down MAX1127 features several power-management features. addition global device power-down pin, MAX1127 offers independent power-down each channel ADC. Jumpers JU1-JU5
Table Power-Down Shunt Settings (JU1-JU5)
JUMPER (PD0) (PD1) (PD2) (PD3) SHUNT POSITION 2-3* 2-3* 2-3* 2-3* POWER-DOWN CONNECTIONS AVDD AVDD AVDD AVDD AVDD CHANNEL CHANNELS DESCRIPTION Channel disabled Channel enabled Channel disabled Channel enabled Channel disabled Channel enabled Channel disabled Channel enabled channels disabled channels enabled
(PDALL) 2-3* *Default configuration: JU1-JU5 (2-3).
MAX1127 Evaluation
locked-loop (PLL) circuit MAX1127 must accordingly. Refer MAX1127 data sheet further details about operation internal PLL. Jumpers JU10, JU11, JU12 control mode MAX1127. Table shunt positions. Ensure that desired clock frequency falls between min/max limits Table data synchronization. Refer MAX1127 data sheet more details. Output Format digital output coding chosen either two's complement straight offset binary configuring jumper JU3. Table jumper configuration.
Evaluates: MAX1126/MAX1127
Table Shunt Settings (JU10-JU12)
JUMPER JU11 2-3* SHUNT POSITION JU12 2-3* INPUT CLOCK RANGE (MHz) 48.750 32.500 24.375 16.000 65.000 48.750 32.500 24.375
Table Output Format Shunt Settings (JU8)
SHUNT POSITION 1-2* DESCRIPTION Straight offset binary selected. Digital output straight offset binary format. Two's complement selected. Digital output two's complement format.
AVDD
*Default configuration: JU10, JU11, JU12 (2-3).
Input Signal
Although MAX1127 accepts differential analog input signals, only requires single-ended analog input signal, with amplitude less than 1.4VP-P provided user. On-board transformers (T1-T4) convert single-ended analog input signal generate differential analog signals ADC's differential input pins.
*Default configuration: (1-2).
Reference Voltage
MAX1127 configured MAX1127's internal reference, stable, low-noise, external reference. jumper JU13 configure desired reference mode. Table shunt settings.
Double-Termination Settings MAX1127 features trimmed, internal termination resistors between positive (true) negative (complementary) line each output (D0-D3, CLK, FRAME). jumper switch resistors into circuit (double termination), switch resistors circuit (single termination). Table shunt positions.
Table Double Termination Shunt Settings (JU6)
SHUNT POSITION 2-3* AVDD DESCRIPTION Double termination selected. Outputs double terminated. Single termination selected. Outputs single terminated.
Table Reference Shunt Settings (JU13)
SHUNT POSITION 3-4* DESCRIPTION Internal reference disabled. Apply external reference voltage REFIO pad. Internal reference enabled. RESERVED. USE.
*Default configuration: (2-3).
*Default configuration: JU13 (3-4).
Output Signal
MAX1127 features four, serial, LVDS-compatible, digital outputs. Each output transmits converted analog input signals channels through additional outputs (CLKOUT FRAME) provided
SLVS Outputs MAX1127 capable generating low-voltage differential signaling (LVDS) scalable low-voltage signaling (SLVS) signals outputs. Jumper controls this feature MAX1127. Table shunt positions. Regardless which output signal type selected, output buffers (U3-U8) will convert data LVPECL logic levels.
MAX1127 Evaluation Evaluates: MAX1126/MAX1127
Table SLVS Shunt Settings (JU7)
SHUNT POSITION 2-3* SLVS/LVDS AVDD DESCRIPTION SLVS outputs LVDS outputs
*Default configuration: (2-3).
LVDS Test Pattern debug signal integrity problems, MAX1127 generate factory-default test pattern SLVS/LVDS output channels. Jumper controls this feature. Table shunt positions.
Output Locations digital outputs MAX1127 connected 40-pin header (J6). board trace length matched minimize data skew improve overall dynamic performance device. Additionally, drivers (U3-U8) buffer level translate digital outputs LVPECL-compatible signals. drivers increase differential voltage swing, able drive large capacitive loads, which present logic analyzer connection. outputs buffers connected 40-pin header (J7). Table location headers J6-J7.
On-Board Deserializer
MAX1127 features on-board deserializer that converts serial outputs MAX1127 parallel data stream. deserializer uses delaylocked loop (DLL) synchronize itself with incoming serial data stream. After every change clock frequency, reset pressing SW1. lit, serial data stream synchronized output deserializer valid.
Table LVDS Test Pattern Shunt Settings (JU9)
SHUNT POSITION 2-3* LVDSTEST AVDD DESCRIPTION Test pattern (0000 1011 1101) transmitted, first, SLVS/LVDS outputs Normal operation
*Default configuration: (2-3).
Table Output Locations
SIGNAL CLKOUT FRAME UNBUFFERED (LVDS SLVS) J6-5 J6-6 J6-11 J6-12 J6-17 J6-18 J6-23 J6-24 J6-29 J6-30 J6-35 J6-36 BUFFERED (LVPECL) J7-5 J7-6 J7-11 J7-12 J7-17 J7-18 J7-23 J7-24 J7-29 J7-30 J7-35 J7-36 DESCRIPTION Channel Channel Clock Frame Channel Channel
True Complementary
MAX1127 Evaluation
Channel through channel data captured headers through J15. Table locations. Deserializer Output Enables Jumpers JU15-JU18 control respective CH0-CH3 output enables deserializer. Table shunt positions.
Evaluates: MAX1126/MAX1127
Table Output Locations (J12-J15)
POSITION J12-38 J12-26 J12-24 J12-22 J12-20 J12-18 J12-16 J12-14 J12-12 J12-10 J12-8 J12-6 J12-4 J13-38 J13-26 J13-24 J13-22 J13-20 J13-18 J13-16 J13-14 J13-12 J13-10 J13-8 J13-6 J13-4 J14-38 J14-26 J14-24 J14-22 J14-20 J14-18 J14-16 J14-14 J14-12 J14-10 J14-8 J14-6 J14-4 J15-38 J15-26 J15-24 J15-22 J15-20 J15-18 J15-16 J15-14 J15-12 J15-10 J15-8 J15-6 J15-4
Evaluating MAX1126
MAX1127 also used verify MAX1126 performance. evaluate MAX1126, replace MAX1127 with free MAX1126EGK sample.
Table Deserializer Output Enables (JU15-JU18)
SHUNT POSITION 2-3* DESCRIPTION Deserializer output disabled Deserializer output enabled
*Default configuration: JU15-JU18 (2-3).
Note: Odd-numbered pins connected ground. Remaining pins Connects.
MAX1127 Evaluation Evaluates: MAX1126/MAX1127
AVDD
AVDD CVDD OVDD
AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD CVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD AVDD OUTON 0.1µF 49.9 OPEN SHORT SHORT 39pF OUT1N 0.1µF SHORT 39pF CLKOUTP IN0N CLKOUTN FRAMEP IN1P FRAMEN OPEN 0.1µF OUT2P SHORT 39pF OUT2N OUT3P IN2P OUT3N OPEN 0.1µF SHORT 39pF SHORT 39pF SHORT 39pF IN3N I.C. PDALL AVDD PLL3 JU12 PLL2 AVDD AVDD REFIO 0.1µF INTREF 13.0k 100k LVDSTEST PLL0 SLVS/LVDS PLL1 JU10 SHORT PINS TRACE) SHORT JU13-5JU13-6 JU13-7JU13-8 AVDD JU11 AVDD REFADJ JU13 JU13-1JU13-2 REFADJ JU13-3JU13-4 AVDD IN2N IN3P AVDD AVDD AVDD 0.1µF AVDD SHORT AVDD OPEN 0.01µF N.C. IN1N N.C. IN1P N.C. 0.1µF 0.1µF 4.02k OPEN OUT1P IN0P VPECL AVDD AVDD 220µF 6.3V OPEN 10µF 1.0µF CVDD CVDD 220µF 6.3V OPEN 10µF 1.0µF OVDD 1.0µF 1.0µF 1.0µF 1.0µF 1.0µF 1.0µF 1.0µF CVDD 1.0µF 1.0µF 1.0µF 1.0µF 1.0µF 1.0µF 1.0µF 1.0µF 1.0µF
OUT0P
OPEN
OPEN
SHORT
OPEN
SHORT SHORT
VPECL 220µF 6.3V OPEN 10µF 1.0µF
OVDD
OVDD 220µF 6.3V OPEN 10µF 1.0µF
0.1µF 49.9
OPEN
SHORT 39pF
OPEN
OPEN
SHORT
IN1N
CVDD
2.2µF
SHORT SHORT
MAX1127
CVDD
CVDD
0.1µF 49.9
OPEN
SHORT 39pF
OPEN
OPEN
CVDD 4.02k 4.02k
SHORT
MAX9111
0.1µF 49.9
SHORT SHORT
0.1µF 49.9
OPEN
OPEN
OPEN
SHORT
OPEN
SHORT
AVDD AVDD
SHORT
SHORT
Figure MAX1127 Schematic (Sheet
VPECL 0.1µF
VPECL 0.1µF
VPECL 0.1µF
49.9 49.9 49.9
0.01µF BD0P BD1P BD2P
0.01µF
0.01µF
BD0N BD1N BD2N
MAX9375
49.9 49.9 0.01µF 49.9 49.9
MAX9375
MAX9375
49.9 49.9 0.01µF
0.01µF
Figure MAX1127 Schematic (Sheet
VPECL 0.1µF VPECL 0.1µF VPECL 0.1µF 49.9 49.9 0.01µF BD3P BCKP 0.01µF 0.01µF BFMP
BD3N BCKN
MAX9375
49.9 49.9 0.01µF
MAX9375
49.9
MAX9375
49.9 49.9 0.01µF
49.9
49.9
0.01µF
BFMN
J6-1 J6-3 J6-5 BDOP
J6-2 J6-4 J6-6
J7-1 J7-3 J7-5
J7-2 J7-4 J7-6
BDON
BD1P
BD1N
BCKP
BCKN
BFMP
BFMN
BD2P
BD2N
J6-37 J6-39 J6-38 J6-40
J6-7 J6-9 J6-11 J6-13 J6-15 J6-17 J6-19 J6-21 J6-23 J6-25 J6-27 J6-29 J6-31 J6-33 J6-35 BD3P
J6-8 J6-10 J6-12 J6-14 J6-16 J6-18 J6-20 J6-22 J6-24 J6-26 J6-28 J6-30 J6-32 J6-34 J6-36
J7-7 J7-9 J7-11 J7-13 J7-15 J7-17 J7-19 J7-21 J7-23 J7-25 J7-27 J7-29 J7-31 J7-33 J7-35 J7-37 J7-39
J7-8 J7-10 J7-12 J7-14 J7-16 J7-18 J7-20 J7-22 J7-24 J7-26 J7-28 J7-30 J7-32 J7-34 J7-36 J7-38 J7-40
Evaluates: MAX1126/MAX1127
BD3N
MAX1127 Evaluation
Evaluates: MAX1126/MAX1127
MAX1127 Evaluation
Figure MAX1127 Schematic (Sheet
VD3.3 JU15 U9-D L96P_7 L96N_7 L94P_7 L94P_6 L91P_6 LO6P_6 LO6P_3 L91P_3 L94P_3 L94P_2 L96N_2 L96P_2 N.C. N.C. N.C. L91N_7 CLKDES XC2V80-5FG256C L94N_7 L95N_5/GCLK5S LO3N_5/D4/AVP5 LO2P_5/D7 LO2P_3/VRN_3 LO2P_6/VRN_6 LO3N_3/VREF_3 LO3N_6/VREF_6 L91N_3 L91N_6 L96P_3 L94N_3 N.C. N.C. N.C. N.C. CLKDES XC2V80-5FG256C U9-C L96N_6 LO2N_0 L93P_6 L95P_4/GCLK2P LO6N_6 L94N_2 LO3P_8 LO4N_2 LO3_5/D5/AVN5 L93N_2 L95P_5/GLCK4P L91P_2 L95N_4/GCLK3S L91N_2 LO3N_4/D2/AVP4 L93P_7/VREF_7 LO3P_3 LO6P_2 LO6N_3 LO6N_2 L93P_3 N.C. L96N_3 N.C. N.C. N.C. N.C. N.C. N.C. N.C. L91P_7 N.C. J15-1 J15-3 J15-5 J15-7 J15-9 J15-11 J15-13 J15-15 J15-17 J15-19 J15-21 J15-23 J15-25 J15-27 J15-29 J15-31 J15-33 J15-35 J15-37 J15-39 J15-2 J15-4 J15-6 J15-8 J15-10 J15-12 J15-14 J15-16 J15-18 J15-20 J15-22 J15-24 J15-26 J15-28 J15-30 J15-32 J15-34 J15-36 J15-38 J15-40 U9-A LO4N_6 LO2N_7/VRP_ LO1N_6 L96P_ LO1P_6 L94N_ LO1P_5/CS LO2N_ LO1N_5/RDWR L95N_1/GCLK1P L94N_5 L95P_0/GCLK6S L96N_5/GCLK7S LO3P_4/D3/AVN4 L96P_4/GCLKOP LO2P_0 L94P_4 N.C. LO1P_3 N.C. LO1N_3 N.C. LO4N_3 N.C. N.C. N.C. N.C. N.C. N.C. N.C. L93P_2/VREF_2 N.C. CLKDES XC2V80-5FG256C CLKDES XC2V80-5FG256C J13-1 J13-3 J13-5 J13-7 J13-9 J13-11 J13-13 J13-15 J13-17 J13-19 J13-21 J13-23 J13-25 J13-27 J13-29 J13-31 J13-33 J13-35 J13-37 J13-39 J13-2 J13-4 J13-6 J13-8 J13-10 J13-12 J13-14 J13-16 J13-18 J13-20 J13-22 J13-24 J13-26 J13-28 J13-30 J13-32 J13-34 J13-36 J13-38 J13-40 J14-1 J14-3 J14-5 J14-7 J14-9 J14-11 J14-13 J14-15 J14-17 J14-19 J14-21 J14-23 J14-25 J14-27 J14-29 J14-31 J14-33 J14-35 J14-37 J14-39 J14-2 J14-4 J14-6 J14-8 J14-10 J14-12 J14-14 J14-16 J14-18 J14-20 J14-22 J14-24 J14-26 J14-28 J14-30 J14-32 J14-34 J14-36 J14-38 J14-40 U9-B L93N_6/VREF_6 LO2P_7/VRN_7 L04P_6 LO3P_2/VREF_2 LO2N_6/VRP_6 LO3N_2 LO2N_5/D6 N.C. L94_5/VREF_5 N.C. L96P_5/GCLK6P N.C. L96N_4/GCLK1S N.C. L94N_4/VREF_4 LO2P_2/VRN_2 LO2P_4/D1 LO2N_2/VRP_2 LO2N_3/VRP_3 LO2P_1 LO4P_3 L95P_1/GCLK0S L93N_3/VREF_3 L95N_O/GCLK7P N.C. N.C. N.C. N.C. N.C. N.C. L93N_7 N.C. JU16 JU17 JU18 VD3.3 VD3.3 VD3.3 SHORT U9-H LO1P_0 SHORT BD3P LO1N_7 BD3N SHORT SHORT SHORT SHORT L96N_0/GLCK5P N.C. SHORT L96P_1/GLCK2S N.C. SHORT LO1P_1 BD0P SHORT BD0N L96N_1/GCLK3P L94P_1/VREF_1 L94N_1 LO3P_1/VRN_1 LO3N_1/VRP_1 SHORT N.C. N.C. N.C. N.C. N.C. LO1N_2 LO1P_7 LO1N_0 N.C. LO3P_0/VRN_0 N.C. LO3N_0/VRP_0 N.C. L94P_0 N.C. L94N_0/VREF_0 L96_0/GLCK4S N.C. SHORT SHORT LO1N_1 XC2V80-5FG256C LO1P_2
J12-1 J12-3 J12-5 J12-7 J12-9 J12-11 J12-13 J12-15 J12-17 J12-19 J12-21 J12-23 J12-25 J12-27 J12-29 J12-31 J12-33 J12-35 J12-37 J12-39
J12-2 J12-4 J12-6 J12-8 J12-10 J12-12 J12-14 J12-16 J12-18 J12-20 J12-22 J12-24 J12-26 J12-28 J12-30 J12-32 J12-34 J12-36 J12-38 J12-40
BD2P
BD2N
BFMP
BFMN
BCKP
BCKN
BD1P
BD1N
MAX1127 Evaluation Evaluates: MAX1126/MAX1127
VD3.3
VD3.3
VCCO D4/CF VD3.3 JU16-4 JU16-8 TDI-FPGA JU16-9 CCLK DONE VD3.3 JU16-5 4.7k INIT JU16-6 JU16-7 4.7k PROGRAM JU16-3 VD3.3 VD3.3 JU16 JU16-1 JU16-2
XC18V01S020
OE/RESET
VD3.3
VD1.5
VD3.3
U9-E XC2V80-5FG256C
U9-F XC2V80-5FG256C
VCC0_0 VCC0_0 VCC0_0 VCC0_1 VCC0_1 VCC0_1 VCC0_2 VCC0_2 VCC0_2 VCC0_3 VCC0_3 VCC0_3 VCC0_4 VCC0_4 VCC0_4 VCC0_5 VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT
VD3.3
DONE PROGRAM CCLK TDI-FPGA INIT
U9-G XC2V80-5FG256C
LO2N_4/DO/DIN VCCAUX DONE PROG CCLK LO1P_4/INIT VCCAUX VCCAUX VCCAUX LO4P_2 LO6N_7
TP12 VD3.3 TP11 TP10
LO6P_7 LO3N_7
VCCO_7 VCCO_7 VCCO_7 VCCO_6 VCCO_6 VCCO_6 VCCO_5 VCCO_5 SHORT
LO1N_4/BY/ DOUT RSVD SHORT SHORT RSVD RSVD
LO3P_7/ VREF_7 LO4N_7 LO4P_7 N.C. N.C. PWRDOWN HSWAP_EN VBATT
VD3.3
VD3.3 220µF 6.3V 220µF 6.3V 10µF 1.0µF
VD3.3 C118 0.1µF C119 0.1µF C120 0.1µF C121 0.1µF
VD1.5 C110 0.1µF C111 0.1µF C112 0.1µF C113 0.1µF C114 0.1µF C115 0.1µF C116 0.1µF C117 0.1µF
VD3.3 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF
VD1.5
VD1.5 220µF 6.3V 220µF 6.3V 10µF 1.0µF
VD3.3 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF C100 0.1µF C101 0.1µF C102 0.1µF C103 0.1µF C104 0.1µF C105 0.1µF C106 0.1µF C107 0.1µF C108 0.1µF C109 0.1µF
Figure MAX1127 Schematic (Sheet
MAX1127 Evaluation Evaluates: MAX1126/MAX1127
Figure MAX1127 Component Placement Guide-Component Side
Figure MAX1127 Board Layout-Component Side
MAX1127 Evaluation Evaluates: MAX1126/MAX1127
Figure MAX1127 Board Layout (Inner Layer 2)-Ground Planes
Figure MAX1127 Board Layout (Inner Layer 3)-Power Planes
MAX1127 Evaluation Evaluates: MAX1126/MAX1127
Figure MAX1127 Board Layout (Inner Layer 4)-Signal Layer
Figure MAX1127 Board Layout (Inner Layer 5)-Signal Layer
MAX1127 Evaluation Evaluates: MAX1126/MAX1127
Figure MAX1127 Board Layout-Solder Side
Figure MAX1127 Component Placement Guide-Solder Side
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 2004 Maxim Integrated Products Printed registered trademark Maxim Integrated Products.

MAX1127 Evaluation MAX1127 evaluation kit) fully assembled tested

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