KE5B256B1 64k-bit 3-port type Ver. 1.2.1 Table Contents
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ADDRESS PROCESSOR
KE5B256B1
64k-bit 3-port type
Ver. 1.2.1
Table Contents
Address Processor KE5B256B1
Features
Introduction Functional Overview Specifications Register Names
Port
Access Registers Basic Operation through Port Search Operation through Port Search Result Output from Port HHA/HEA Register Operation Automatic Increment Function Table Maintenance
Block Diagram Assignment Descriptions
Assignment Descriptions
Cascading
Device Registration Priority Cascade Connection Input Port Cascade System Output Port Cascade System Port Cascade System Characteristics Cascade System Single Device Operation
Port Operation Mode Overview
Port Overview Arbitration Operation Modes Overview External Arbitration
Table
Entry Segment Table Configuration Read/Write Segment Data Search Table
Initialization Examples Command Descriptions
Command Functions Conditions Executing Commands
Input Port
Input Port Configuration Sequence Configuration Selection Channel Start Sequence NumIP Sequence Operation Automatic Output
12.1 12.2
13.1 13.2 13.3 13.4
Register Descriptions
Overview Register Addresses Register Maps Conditions Accessing Registers
Output Port
Sequence Configuration Selection Channel Start Sequence NumOP Sequence Operation
14.1 14.2 14.3 14.4
Electrical Characteristics
Absolute Maximum Ratings Operating Range Characteristics Characteristics
Package Outline
Address Processor KE5B256B1
Features Introduction
KE5B256B1 256k-bit (Content Addressable Memory) device with architecture. main function fast searching data search data table stored CAM. User define row/column table size flexibility. width entry search data table selected from bits bits, increments bits segment). User define area searched entry freely terms position width. search operation executed each segment, cycle time 80ns with fast operation characteristic CAMs. KE5B256B1 provides ports, Input Port, Output Port Port. These ports designed have most appropriate functionality. Input Port, which only used inputting data, provides programmable input data formatter programmable sequencer. These capabilities enable formatting incoming data flexible search operation with table column pre-determined sequence writing into Input Port. Therefore, user execute complex search operations quickly. search results output flag register reading from Output Port Port. Output Port only used outputting search results. Like Input Port, programmable sequencer. Output Port output search results automatically according pre-determined sequence reading from Output Port. Port used definition search table, table configuration/maintenance configuration Input Port Output Port Port registers commands which user realize functions easily. registers accessed with direct addressing, there various effect commands table maintenance. input/output data bits width. endian function supported make easy access search table data bits. upper bits lower bits segment read/written with same address using endian function. Multiple devices easily cascade-connected order increase number entries table without external logic. extended realized cascade connection treated were continuous table device, because priority control done internally between devices. However, number segments forming entry search data table must same devices (even devices cascade connected). This device must arbitrate between ports protect against data destruction caused simultaneous access from plural ports. User select methods arbitration. internal arbitration mode which restricts device internal operation port-dependent modes (CPU mode, mode, mode, mode). this case, device determines whether device receives operations from every port not. other external arbitration. this case, simultaneous access from every port permitted. However, user decrease execution cycles, because instead external arbitration, mode restriction applied. User select either method according required applications.
Address Processor KE5B256B1
Functional Overview
KE5B256B1 (Address Processor: provides best solution fast complex "Address Filtering" requirements today's internetworking equipment with following outstanding functions. Flexible search data table definition answering various protocols. entry size configurable from bits bits. search operation width data performed with data position table. area accessed RAM. 3-port architecture Optimized functionality each port provides fast data processing. Programmable input data formatting search sequence input data width selected bits.
Definition data input search start position. Masking possible. Search window byte unit. Maximum step search sequence definition column table. Programmable output sequence Output sequence definition search result. Output sequence definition column entry. Multi-channel sequence maximum kinds sequences sequences defined indicating channel/ number start sequence. Cascading additional logic required. cascaded table acts integral search data. Commands Useful commands search table maintenance
Specifications
core Capacity Access table entry Configuration (Entry size) kbits Random access data (RAM, substitution) Configurable control entry width from bits bits units bits bits 8,192 entries bits 4,096 entries bits 2,728 entries bits 2,048 entries bits 1,636 entries bits 1,364 entries bits 1,168 entries bits 1,024 entries devices (adds table depth) Port Input Port (automatic) Masking Search operation table segment bits) search more than bits data accumulation using Access Port Output Port (automatic) result (HO_) Intermediate search result pins (SH0_, SH1_) address Entry data address data arch ratio
Cascading Search Operation
Result Output
Address Processor KE5B256B1
Specifications (cont'd) Ports Input Port (Key data input) Input Port sequence Sequence) Input data block width selectable (32, bits) Multi-channel: sequence channels (A/B) defined. Number start sequence selected. Maximum 8-step input sequence configuration data formatting functions. Through: block selectable among blocks data stream Data Accumulation Most recent bits temporarily stored (Accumulation Buffer Sub-accumulation Buffer) Search Window Set: data selectable with 32-bit width among bits accumulated data starting from (n=0-3, byte shift) byte Mask operation segment searched order. bits Multi-channel sequence channels (A/B) defined. Number start sequence selected. Maximum 8-step output sequence configuration Search data: data after data formatting used sequence (CMP0 CMP7 register) status: Hit, multi-hit, used channel (HSTAT register) address: entry address with highest priority (HHA register) Contents address (MEMHHA register) status output combination with other search results 16-bit data, 8-bit address Command execution Register Read/Write
Output Port (Search result output) Output Port sequence Sequence)
Port Sequence reset Search result output pins Cycle time Supply voltage Package Technology
SQRST_ (Pin) SSQRST command (from Port) HO_: Results each search operation SH0_, SH1_: Intermediate search results specified step sequence 80ns LVTTL compatible 3.3V 0.3V 144-pin PQFP 0.5µ CMOS
Address Processor KE5B256B1
Register Names
Register names described following abbreviations. Abbreviations Registers Abbreviation Register CNTL Register DEVID Register DEVSTAT Register DEVSEL Register Register MEMAR Register MEMHHA Register MEMHEA Register CPUHS Register MEMAR_AT Register MEMHHA_AT Register MEMHEA_AT Register SHASGN Register HHASGN Register Register Register Register MASK Register Register AOSC Register CPUINP Register CPUMASK Register CPUSRS Register CPUINP2 Register CPUMASK2 Register CPUSRS2 Register HSTAT Register ESTAT Register Register Register Register Register
Register Name Command Register Control Register Device Register Device Status Register Device Select Register Address Register Memory_AR Register Memory_HHA Register Memory_HEA Register HHA/HEA Segment Register Memory_AR Attribute Register Memory_HHA Attribute Register Memory_HEA Attribute Register Sequence Flag Assignment Register Automatic Output Assignment Register Register Search Start Register Channel Sequence Register Mask Register Automatic Output Control Register Automatic Output Control Register Input Data Register Mask Register Search Segment Register Input Data Register Mask Register Search Segment Register Status Register Empty Status Register Highest Address Register Highest Empty Address Register Sequence Result Register Comparand Register
Address Processor KE5B256B1
Block Diagram
Input Port bits)
IPCH ISNM<2:0> SQRST_
Data Formatter
Input Port Sequencer
ID<31:0>
bits
bits
MASK Comparison Logic Command
Control Status
Priority Encoder
Access
Empty
Decoder
8,192 words 32bits
Flag
Array
Memory
Configuration
Port
bits
R/W_ RST_ SP/TP_ bits DAT<15:0> bits ADD<7:0>
Search bits Table Status
OPCH OPNS
Output Port Sequencer
FLI_ FLO_ bits SH0_ SH1_ IPBUSY_/OPACT_ OPBUSY_/IPACT_
Output Port bits OD<31:0>
Flag Logic
Fig. Block Diagram
Address Processor KE5B256B1
Assignment Descriptions Assignment
KE5B256B1CFP (144-pin PQFP type)
index
KE5B256B1CFP QFP144
Fig. 3.1.1 Assignment
Address Processor KE5B256B1 Table Assignment
Signal Name OD<2> OD<1> OD<0> SH1_ SH0_ FLO_ ID<0> ID<1> ID<2> ID<3> ID<4> ID<5> ID<6> ID<7> ID<8> ID<9> ID<10> ID<11> ID<12> ID<13> ID<14> ID<15> ID<16> ID<17> ID<18> ID<19> ID<20> ID<21>
type
Signal Name ID<22> ID<23> ID<24> ID<25> ID<26> ID<27> ID<28> ID<29> ID<30> ID<31> IPBUSY_/OPACT_ OPBUSY_/IPACT_ SQRST_ RST_ ADD<0> ADD<1> ADD<2> ADD<3> ADD<4> ADD<5> ADD<6> ADD<7> R/W_ DAT<0> DAT<1> DAT<2> DAT<3> DAT<4> DAT<5>
type OPEN*1
Address Processor KE5B256B1 Table Assignment (cont'd)
Signal Name DAT<6> DAT<7> DAT<8> DAT<9> DAT<10> DAT<11> DAT<12> DAT<13> DAT<14> DAT<15> ISNM<0> ISNM<1> ISNM<2> OPNS IPCH OPCH OD<31> OD<30> OD<29> SP/TP_ FLI_ OD<28> OD<27> OD<26> OD<25> OD<24> OD<23> OD<22> OD<21> OD<20>
type OPEN*1
Signal Name OD<19> OD<18> OD<17> OD<16> OD<15> OD<14> OD<13> OD<12> OD<11> OD<10> OD<9> OD<8> OD<7> OD<6> OD<5> OD<4> OD<3>
type OPEN*1
pins should open. connect.)
Address Processor KE5B256B1
Descriptions
name DAT<15:0> Attribute Port Data Input Output Tri-state LVTTL Function DAT<15:0> 16-bit, bidirectional data used convey data, commands, status from Address Processor (AP). direction controlled state R/W_. DAT<15:0> enabled level CE_. ADD<7:0> 8-bit address used select registers.
ADD<7:0>
Port Address Input LVTTL Device Enable Input LVTTL
used access from Port. R/W_, ADD, inputs latched falling edge CE_.
R/W_
Read/Write Input LVTTL
R/W_ selects write cycle. R/W_ high selects read cycle. state R/W_ registered falling edge CE_.
RST_
Hardware Reset Input LVTTL
RST_ hardware reset signal. pulse RST_ initializes minimum hold time 40ns.
ID<31:0>
Input Port Data Input LVTTL
ID<31:0> 32-bit data used convey search data through Input Port. width also configured bits (ID<7:0>) bits (ID<15:0>).
Address Processor KE5B256B1 Name Attribute Input Port Write Pulse Input LVTTL Function controls search operation through Input Port. Users select polarity According through configuration, data transferred falling edge (negative pulse) rising edge (positive pulse)
SP/TP_
Port Number Select Input LVTTL
SP/TP_ controls mode restriction register access command execution. When SP/TP_ pulled down, independent triple ports restricts some operations mode. When SP/TP_ pulled like single port reduces restriction.
SQRST_
Input/Output Port Sequence Pointer Reset Input LVTTL
SQRST_ Sequence Pointer Reset signal Input Port Output Port. pulse SQRST_ initializes Input Port Sequence Pointer Output Port Sequence Pointer. hold time requires more than 40ns.
OD<31:0>
Output Port Data Output LVTTL Output Port Read Pulse Input LVTTL
OD<31:0> 32-bit data used output results search operation.
controls read access through Output Port. Output Port read cycle starts falling edge RD_. outputs results search operation according output sequence configuration.
Output Port Outpt Enable Input LVTTL
enables output. When low, output drivers enabled. When high, impedance becomes high.
Address Processor KE5B256B1 Name IPBUSY_/OPACT_ Attribute Input Port Busy/ Output Port Active Output LVTTL Function IPBUSY_/OPACT_ used monitor status port operation. When SP/TP_ pulled down, this becomes busy signal Input Port. This during Output Port read cycle mode. other hand, when SP/TP_ pulled this becomes active signal Output Port. This during Output Port read cycle.
OPBUSY_/IPACT_
Output Port Busy/ Input Port Active Output LVTTL
OPBUSY_/IPACT_ used monitor status port operation. When SP/TP_ pulled down, this becomes busy signal Output Port. This during Input Port read cycle mode. other hand, when SP/TP_ pulled this becomes active signal Input Port. This during Input Port write cycle.
Flag Output Output LVTTL
used output search results. This when even occurs search operation. This high when entry hit. cascaded system, signal cascade configuration appear output lowest priority device (Last Device).
Flag Input Input LVTTL
used cascaded system. input connected output adjacent higher priority device. This connection propagates information from high priority device lower priority device. highest priority device should pulled cascaded system, single system, device should pulled
Address Processor KE5B256B1 Name SH0_, SH1_ Attribute Sequence Flag Output Open Drain Function SH0_ SH1_ used output intermediate search results search sequence from Input Port. When there search results specified sequence number, this low. other hand, when there hit, this high impedance. SH0_ SH1_ programmably selected output intermediate search results.
Priority Output Output LVTTL
used propagate priority information device output multi-hit information. cascaded system, this propagates priority information (DEVID priority) cascaded system lower priority device. This also used multi-hit status flag. When this low, multi-hit occurs. cascaded system, lowest priority device (Last Device) outputs system multi-hit information.
Priority Input Input LVTTL
used cascaded system. input connected output adjacent higher priority device. This connection propagates DEVID priority from high priority device lower priority device. Multi-hit information also propagated this connection. highest priority device should pulled cascaded system, single system, device should pulled FLO_ used output search results. This when entries filled with effective entries (full status) there entry registration. cascaded system, full signal cascade configuration appears FLO_ output lowest priority device (Last Device).
FLO_
Full Flag Output Output LVTTL
Address Processor KE5B256B1 Name FLI_ Attribute Full Flag Input Input LVTTL Function FLI_ used cascaded system. FLI_ input connected FLO_ output adjacent higher priority device. This connection propagates full/empty information from high priority device lower priority device. FLI_ highest priority device should pulled cascaded system, single system, device should pulled IPCH determines Input Port active channel when hardware channel selection defined CNTL register. state IPCH registered falling edge SQRST_ pulse pulse SSQRST command. IPCH selects channel high selects channel "B."
IPCH
Input Port Channel Input LVTTL
ISNM<2:0>
Input Port Start Sequence Number Select Input LVTTL
ISNM<2:0> used indicate start search sequence number. When hardware channel selection defined CNTL register, this 3-bit field indicates start sequence number directly. Signals this fields latched falling edge SQRST_ pulse pulse SSQRST command. OPCH determines Output Port active channel when hardware channel selection defined CNTL register. state OPCH registered falling edge SQRST_ pulse pulse SSQRST command. IPCH selects channel high selects channel "B."
OPCH
Output Port Channel Input LVTTL
Address Processor KE5B256B1 Name OPNS Attribute Output Port Start Sequence Number Selection Input LVTTL Function OPNS used indicate start output sequence number. This determines whether start sequence number number indicated CNTL register. Signal OPNS latched falling edge SQRST_ pulse pulse SSQRST command. When this low, sequence number selected. other hand, when this high, sequence number pointed CNTL register selected.
Supply Supply
Power Supply: 3.3V 0.3V Ground
Address Processor KE5B256B1
Port Operation Mode Overview Port Overview
KE5B256B1 Input Port, which only used input search data, Output Port, which only used output search results, Port, which used control device, table configuration, table maintenance. overview each port presented below. Input Port 32-bit Input Port receives data search operations. port width 32-bit width, configured bits. When bits configured, bits side ID<31:0> used, with bits, ID<15:0> effective. With bits, ID<7:0> effective. data ID<31:0> input into device applying writing pulse pulse) pin. pre-defined search sequence sequence) then executes. polarity pulse programmable, configured user negative positive pulse. pulse cycle called Input Port cycle. sequencer Input Port operates synchronously with pulse. sequence executes following processes. Through Only desired data blocks search keys picked from among input data stream applied from Input Port. Data Accumulation data blocks picked Through process stored Accumulation Buffer Sub-accumulation Buffer device. total number bits which stored Accumulation Buffer Sub-accumulation
Buffer bits. Search Window Setting 32-bit data block selected search data from among 64-bit data block stored above buffers. position window byte. Mask Operation bits search data selected masked bit. Masked bits compared with corresponding bits search data. Selection Search Segments column position (segment) search data table searched selected. Execution Search These sequencer operation sequence) programmable. Each step search operation defined independently. sets sequence defined (2-channel architecture). Each channel contain maximum steps. kinds sequences execute changing these channels. Furthermore, user sequencer dividing function. this case, maximum kinds sequence, which have various search mask definitions search segment definitions, defined (multi-channel). Chapter detailed discussion sequence definitions. Output Port 32-bit Output Port provides search results. data output synchronously with pulse OD<31:0>. cycle pulse called Output Port Cycle. There several search results output from Output Port listed below.
Address Processor KE5B256B1 status (Hit, Multi-hit, etc.) Address entry Stored data entry data used sequence Users define which results output numbers which results output sequencer sequence). sequence also constructed channels, each channel contain maximum steps sequence). Users sequencer dividing function define multi-channel sequences. Chapter detailed discussion sequence definitions. Port Port 16-bit data DAT<15:0> interfacing with host processor. address ADD<7:0> determines which register accessed device. Each operation through Port executed synchronously with pulse. pulse cycle called Port Cycle. R/W_ signal determines whether cycle reading cycle writing cycle. operations using Port executed reading writing registers indicated Address (ADD<7:0>). processes executed Port presented below. Setting Basic Device Operations This setting executed writing CNTL register. contents setting Endian function (see Chapter polarity pulse method IP/OP channel selection (see Chapters detailed discussion CNTL register presented Section 13.3. Device Registration (only cascaded systems) With cascaded system, Device must registered. detailed discussion Device registration presented Section 9.1. Table Configuration column size (entry width) size (entry number) table must defined. This definition called table configuration. Chapter detailed discussion. IP/OP Sequence Definition search sequence Input Port sequence) output sequence Output Port defined. method input data formatting, mask operation, search segment defined setting register, register, register, MASK register sequence. Section detailed discussion. pointing search required results (Status, Address, Data) output segment defined setting register AOSC register. detailed discussion presented Section 7.1. Table Creation Maintenance creation maintenance table executed accessing data CAM. This operation executed both former operation also using maintenance command. Chapter detailed discussion. Command Execution Commands executed writing OP-code into register. Some commands prepared mode change, device reset, IP/OP sequence reset, table maintenance.
Address Processor KE5B256B1 Search Operation search operation also executed through Port. However, automatic search operations cannot defined search operations through Port, with sequence). data, mask data, search segment number should CPUINP, CPUMASK, CPUSRS register prior performing SRCH command. detailed discussion presented Chapter Search Results results search operation output Port reading registers (e.g. HSTAT, ESTAT, HHA, CMP) which store status, address, intermediate information sequence. Stored data entry output reading MEMHHA register. detailed discussion, Chapter access table above-mentioned operations part simultaneous access through Input Port Output Port permitted protect table data against destruction. However, register access except table execution commands with relation table manipulation executed while Input Port Output Port running, because access will cause table destruction. detailed discussion operations which permitted simultaneously presented Table 4.3.1. internal arbitration, example, mode, device controlled execute operations through Input Port sequence) Output Port sequence). Therefore, shift mode operation necessary before executing required operations. External Arbitration External arbitration method that restricts access simultaneous device through plural ports external device. example, when access signals each port created same clock, accesses each port exclusive. this case, command shifting modes omitted using external arbitration. There basically mode concept external arbitration. only restrictions operation modes that related sub-mode table definition DEVID sub-mode Device registration. SP/TP_ determines which arbitration method selected. When SP/TP_ pulled down, internal arbitration selected. pulled external arbitration selected. Internal Arbitration Internal arbitration restricts access simultaneous device through plural ports according operation mode. operation modes internal arbitration include mode, which host processor mainly operates mode, which sequence executed, mode, which sequence executed, mode, which waiting mode shifting mode. sub-mode table definition DEVID sub-mode Device registration also included.
Arbitration
This device permitted access through plural ports simultaneously protect against data destruction. Therefore, necessary arbitrate operations through three ports (CPU, Input, Output) using methods described below.
Address Processor KE5B256B1
Operation Modes Overview
mentioned above, during internal arbitration, operation device restricted operation mode. detailed discussion each mode given below. Mode mode used access device through Port. this mode, accesses through Input Port Output Port become invalid. Transition mode executed device reset operation (applying pulse RST_ issuing SRST command) issuing SWCPUP SWCPU_IM commands. Operation through Port basically mode, there operations which executed other modes. internal arbitration, operations related table executed shifting mode. Operations which performed only mode discussed below internal arbitration. Writing CNTL Register CNTL register different from core, this register cannot written only mode because basic definitions CNTL register important information accessing table. Reading CNTL register executed other modes. Creating Table Maintenance Commands read/write data table executed protect against data destruction simultaneous access through Input Port Output Port when only mode executed. Reading Register register also accessed protect against
data destruction simultaneous access through Input Port Output Port when only mode executed. When execute above operation, which executed only mode, careful about mode shifting. summary operations which permitted simultaneous access through Input Port Output Port presented Table 4.3.1. DEVID Sub-mode DEVID sub-mode, which belongs mode, used register unique Device every cascaded device. following operations require registration Device DEVID sub-mode. STR_DEVID command Read/Write DEVID register NXT_PR command END_DEVID command DEVID sub-mode except Device registration. case single device, DEVID submode necessary because Device registration necessary. Section detailed discussion Device Sub-mode sub-mode, which belongs mode, user defines many segments segment bits) table entry. This operation called table configuration. sub-mode, only following operations which necessary configure table performed. STR_TC command Read/Write register (pointing address)
Address Processor KE5B256B1 Table 4.3.1 Prohibited operations simultaneous access through Input Port Output Port
Operations Register access table Content operation MEMAR register Read/Write MEMHHA register Read/Write MEMHEA register Read/Write MEMAR_AT register Read MEMHHA_AT register Read MEMHEA_AT register Read Command table SRCH command SRCH2 command PRG_AL command PRG_NAC command PRG_AC command RST_AC command PRG_ACWH command RST_ACWH command PRG_HH command PRG_AR command NXT_HH command Secondary register access table CNTL register Write register Read GEN_HIT command NXT_HE command GEN_FL command APPEND command APPEND_NHE command RESTORE command STMP2_AR command STMP_HH command STMP2_HH command STMP_HE command STMP2_HE command
PRG_NACWH command STMP_AR command
Read/Write MEMAR register (Read/Write data) END_TC command These commands cannot used except table configuration. Table configuration must executed when user uses device. detailed discussion table configuration presented Section 5.2. Mode mode stand-by state mode mode. device moves mode from mode when SWIOP command executed. this mode, sequencer Input Port starts operate automatically, mode device moves mode (Note When defined sequence ends, mode returns mode automatically.
When pulse applied mode, sequence Output Port starts operate mode device moves mode. When defined sequence ends, mode returns mode. mode, operations (e.g. accessing table through Port) which permitted only mode cannot executed. When user wishes execute these operation, necessary change mode issuing SWCPUP command SWCPUP_IM command. Mode Input Port active mode. When pulse applied Input Port mode, mode device moves mode search operation starts according defined sequence. search operation executed synchronously with pulse,
Address Processor KE5B256B1 sequence processed step step. sequence pointer increases with each step. When pointer arrives step which defined sequence, pointer stops mode returns mode automatically. However, when mode returns mode, sequence will operate even when pulse input, because sequence pointer stopped. user wishes start sequence again, necessary initialize stopped pointer. Inputting SQRST_ pulse issuing SSQRST command initializes pointer. mode, output operation through Output Port operations (e.g. accessing table through Port) which permitted only mode cannot executed. When interrupt commands (SWCPUP, CWCPUP_IM, SWCPUP_SQE command) executed before sequence, device moves mode according timing command specification. detailed discussion interrupt commands through Port presented later section. Mode Output Port active mode. When pulse applied Output Port mode, mode device moves mode output operation starts according defined sequence. output operation executed synchronously with pulse sequence processed step step. sequence pointer with each step. When pointer arrives step which defined sequence, pointer stops mode returns mode automatically. When mode returns mode, sequence will operate when pulse input, because sequence pointer stopped. Users wish restart sequence should initialize stopped pointer using sequence pointer reset operation. mode, search operation through Input Port operations (e.g. accessing table through Port) which permitted only mode cannot executed. When interrupt commands executed before sequence, device moves mode according timing command specification. (Note sequence pointer reset operation with changing operation necessary start sequence.
Address Processor KE5B256B1 Mode Transition Command Mode transition shown Fig. 4.3.1 when SP/TP_ pulled down internal arbitration). mode transition controlled pulses command. detailed discussion presented below. mode mode transition mode from mode executed basically executing SWIOP command. Some commands which executed mode have SWIOP command function. After these commands execute, device return mode immediately. This function called automatic SWIOP function. Users determine whether automatic SWIOP function setting CPUHS register. This function omits issuing SWIOP command, make processes more efficient. following commands have automatic SWIOP function. Chapters detailed discussion each command. Append commands APPEND command APPEND_NHE command Stamp commands STMP_AR command STMP_HH command STMP_HE command STMP2_AR command STMP2_HH command STMP2_HE command mode mode transition mode from mode executed inputting pulse. However, when sequence pointer stops, pulse received mode transition executed. user wishes move mode (starting sequence), sequence pointer reset operation must executed beforehand. sequence pointer reset operation executed before SWIOP command. mode mode When predefined sequence ends, mode device returns mode. When sequence pointer reset operation executed mode, mode returns mode without waiting sequence. Users wish have mode return mode middle sequence should use, sequence pointer reset operation. (See Chapter 14.) mode mode transition mode from mode executed inputting pulse. However, when sequence pointer stops, pulse received mode transition executed. user wishes move mode (starting sequence), sequence pointer reset operation must executed beforehand. sequence pointer reset operation sequence necessary sequence pointer reset operation executed before sequence which corresponds sequence, because sequence pointer reset operation initializes both sequence pointer sequence pointer. mode mode When predefined sequence ends, mode returns mode. When sequence pointer reset operation executed mode, mode returns mode without waiting sequence. Users wish have mode return mode middle sequence should use, sequence pointer reset operation. (See Chapter 14.)
Address Processor KE5B256B1
Power Device Reset
*SP/TP_pull down
STR_DEVID command END_DEVID command STR_TC command END_TC command
DEVID sub-mode sub-mode
mode
sequence after SWCPUP, SWCPUP_SQE command execution cycle after SWCPUP_IM command execution
sequence after SWCPUP, SWCPUP_SQE command execution cycle after SWCPUP_IM command execution
SWIOP command Stamp, Append command with automatic SWIOP command RD_pulse
SWCPUP command SWCPUP_IM command pulse
mode
Sequence pointer reset sequence
mode
Sequence pointer reset sequence
mode
Normal operation state
Device reset RST_pulse SRST command Sequence pointer reset SQRST_pulse SSQRST command Fig. 4.3.1 State Diagram internal arbitration Table 4.3.2 IPBUSY_/OPACT_, OPBUSY_/IPACT_ internal arbitration IPBUSY_/OPACT_ mode (including DEVID sub-mode sub-mode) mode mode mode OPBUSY_/IPACT_
Address Processor KE5B256B1 mode mode SWCPUP command SWCPUP_IM command issued move mode mode from mode. mode/OP mode mode (CPU interrupt) When interrupt commands (SWCOUP, SWCPU_IM, SWCPUP_SQE) issued, user move mode mode from mode/OP mode without using mode. detailed discussion interrupt commands presented below. SWCPUP Command When SWCPUP command issued during sequence/OP sequence, interrupt reserved device moves mode without passing through mode after sequence being executed. When SWCPUP command issued mode, device moves mode immediately. SWCPUP_SQE Command SWCPUP_SQE command also moves mode mode after sequence/OP sequence. However, when command issued mode, interrupt only reserved device does move mode immediately. This point different from SWCPUP command. this case, transition mode also executed after sequence/OP sequence. SWCPUP_IM Command When SWCPUP_IM command issued during sequence/OP sequence, interrupt reserved immediately device moves mode without waiting sequence being executed. input Port cycle/Output Port cycle, which executed when Normal transition DEVID sub-mode from mode executed issuing STR_DEVID command. END_DEVID command issued return mode after Device registration. mode sub-mode Normal transition sub-mode from mode executed issuing STR_TC command. END_TC command issued return mode after table configuration. Users confirm mode device reading DEVSTAT register IPBUSY_/OPACT_ OPBUSY_/IPACT_ pin. IPBUSY_/OPACT_ OPBUSY_/IPACT_ pins beSWCPUP_IM command issued, continues operate device moves mode cycle. When SWCPUP_IM command issued mode, device moves mode immediately. sequencer/OP sequencer detects issuance above-mentioned interrupt commands edge WR/RD_ pulse. (See Chapter interrupt mode/OP mode.) When timing shown Chapter observed, command detected until next edge WR/RD pulse, transition mode executed late. transition mode confirmed DEVSTAT register IPBUSY_/ OPACT_ OPBUSY_/IPACT_ pin. there WR/RD_ pulse some reason, interrupt command detected transition mode executed. this case, SWCPUP command move device mode after IP/OP sequence stopped sequence pointer reset operation. mode DEVID sub-mode
Address Processor KE5B256B1 come busy signals internal arbitration, shown Table 4.3.2. Both IPBUSY_/OPACT_ OPBUSY_/IPACT_ pins become indicate "Busy" Input Port/ Output Port mode (including DEVID submode sub-mode). OPBUSY_/IPACT_ becomes prohibit operation through Output Port indicates "Busy" Output Port. IPBUSY_/OPACT_ becomes prohibit operation through Input Port indicates "Busy" Input Port. IPBUSY_/OPACT_ OPBUSY_/IPACT_ pins become high indicate ready status sequence sequence mode. DEVSTAT register flag which indicates that mode mode internal arbitration. DEVSTAT register flag which indicates that mode mode internal arbitration. DEVSTAT register flag which indicates that mode mode internal arbitration. Chapter detailed discussion DEVSTAT register. Examples typical internal arbitration presented below. When device reset operation RST_ signal SRST command) executed, device moves mode automatically. After Power device reset operation pulse RST_ signal must executed. device reset operation initializes many registers. initialized values shown Chapter Registers sequence/OP sequence have pre-determined initial values. Register Device every device moving DEVID sub-mode after device reset operation cascaded system. After Device registration, transition back mode executed END_DEVID command. Chapter detailed discussion Device registration. case single device, Device registration necessary. First, execute designation device operation setting CNTL register mode after device reset operation (Device registration cascaded system). detailed discussion CNTL register presented Chapter 13.) Second, execute table configuration moving sub-mode. When table configuration words ends, transition back mode executed END_TC command. Third, execute create table operation (writing table data). Chapter detailed discussion command accessing maintenance table. Execute sequence/OP sequence definition setting register, register, register, MASK register, register, AOSC register. detailed discussion presented Section 7.1. After above processes have been executed mode, device activated. When SWIOP command issued this time, mode ends device moves mode. When pulse input after sequence pointer reset operation mode, device moves mode executes sequence according definition. When sequence ends, mode moves mode automatically. this time device moves mode when pulse input, user fetch results sequence using sequence. When sequence
4-10
Address Processor KE5B256B1 ends, device returns mode. When modifying/appending data table after sequence sequence, issue above interrupt command move device mode. After modifying/appending data table, device moved mode SWIOP command. sequence pointer reset operation executed, device moved waiting state transition mode. sequence pointer reset operation also executed mode after transition mode. external arbitration operations described below. device reset operation also necessary external arbitration after Power device should then moved DEVID sub-mode using STR_DEVID command cascaded systems Device should registered. After Device registration, execute END_DEVID command. After setting CNTL register, move device sub-mode using STR_TC command execute table configuration. After table configuration, exit Device from sub-mode using END_TC command. After writing table data IP/OP sequence configuration, sequence sequence start without SWIOP command sequence pointer reset operation executed. modification/appending table data entry) after sequence sequence, mode transition using interrupt command necessary. Therefore SWIOP, SWCPUP, SWCPUP_IM, SWCPUP_SQE commands completely unnecessary. However, user should control device from outside maintain timing specifications between RD_, CE_, signals. operations through Port related table (other than Table 4.3.1), there timing restriction between pulse pulses.
External Arbitration
described Section 4.2, external arbitration method outside device which prohibits simultaneous access device through plural ports. example, when accessing signals plural ports (WR, RD_, CE_) given from same system clock only becomes active, sufficient interval signals secured because only signal always accesses device. When interval accessing from every port guaranteed obtain determined time width outside device, external arbitration defined. When external arbitration defined, mode restriction operations disappears issuing commands (SWIOP, SWCPUP, SWCPU_IM, SWCPUP_SQE) mode transition necessary. Therefore, process cycles decreased when much accessing table through Input Port Output Port modification table through Port required. However, sub-mode table configuration DEVID sub-mode DEVICE registration necessary move device sub-mode. comparison with mode transition internal arbitration shown Fig. 4.4.1.
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Address Processor KE5B256B1 user observes above-mentioned timing restrictions among signals, mode transition necessary except transition sub-mode table configuration transition DEVID mode Device registration. sequence start during sequence (before finishing sequence completely), sequence continue execute again. That both sequence sequence simultaneously. However, adequate care should used sequence configuration. external arbitration, there mode concept. DEVSTAT register after device reset operation indicates same status mode. However, this does change there after. bits DEVSTAT register initialized "0," these bits become when sequence/OP sequence running. OPBUSY_/IPACT_ busy signal Output Port, becomes port active signal which indicates whether Input sequence running not. IPBUSY_/OPACT_ busy signal Input Port, becomes port active signal which indicates whether Output sequence running. above discussion summarized Table 4.4.1. After sequence pointer reset operation, both OPBUSY_/ IPACT IPBUSY_/OPACT_ pins become high, indicate that both sequence sequence start. When sequence starts pulse, OPBUSY_/IPACT_ becomes low, indicates that sequence running. OPBUSY_/IPACT_ becomes high when sequence ends. other hand, when sequence starts pulse, IPBUSY_/OPACT_ becomes low. IPBUSY_/OPACT_ becomes high, when sequence ends. When both sequence sequence running, both OPBUSY_/IPACT IPBUSY_/ OPACT_ pins become low. However, both pins high initial state after device reset operation, because neither sequence being executed. Thus, attributes indications OPBUSY_/IPACT IPBUSY_/ OPACT_ pins change depending arbitration method. Therefore, careful with regard differences shown Table 4.3.1 Table 4.4.1.
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Address Processor KE5B256B1
Power Device Reset
*SP/TP_pull
STR_DEVID command END_DEVID command
DEVID submode
STR_TC command END_TC command
sub-mode
Waiting state IP/OP sequence
CPU, modes)
RD_pulse pulse
sequence
Sequence pointer reset** sequence Normal
sequence
Sequence pointer reset** sequence
operation state
Device reset RST_pulse SRST command Sequence pointer reset SQRST_pulse SSQRST command Fig. 4.4.1 State Diagram external arbitration Table 4.4.1 IPBUSY_/OPACT_, OPBUSY_/IPACT_ external arbitration IPBUSY_/OPACT_ OPBUSY_/IPACT_ Both sequence sequence running (Initial state after device reset) sequence running sequence running Both sequence sequence running
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Address Processor KE5B256B1
Table
KE5B256B1 256-kbit stores data table searched CAM. This chapter discusses data table (CAM table) construction relation between searches table.
Segment Data segment data stores entry data. width segment datum bits. segment data used RAM. segment data operates search operation. table read/write, table maintenance, outputting search results, segment data operates RAM. definition distinction CAM/RAM required. methods addressing when reading/writing segment data used address (absolute address indication) indication address segment number entry, using entry address shown register (discussed below) index. Boundary
Entry Segment
table made logically many entries. searching, part data entries compared simultaneously with entries CAM. device feature, width (data entry) number entries flexibly. entry made 32-bit segments. Accessing table searching operation executed segment unit. Physically, segment corresponds CAM_word. device (8,192)-CAM_words store 256k-bit entry data. Each word assigned absolute address (CAM address) 0H~1FFFH (0~8192), only segment data space storing entry data, also circuit elements realizing some functions. Fig. 5.1-1 shows elements comprising segment. detailed discussion presented below.
Boundary used segment numbers (discussed below) Table Configuration, read written only sub-mode. Segment Number 3-bit width segment number indicates number segment entry. segment data read written only sub-mode.
bits
bits
Segment data Segment number Boundary Empty Access Flag
Fig. 5.1.1 Word structure
Address Processor KE5B256B1 search operation, position searched selected indicating segment number. When user accesses segment data RAM, they should select segment entry indicating segment number. segment number determined register register with index which segment number entry. entry width entry number table determined setting Boundary segment number. Section 5.2, Table Configuration detailed discussion setting sequences. Empty Empty flag that indicates whether valid data written segment (empty). flag logic shown below. valid (Valid data written.) empty (Segment space.) When Empty "1," segment search target. Empty Bits words after device reset operation. reset when corresponding segment written. conditions under which Empty reset presented below. conditions (empty) Device reset Table configuration Purge command Reset conditions (valid) Writing segment data Restore command Stamp command Append command Empty read into MEMAR_AT, MEMHHA_AT, MEMHEA_AT register. Flag Flag indicates whether applied search data identical with segment data being searched. flag logic shown below. Mis-hit (not identical) (identical) Flag internal data, cannot read written directly register access, etc. Access Access flag that indicates whether there previous hits search operation. flag logic shown below. hits. history) more previous hits. less than hit) initial state Access "0." Users specify whether history held Access during search operation. Access when there more hits after search which hold history. Access holds until Access reset operation (purge command reset, etc.) executed. When purge command executed with Access Bit, entries which have hits purged collectively. detailed discussion purge command function appears Section 8.7. Access basically after search operation reset command. However, same operation also executed accessing MEMAR_AT, MEMHHA_AT, MEMHEA_AT register. Access read through these registers.
Address Processor KE5B256B1
Table Configuration
Table Configuration table table construction device defined flexibility Table Configuration. There eight variations Table Configuration, shown below. bits 8,192 entries segment construction) bits 4,096 entries segment construction) bits 2,728 entries segment construction) bits 2,048 entries segment construction) bits 1,636 entries segment construction) bits 1,364 entries segment construction) bits 1,168 entries segment construction) bits 1,024 entries segment construction) above constructions defined setting Boundary segment number data). 8,192CAM word (0H~1FFFH) actually divided into four banks. same configuration necessary banks. case entry segment construction, define segment number cyclically (e.g. n-1, from head word each bank, Boundary segment number word other words "0." This operation concatenates continuous segments (segment number segment number entry. concept entry Table Configuration shown Fig. 5.2.1. Each entry contain contents extending across multiple segments. this case, entry number bank becomes maximum integer which satisfies following formula. 2,048 total entry number four banks When entry constructed segments, there remaining segments every bank. segment number remaining segments must ("111"), Boundary must "0." necessary that number remaining segments case identical with quotient obtained division
word number (8,192) because every four bank remaining segments. device does operate table without Table Configuration. Therefore, after Power device reset operation, Table Configuration necessary before using device. Table Configuration Procedure Table Configuration procedure described below. First, write "n-1" value WW<2:0> bits CNTL register. value "n-1" important when using automatic increment function MEMHHA register MEMHEA register, which explained Chapter this time, other bits CNTL register must also appropriate values every setting device. CNTL register shown Chapter Move sub-mode write data with STR_TC command. Write address register data table MEMAR register. maps these registers shown Chapter data must words four banks. When entry comprises 7-segments, remaining segments each bank must (segment number "111," Boundary "0"). cascaded systems, same configuration necessary devices. this case, broadcast writing method, which write devices simultaneously, useful. written data confirmed reading MEMAR register sub-mode. Escape sub-mode using END_TC command after setting data 8,192 words. Table Configuration, frame table complete, entries become empty. GEN_FL command must executed immediately after Table Configuration that device will recognize empty condition entries. Chapter Chapter detailed discussion GEN_FL
Address Processor KE5B256B1 Segment number Segment Segment bits Bank Entry number
Boundary
Segment
Entry number
Entry number
Remaining segment Segment content(i,1)
content(i,0)
Entry number
Bank
Entry number 2m-1
Remaining segment
Entry number Bank
Entry number 3m-1
Remaining segment
Entry number
Bank
Entry number 4m-1
Remaining segment Fig. 5.2.1 Concept Table Configuration
Address Processor KE5B256B1 command. construction data table 3-segment configuration shown Fig. 5.2.2. Table Configuration procedure shown Fig. 5.2.3. Start Segment Entry Address Index Every entry table constructed with single plural segments. start segment which segment number represents entry, unlike other segments, following some important roles. Entry Address address start segment called entry address, used indicate location entry. register stores highest priority (CAM address small) address. register stores highest priority empty entry address. necessary that interval entry address 7-segment construction because banks have remaining segments between banks. Empty Entry Empty start segment indicates whether entries empty. When Empty start segment "1," whole entry treated empty object search. When whole entry valid. Empty start segment cleared writing start segment, changed writing other segments. PRG_AR command RESTORE command must also executed start segment. When stamp command executed start segment, entry becomes valid. Entry Access Flag start segment represent entry information. When object search index entry address which stored register register. entry being accessed selected index segment number entry. Modification, appending, purge operations segment data then performed with case. Priority mentioned above, address empty entry shown register register order entry priority. Therefore, entry priority important device. degree priority determined relation between entry physical device location. same device, entry with small address high priority. same device, entry which entry address highest priority. cascaded system, higher level devices system have higher priority. entries higher level devices have higher priority than entries lower level devices. also detailed discussion Chapter start segment, search result also indicated Flag access flag start segment. register stores entry address (CAM address start segment). user should access start segment when reading/writing access using MEMAR_AT register.
Read/Write Segment Data
Reading writing entry data executed reading writing segment data. method reading writing segment data method discussed below.
Address Processor KE5B256B1 address 2,043 2,044 2,045 2,046 2,047 2,048 2,049 2,050 2,051 4,091 4,092 4,093 4,094 4,095 4,096 4,097 4,098 4,099 6,139 6,140 6,141 6,142 6,143 6,144 6,145 6,146 6,147 8,187 8,188 8,189 8,190 8,191 Boundary Segment number Bank
Remaining segment Bank
Remaining segment Bank
Remaining segment Bank
Remaining segment
data Fig.5.2.2 Example Table Configuration entry with three segments
Address Processor KE5B256B1 Boundary Segment number Entry number
Bank
Remaining segment
Boundary
Entry number
Bank
1363 Remaining segment
Boundary
Bank
Entry number 1364 1365 1366 2045 Remaining segment
Boundary
Bank
Entry number 2046 2047 2048 2727 Remaining segment Table status after configuration Fig. 5.2.2 Example Table Configuration entry with segments (cont'd)
Writing CNTL register
Writing register
Writing register
Writing data
Writing register
Writing data
Writing register
Writing data
Writing register
Writing register
CNTL register
register
register
MEMAR register
register
MEMAR register
register
MEMAR register
register
register
ADD<7:0>
Maximum segment number entry
STR_TC command END_TC command GEN_FL command
Address Processor KE5B256B1
DAT<15:0>
1FFFH
sub-mode
Fig. 5.2.3 Example Table Configuration entry with segments
Address Processor KE5B256B1 Address Indication physical address (0H~1FFFH) assigned every segment (CAM word) There address indication methods, described below. Absolute Addressing Register segment selected designating address (0H~1FFFH) using address. selected segment data accessed through MEMAR register. After setting register, segment data read executed reading MEMAR register, writing segment data executed writing MEMAR register. Indexed Addressing Register index entry address which stored register. segment selected index segment number entry. selected segment number indicated CPUHS register. selected segment data accessed through MEMHHA register. After setting register, reading segment data executed reading MEMHHA register, writing segment data executed writing MEMHHA register. function this addressing method, segment number entry address incremental. Creating table data table maintenance easy using this function. Indexed Addressing Register index entry address which stored register. segment selected index segment number entry. selected segment number indicated CPUHS register. selected segment data accessed through MEMHEA register. After setting register, reading segment data executed reading MEMHEA register, detailed discussion setting CPUHS register case above presented Section Chapter Endian Function width segment data bits, width Port data bits. Therefore, accesses necessary read/write segment data. device endian function that changes upper lower bits MEMAR, MEMHHA, MEMHEA register automatically when accessing these registers. This function enabled default. 32-bit read/write operation executed every times these registers accessed. CNTL register indicates which register accessed first. Accessing controlled endiantoggle-pointer. This toggle operation executed when MEMAR, MEMHHA, MEMHEA registers read written. Therefore, when upper lower 16-bit word only read written, care necessary regarding whether next access object upper lower. (next access point flag) DEVSTAT register indicates whether next access object upper lower. Basically, necessary read write both upper lower word. However, user wishes access either upper lower word according contents segment data, necessary access side. this case, endian function disabled setting EAOFF CNTL register "1." When endian function disabled, toggle operation executed side always accessed. CNTL register determines whether object being accessed upper lower. When user wishes change fixed side, necwriting segment data executed writing MEMHEA register. function this addressing method, segment number entry address incremental. Creating table data table maintenance easy using this function.
Address Processor KE5B256B1 essary EAOFF CNTL register (endian function EAOFF endian function OFF), select side using bit. Access endian function also shown Fig. 5.3.1. When following operations executed, toggle pointer initialized according flag CNTL register. Device reset Writing register Writing CPUHSL register Search operation (through Input Port Port) GEN_HIT command GEN_FL command Renewal register Renewal register Series Registers confirmation entry Empty executed reading series registers (MEMAR_AT, MEMHHA_AT, MEMHEA_AT registers). Reading Empty read-only function, able write. specified segment modified with PRG_AR command RESTORE command. Designation address segment same with MEMAR, MEMHHA, MEMHEA registers. segments accessed using series registers. sub-mode, Empty with data read with MEMAR register. When Empty reading/writing Access Bit, read start segment (segment number
Search Table
search operation executed segment table. search operation, comparison executed indicating segment number searched. segments which have indicated segment number effective entries become objects search compared with data. This search operation completed 80ns. searches multiple segments, user search operation. search, result, which operation between previous search results specified step search results, appears search result. example, when user specifies search operation second search step, entry which both first second step dealt with entry, Flag that start segment "1." detailed discussion search operation presented below. reader should refer Fig.5.4.1 easier understanding. This example one-entry 3-segment construction. total search operations executed. first search operation, segment number indicated, second search operation, segment number indicated search object. search operation defined second search operation. data bits) input into device through Input Port Port, used search operation. upper bits segment masked that only part "A1" used search operation, device defined execute search operation with segment first search operation, entries which have segment data "A1" segment number segment (entry hit, Flags start segments every entry "1." register holds entry address
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Address Processor KE5B256B1 Endian toggle pointer
toggle
side Segment data bits)
side
EAOFF 0:(toggle ON*1) Access object
toggle operation executed reading writing MEMAR, MEMHHA,and MEMHEA register. endian toggle function initial state after device reset, user accesses device start from side.
EAOFF 1:(toggle OFF)
Access object
Fig. 5.3.1 Endian function
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Address Processor KE5B256B1 highest priority (Highest Address) after search operation executed. this example, register holds entry address ("3") entry priority becomes higher upper device cascaded devices, becomes higher absolute address device becomes smaller. second search operation, data bits) introduced into device search data. segment defined search object, search defined. Therefore, second search "B1," some entries (entry which have "B1" segment number hit. this example, entry entry entries. User execute search operation plural segments with data which many bits. shown this example, when length data multiple bits, search operation executed with data length using mask capability. segment number search defined every search operation independently, segment used search operation need close. search operation indicated, search result which independent previous search result appears. entries (entry number which have segment data "B1" segment when search defined second search step. case search operation through Input Port search), segment number search IG<2:0> bits register, case search through Port (CPU search), CG<2:0> bits CPUSRS register. search operation, search steps executed search sequence. Users define segment number every search step independently. maps registers presented Chapter register address which highest priority address (Highest Address) entries. Fig. 5.4.1, entry address "3H" stored register entry No.1 first search result. After second search operation, entry address "6H" entry stored register. After search operation, user learn address entry reading register. segment entry accessed with index which register. detail discussion presented Chapter register address which highest priority address (Highest Empty Address) empty entries. Fig. 5.4.1, entry highest priority empty entry, entry address "7F5H" entry stored register. table maintenance, example appending entry, executed with index which register. Chapter detail discussion. mentioned above, device supports mask capability data, designating segment search every search operation, search operation. Therefore, device handle various search operations flexibly. example here 3-segment construction, other cases same.
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Input Port
Port
Address Processor KE5B256B1
Search data Segment number search Search data Upper bits masked Segment search
Segment number
Entry number Entry No.0 Entry No.1 Entry Entry Entry
Entry address
Entry Entry Empty area Remaining segment Entry Entry Entry
7F2H 7F5H 7F8H 7FBH 1800H
Entry 2727 Remaining segment
1FFBH
Hit, Multi-hit, etc. HSTAT register
MEMHHA register Search result
register
7F5H register
Output Port
Port Fig. 5.4.1 Search table
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Address Processor KE5B256B1
Input Port
Sequence Configuration
Two-channel Structure
Input Port used inputting data. search sequencer starts with writing data into Input Port pulse input), maximum 8-step search operation executed synchronously with pulse automatically. This search sequence sequence) programmable data formatting, start search timing, segment location search. also indicates mask independently with every step. When search described Chapter defined, search operation data over bits executed. This sequence definition called sequence configuration. detailed discussion sequence configuration sequence presented this chapter.
search sequencer Input Port 2-channel structure which channel (Ach) channel (Bch), independent channels defined. These channels used with changing channels. Furthermore, when multi-channel configuration which define maximum independent sequences used, various search sequences executed, shown below. Since user define plural sequences beforehand, there overhead operation which renews configuration changing configurations. following registers define sequence. These registers prepared channels. maximum steps defined every channel independently. register (CUT0L/CUT0H, CUT1L/CUT1H) register (SS0L/SSOH, SS1L/SS1H) register (CS0~CS7) MASK register (MASK0L/MASK0H MASK7L/MASK7H) above registers, both register register mapped same address. User access channel (inactive channel), which selected sequencer, reading/writing these pointed registers. That say, when being used, register accessed, when being used, register accessed. Therefore, while side channel used, other side channel defined. Section detailed discussion.
Input Port Configuration
port width bits, configured bits. When bits configured, bits side ID<31:0> used. case bits, ID<15:0> effective. case bits, ID<7:0> effective. polarity pulse programmable. When polarity positive, data ID<31:0> acquired internal buffer with positive edge pulse. other hand, case negative polarity, data acquired with negative edge, search operation starts synchronously with pulse. width Input Port defined IW<1:0> bits CNTL register. polarity pulse defined CNTL register.
Address Processor KE5B256B1 Content Configuration detailed discussion configuration presented this section. Through data acquired into device synchronously with pulse according definition. data which acquired with pulse, whose width defined Input Port width, called data block. device function which acquires necessary data blocks sequence data maximum data blocks. This function called Through function. User define 64-bit register (divided CUT0L, CUT0H, CUT1L, CUT1H registers every bits) according which data block acquired. There explanation Through function Fig. 6.2.1 (a). This example shows that Input Port width bits. 8-bit data block, which input with first clock after sequence reset operation, treated block CT<0> register determines whether data acquired. Similarly, every register corresponds every data block. Only data blocks which correspond acquired. this example, blocks acquired. Fig. 6.2.2 shows 16-bit width Input Port case Fig. 6.2.3 shows 32-bit width case. They same Fig. 6.2.1 except that acquired data bits bits. Data Accumulation data blocks acquired Through function stored into 32-bit Accumulation Buffer sequential order from least significant bit. When pulse applied after 32-bit Accumulation Buffer space which data blocks stored (Buffer full), content Accumulation Buffer moves into Subaccumulation Buffer newly acquired data block stored side. Next, when Accumulation Buffer full, acquired data block stored higher side previous acquired data block. However, buffer full, data stored side Accumulation Buffer after content Accumulation Buffer moves into Sub-accumulation Buffer. After this, operation repeated every data block inputting. When content Accumulation Buffer moves into Sub-accumulation Buffer, previous acquired data block purged. general process called Data Accumulation, executed device automatically with data acquisition Through function. Fig. 6.2.1 shows that first acquired data blocks (block input into Accumulation Buffer 8-bit unit. When (block data block acquired, content Accumulation Buffer moves into Sub-accumulation Buffer, because Accumulation Buffer space. Data blocks after this block acquired into Accumulation Buffer same manner first four blocks. Therefore, when block (block acquired, status buffers becomes that shown Fig. 6.2.1 (c). case data blocks (Fig.6.2.2), data blocks (Fig.6.2.3), move into Sub-accumulation Buffer occurs after every second data block acquisition bit), after each data block acquisition bit). Accumulation Buffer Sub-accumulation Buffer have newest 64-bit data. User makes data search operation with 32-bit selected data 64-bit data.
Address Processor KE5B256B1
Data block bits) (8x64) bits 8bits 8bits 8bits 8bits Accumulation Buffer 8bits 8bits 8bits Sub-accumulation Buffer Input data stream register register 8bits
Search window
0-byte 1-byte 2-byte 3-byte
shift shift shift shift
Search data bits segment
Concept data formatting
8bits 8bits Accumulation Buffer 0-byte 1-byte 2-byte 3-byte shift shift shift shift 8bits 8bits 8bits 8bits
Sub-accumulation Buffer
Search window
Search data bits)
8bits 8bits
data first search operation
8bits 8bits Accumulation Buffer 0-byte 1-byte 2-byte 3-byte shift shift shift shift
Sub-accumulation Buffer
Search window
Search data bits)
data second search operation Fig. 6.2.1 Input data formatting example (Input Port width 8bits)
Address Processor KE5B256B1
Data block bits) (16x64) bits
Input data stream
register register
8bits 8bits 8bits 8bits Accumulation Buffer 8bits 8bits 8bits Sub-accumulation Buffer
8bits
Search window
0-byte 1-byte 2-byte 3-byte
shift shift shift shift Search data bits segment
Fig. 6.2.2 Input data formatting example (Input Port width 16bits)
Data block bits) (32x64) bits
Input data stream
8bits
8bits 8bits 8bits
8bits
register register
8bits 8bits 8bits
Accumulation Buffer
Sub-accumulation Buffer
Search window
0-byte 1-byte 2-byte 3-byte
shift shift shift shift Search data segment
Note: 64-bit data stored data blocks However, definition search operation with register occurs only time. this figure, search data stand data blocks. necessary define search window appropriately.
Fig. 6.2.3 Input data formatting example (Input Port width 32bits)
Address Processor KE5B256B1 Search Start register points timing start search operation (Search Start). register like register, 64-bit width register (divided SS0L, SS0H, SS1L, SS1H registers every bits). search operation starts when data blocks which correspond location (defined "1") register input. Fig. 6.2.1 "1." When either block block input, search operation starts. mentioned above, possible execute maximum 8-step search operation sequence. Therefore, number bits which defined register high register 64-bit register, user define Search Start timing data blocks input timing. When search operation starts according definition register, search operation executed according definition following register MASK register. There explanation about Through, Data Accumulation, Search Start again with referring Fig. 6.2.1 below. first block acquired with first pulse. However, SS<0> register "1", search operation executed this time. When block acquired with pulse, SS<2> "1," first search operation executed. (See Fig. 6.2.1 (b)) When blocks acquired with pulses, Accumulation Buffer space. when block acquired with pulse, content Accumulation Buffer moves into Sub-accumulation Buffer. Block stored Accumulation Buffer same time. However, since bits register which correspond these data blocks "1," search operation executed. When block acquired with 10th pulse, SS<9> register "1," second search operation executed. (See Fig. 6.2.1 (c)) Fig. 6.2.2 Fig. 6.2.3 case 16-bit width Input Port 32-bit definition. mentioned above, when search operation starts according definition register, search operation executed according definition following MASK registers. There eight registers (CS0 CS7) eight MASK registers (MASK0 MASK7). Every register corresponds sequences numbered sequence pointer determines which search operation sequence number executed. pointer increased with every search operation according register which "1." structures MASK registers seen Fig. 6.2.4. detailed discussion these functions with reference Fig. 6.2.4 presented below. Search Window Search Window function which 32-bit data search taken from 64-bit data stored Accumulation Sub-accumulation Buffers. 32-bit window 64-bit data, continuous 32bit data taken data. location window define four kinds byte unit. detailed discussion Search Window with reference Fig. 6.2.1 presented. case 0-byte shift, 4-byte data used search data. case 1-byte shift, lower 3-byte Accumulation Buffer upper 1-byte Sub-accumulation Buffer selected. Similarly, case 2-byte shift, lower 2-bytes Accumulation Buffer upper 2-bytes Sub-accumulation Buffer selected.
Address Processor KE5B256B1 register MASK register MASKH register 32bits 1bit (Sequence number) Sequence pointer Mask data Search window data Access flag Search head flag Search segment number sequence flag Fig. 6.2.4 register MASK register case 3-byte shift, lower 1-byte Accumulation Buffer upper 3-byte Sub-accumulation Buffer selected. This function useful take data adjusting data gap, when search data stands among input data blocks. Search Window executed setting byte shifting byte number SW<1:0> bits register which corresponds every search step. Fig.6.2.1 (c)), SW<1:0> bits "00" order that first search 0-byte shift mode. SW<1:0> "10" order that second search 2-byte shift mode. making data, which constructed with Through, Data Accumulation, Search Start, Search Window Set, called data formatting. data made data formatting stored register that data's sequence number, user confirm data every sequence reading register. There registers (CMP0 CMP7) which correspond sequence numbers every search operation. Definition Search Segment segment number search object defined with every search step sequence freely. numbers segment searched order this function. segment data defined segment number data compared among effective entries 3bits 1bit 1bit 2bits 16bits 16bits MASKL register
Address Processor KE5B256B1 data table definition search segment. segment number defined from "number segment entry definition search segment executed setting segment number into IG<2:0> bits register, which corresponds every sequence number. Mask Data mask operation executed 32-bit search data, which made data formatting, each according content mask data definition. bits whose corresponding mask data compared. mask data defined MK<31:0> bits MASK register, which correspond every sequence number. Fig. 6.2.1, upper 16-bit Accumulation Buffer does have input data first search operation (b), upper 16-bit location necessary masked protect wrong search operation unsettled data. this case, upper 16-bit mask data lower "0." second operation (c), mask data defined 32-bit data object comparison. Search Head Search When search data over bits search object stand among plural segments, user executes search operation. search operation Flag set, result search operations hit. search operation sequence defined with head flag (ISH bit) register. search step whose Search Head flag defined executed independently with previous search result. other hand, search step whose search head flag defined "0," search operation with previous search result executed. result step which search defined search result with previous search results. User must Search Head flag first search step. search operation defined series search operations from sequence number step whose Search Head flag defined "1," until sequence before next appears. Some Search Head flags defined sequence. other hand, previous search result purged search operation whose Search Head flag "1," case confirming search result, user needs take result before next search operation. Access Access means past career results described Chapter Access determines whether search result reflects Access Bits every entry. When Access flag (IAC bit), which corresponds sequence number, "1," each entry's Access Bits "1." other hand, when "0," Access holds previous state. Access which once cleared until Purge RST_AC command executed. Using career stored Access Bit, user simultaneously erase entries which have have careers with command table maintenance (PRG_NAC PRG_AC). Furthermore, when search indicated, user needs careful about indicating Access Bit. example, user indicates search execute 64-bit comparison with search operation indicate Access (IAC "1"), Access Bits entry which entries first search operation "1." Therefore, remaining bits hit, Access holds previous status ("1"). result this search operation
Address Processor KE5B256B1 outputs after search operation, user must Access (IAC "1") only second step. mentioned above, when search operation defined indicating Access Bit, user needs Access (IAC "1") last step. End-of-sequence sequence indicated with End-Of-Sequence flag (EOS bit) register. When search step whose completes, sequence completes. pulses after sequence ignored. When sequence pointer cannot detect endof-sequence (EOS "1"), sequence cannot complete there possibility mis-operation. Therefore, user must register corresponding fitted step. mentioned above, after setting Through register, setting executing timing (the Search Start) register, setting content every step MASK registers, configuration completed. Multi-channel Function previously stated, CUT, MASK registers prepared both Bch, user define kinds sequence. MASK registers have 16-step register total (because steps channels). User increase independent sequences steps (fully independent every step) maximum device effectively dividing sequence channels. This function called multi-channel function. multi-channel function realized setting sequence number freely. search step which indicated sequence pointer executed when data block whose Search Start indicated register acquired. initial value sequence pointer called sequence start number. sequence start number indicated pins setting value register timing sequence pointer reset. search operation executed order from indicated step every Search Start timing. sequence pointer stops step which end-of-sequence indicated. sequence then complete. configuration shown Fig. 6.2.5 necessary realize multi-channel function. end-of-sequence (EOS= "1") indicated plural steps, sequences divided into independent sequences every end-of-sequence. example, this example user selects sequence sequence number, 3-step sequence number (No.2 No.4) executed search operation. user selects sequence sequence number, sequence No.5 executed search operation. User define independent sequences number (Max. uses them with changing. However, definition Through Search Start common every channel, data block acquired search operation executed according definition registers though step selected sequence number. same. example, case example shown Fig.6.2.5, sequence divided into three sequence blocks. Search Starts defined first sequence block which sequences, device cannot execute step (the sequence No.4) sequence block. device cannot recognize sequence No.4 forever, sequence cannot completed. case multi-channel configuration shown Fig. 6.2.5, user needs define register which cor-
Address Processor KE5B256B1 responds maximum number sequence step (Ach Fig. 6.2.5). Furthermore, detailed description selection method channel start sequence number presented Section 6.3. Notice Configuration careful following item configuration: registers configuration which selected sequence (active channel) cannot accessed. opposite side accessed through Port. User needs careful which channel executing configuration. bits register must when Channel select corresponding bits register "1." execute search operation without data block acquisition.) maximum number steps, which defined same channel register, register. case search operation, careful where Access segment number search operation value which indicated Table Configuration. user uses value which different from value data, operation guaranteed. case segment structure, segment No.7 ("111") remaining segment cannot used segment search operation.
channel sequence
channel sequence
register MASK register
Sequence No.0
register MASK register
Sequence No.0
Sequence No.1
Sequence No.1
Start sequence No.select
Sequence No.2
Sequence No.2
Sequence No.3
Sequence No.3
Sequence No.4
Sequence No.4
Sequence No.5
Sequence No.5
Sequence No.6
Sequence No.6
Sequence No.7
Sequence No.7
Fig. 6.2.5 multi-channel configuration
Address Processor KE5B256B1 Define end-of-sequence with appropriate step. channel start sequence number defined freely user indicates error channel/start sequence, possible operate unexpectedly. registers sequence configuration have fixed initial values, recommend user configure unused registers strongly. Furthermore, software selection selected active channel initial state after device reset operation. both cases current selected channel confirmed reading IA<2:0> bits CNTL, HSTAT, ESTAT register. Furthermore, channel which selected accessed through Port. definition these registers also executed mode. Selection Start Sequence Number There methods select active channel Input Port: Hardware channel selection IPCH Software channel selection CNTL register When user indicates hardware channel selection, active channel selected IPCH pin. status IPCH latched into device timing sequence pointer reset operation (low pulse SQRST_ falling edge pulse SSQRST command). When latched signal level, channel selected. other hand, when latched signal high level, channel selected. signal IPCH changes after sequence pointer reset operation, channel changing does occur. When user indicates software channel selection, active channel selected definition IA<2:0> bits CNTL register. sequence pointer reset operation after register definition completes channel selection. sequence pointer reset operation necessary after register definition. determines which above methods used. When this "0," software selection selected. When this "1," hardware selection selected. There also methods select start sequence number: Hardware selection ISNM<2:0> Software selection CNTL register When user selects hardware selection, start sequence number selected IPN<2:0> bits CNTL register. This 3-bit defined sequence number recognized sequence pointer reset operation sequence number. both cases current selected sequence number confirmed reading IPN<2:0> bits CNTL register. When user changes method changing channel start sequence number writing CNTL register, channel start sequence number must recognized device sequence pointer reset operation selection method.
Selection Channel Start Sequence Number
Channel Selection
6-10
Address Processor KE5B256B1
Sequence Operation
Sequence Operation sequence search step every sequence number executed according sequence configuration described Section 6.2. internal sequence pointer controls which search step sequence number executed. sequence pointer constructed with increment counter. This counter initialized above-mentioned start sequence number sequence pointer reset operation (low pulse SQRST_ issuing SSQRST command) increases after step search operation. Through Search Start also initialized sequence pointer reset operation. right control returns register (CT<0>) register (SS<0>) (The right control returns CT<0> SS<0> according start sequence number.) sequence starts with first pulse after sequence pointer reset operation. data block acquired according definition register, search step executed according definition register. search step executed timing pulse which corresponds defined register. search step, which identical sequence number with sequence pointer, executed according definition register MASK register. value sequence pointer increased completion search step. Therefore, sequence number which executed next step forward previous step. search step executed order repeat repeating same process. After completion search operation which defined register, pointer stops
sequence complete. User confirm which sequence number complete IS<2:0> bits DEVSTAT register. pulses after sequence completion ignored until sequence pointer reset operation executed again. Search Results search results reflected four pins (HO_, PO_, SH0_, SH1_) five registers (CMP, HSTAT, HHA, MEMHHA, SH). description search results which indicated pins registers presented below. Output Pins After search operation, occurs, this outputs level, occurs, this outputs high level. Furthermore, this initialized sequence pointer reset operation holds previous status next search operation. After search operation, there multi-hit entry, this outputs level, there multi-hit entry, this outputs high level. Furthermore, this outputs DEVID priority signal DEVID sub-mode. This initialized sequence pointer reset operation holds previous status next search operation. SH1_, SH0_ pins These pins output results specified sequence number. SHASGEN register determines sequence number which search results output. User define independent sequence number SH0_ SH1_ register. Each outputs level result
6-11
Address Processor KE5B256B1 defined sequence number hit, becomes high impedance occurs (open drain output). case search, each outputs search results defined sequence number. Furthermore, SH0_ SH0_ pins initialized high impedance state sequence pointer reset operation. Fig. 6.4.1 shows example sequence process change above flag's outputs. this example, Input Port 16-bit width, pulse polarity negative, registers defined acquire data blocks execute search operation timing data blocks Sequence No.2 indicated start sequence number, sequence No.4 indicated end-of-sequence number. Furthermore, SH0_ defined output search result sequence No.2 SH1_ defined output search results sequence No.4 SHASGEN register. sequence occurred first pulse after sequence pointer reset operation. OPBUSY_/IPACT_ changes level. This means that sequence started. (When SP/TP_ low, this means that mode mode.) sequence executed synchronously with pulse every search operation executed with 3rd, 6th, pulses. pins change according this operation. other hand, SH0_ SH1_ pins change only indicated sequence number. SH0_ initialized high impedance state with sequence pointer reset operation. outputs search results after sequence No.2 search step executed with pulse, holds results. When sequence No.4 step executed with pulse holds result after this, SH_1 changes same manner above SH0_ pin. changes when next search operation executed. However, SH0_ SH_1 changes, when specified sequence number executed, hold results. Therefore, these pins useful monitoring middle results. sequence operation completion indicated when sequence operation complete with pulse OPBUSY_/IPACT_ becomes high level. case SP/TP_ "0," device returns mode.) specification every flag presented Chapter description OPBUSY_/IPACT_ changing timing presented here. start sequence, OPBUSY_/IPACT_ changes with first edge pulse. pulse polarity negative: negative edge; pulse polarity positive: positive edge) other hand, methods changing OPBUSY_/IPACT_ sequence defined below: With first edge pulse With second edge pulse second edge pulse positive edge when polarity negative, negative edge when polarity positive. case above, user always monitor OPBUSY_/IPACT_ signal with first edge pulse. However, when OPBUSY_/IPACT_ becomes high level, sequence fully complete. shows that sequence will complete with this cycle. case (2), OPBUSY_/IPACT_ becomes high level, sequence fully complete. Select this method user wishes control signal with OPBUSY_/IPACT_ pin. BUSY CNTL register determines which method user selects. When this "1," method selected, when this "0," method selected.
6-12
SQRST_
IPCH,ISNM<2:0> Sequence No.2(A-ch) CT<0>=0 SS<0>=0 CT<1>=1 SS<1>=0 CT<2>=1 SS<2>=1 CT<3>=0 SS<3>=0 CT<4>=1 SS<4>=0 CT<5>=1 SS<5>=1 CT<6>=1 SS<6>=0 CT<7>=1 SS<7>=1 CUT,SS register setting
ID<15:0>
Internal data
First search Sequence No.2
Second search Sequence No.3
Third search Sequence No.4
6-13
SH0_
Valid Valid Valid
Valid Valid
Valid Valid
SH1_ OPBUSY_/IPACT_
Valid
Address Processor KE5B256B1
SSQRST command also executed. case designating start sequence No.2(A-ch) hardware selection. polarity negative. Input Port width bits. (ID<31:16> don't care) results output every search operation.(AC characteristic HO_pin different from PO_'s. Chapter 14for details.) SH0_pin defined hit/miss sequence No.2. SH1_pin defined hit/miss sequence No.4 BUSY CNTLH register "1." BUSY CNTLH register "0." Fig.6.4.1 Sequence Operation timing example
Address Processor KE5B256B1 Register Outputs Register 32-bit data, which used every search step after formatting operations, stored CMP0 CMP7, depending Sequence number. HSTAT Register After search operation stores device, multihit device, cascaded system, multihit cascaded system, etc. Register After search operation stores entry address with highest priority. MEMHHA Register User read segment data, which stored entry address indicated register, outputting MEMHHA register. Register device-search results each step sequence stored. defined Sequence number executes search operation, register stores results search each sequence number. detailed above mentioned register presented Chapter content HSTAT register rewritten each search operation, content register changes according sequence number. this example, after search step sequence No.2 executed, CMP2 stores formatted data. After search step sequence No.3 executed, CMP3 stores formatted data. After search necessary assert pulse pulse outputting these registers with satisfied recovery time second edge (Min. 20ns) after Input Port cycle time (Min. 80ns). pulse satisfy this condition, there effective result. specifications about between pulse pulse pulse presented Section MEMHHA register cannot accessed through Port without moving mode when SP/TP_ pulled down. When SP/TP_ pulled external arbitration between pulse pulse necessary protect data destruction. Restarting Suspending Sequence mentioned above, when sequence complete, sequence pointer stops does receive pulse. user wishes start sequence again, execute sequence pointer reset operation. user wishes suspend sequence, execute sequence pointer reset operation. this time, necessary keep recovery time (Min. 20ns) from overlapping pulse SQRST_ pulse pulse SSQRST command). case internal arbitration with SP/TP_ pulled down, there case which above timing cannot kept because signal does synchronize with signal external device. this case, execute interrupt with SWCPUP_IM command. step sequence No.4 executed, CMP4 stores formatted data. above registers except register output through Output Port Port. User information sequence with pulse reading registers with pulse. register only read device select operation through Port.
6-14
Address Processor KE5B256B1 suspends sequence from next pulse cycle. However, this time, there pulse, device does recognize execute interrupt. Therefore, user needs suspend sequence with sequence pointer reset operation. "1," automatic output executed sequence No.7 channel. Chapter HHASGN register. Fig. 6.5.1 shows timing automatic output. automatic output function defined sequence No.7 No.2, every sequence hits. automatic output function defined sequence No.0, output OD<31:0> high impedance, though signal level. automatic output function defined sequence No.7 No.2 hits occur, output OD<31:0> bus. there this case, output high impedance. output holds current status until next search operation executed sequence executed. output while level. Basically, automatic output function defined only sequence number which expected have single hit. However, user control exclusively monitoring pins output every device, chance single chip multi-hit occurring problem (The highest priority entry address device output.) spite automatic outputting, control Output Port changed device output defined sequence data when sequence starts with pulse. IPHA<7:0>, IPHB<7:0> bits HHASGN register when using automatic output function. device reset operation initializes HHASGN register "0000H," this function disabled initial status.
Automatic Output
device output content register OD<31:0> automatically optional sequence function sequence. called automatic output function. This function enabled setting HHASGN register. enables user output without applying pulse Output Port search operation with pulse. content HHAH (Device output OD<31:16> content HHAL (HHA device) output OD<15:0>. description presented Chapter When signal high level, OD<31:0> becomes high impedance according automatic output mode. When signal level automatic function enabled occurs, output. case cascaded system, only device which outputs HHA. However, when signal level, every OD<31:0> always driven high level. When using this function, user device basically application which only single hit, because when multi-device hits, output confliction OD<31:0> occurs. case using search operation which searches plural segments sequence, possible that multi-hit will occur middle sequence. Therefore, user define automatic output sequence number. User defines IPHA<7:0>, OPHB<7:0> bits HHASGN register corresponding sequence number automatic output. example, IPHA<0>
6-15
Address Processor KE5B256B1 Sequence No.0 ID<31:0> OD<31:0> Valid automatic output sequence No.1 No.2 Fig. 6.5.1 automatic output Valid Valid Valid Valid Sequence No.1 Sequence No.2
6-16
Address Processor KE5B256B1
Output Port
Output Port port outputting search results. Output port sequencer, does Input port. sequencer starts output search results OD<31:0> according defined procedure, when pulse applied after sequence search through port. output status, entry address, entry data, Search data used either sequence sequence. defining results which output number results which output called sequence configuration. this chapter, both sequence configuration sequencer works explained.
same address. When registers these address read/ written, registers unselected channel read/ written. sequence unselected channel defined even while sequence selected channel executed. Section about channel selection. Configuration assignment AOSC registers sequence definition shown Fig. 7.1.1 Fig. 7.1.2, examples sequence configuration described below. Selecting Search Results Output search results output OD<31:0> data five registers, register, HSTAT register register, MEMHHA register, MEMHHA register. information about register output registered registers. There eight registers, AOC0 AOC7, each register corresponds sequence numbers respectively. OR<7:0> each register determines address register output. (For example output HSTAT register.) According these configurations, search results output from OUTPUT port step step. sequence number executed pointed sequence pointer, sequence pointer incremented each step sequence executed. initial value sequence pointer (the start sequence number) selected from explanation this function described later. explanation each register which stores search results described below: Register (Address: A0H, A2H, AEH)
Sequence Configuration
Two-channel Structure independent, different sequences defined, because sequencer also Two-Channel structure (Ach/Bch) similar sequencer. These sequences selected time. More than three sequences defined executed using multi-channel configuration. multi-channel configuration used with specifying start sequence number like sequence. Plural sequences defined advance, there overhead process like reconfiguration when sequence changed. following registers relate definition sequence. These registers prepared channels, eight step sequence maximum defined independently channels. register (AOC0 AOC7) AOSC register (AOSC0 AOSC7) These registers mapped
data used each step sequence stored.
Register (Sequence Number) Sequence pointer bits
Address Processor KE5B256B1 bits
Register output register HSTAT register register MEMHHA register MEMHHA register ONE/ALL_flag Mixing method(MX1,MX0) Sequence flag(EOS) Fig.7.1.1 AOC(Automatic Output Control)register AOSC Register (Sub-sequence Number) Sub-sequence pointer Segment number output Mixing method (MXS1,MXS0) Sub-Sequence flag (EOSS) Fig.7.1.2 AOSC(Automatic Output Sub-Control)register bits 3bits
Address Processor KE5B256B1 HSTAT Register (Address 90H) Four kinds search result information stored: device, Multi-Hit device, cascaded system, Multi-Hit cascaded system, information active channel IP/OP sequence. HSTAT register mixed with output data other registers (CMP, HHA, MEMHHA, HHA&MEMHHA registers). Register (Address: 94H) Entry address with highest priority stored. MEMHHA Register (Address 0EH) content entry stored. AOSC register specifies segment number entry output. segment number specification described later section. HHA&MEMHHA Register (Address B0H) register MEMHHA register output turn address HHA&MEMHHA register register. content register output first then that MEMHHA register output each entry. AOSC register specifies segment number entry output. HHA&MEMHHA register provided operation with automatic search result output through Output Port. cannot accessed through Port. series sequence, only three registers, HHA, MEMHHA, HHA&MEMHHA registers, defined registers. order specify registers, which have individual address each bits LSB/MSB side, address side (smaller address) must specified. address HHA&MEMHHA register B0H. ONE/ALL_ Flag search result normally output read cycle sequence number register. When MEMHHA register, register HHA&MEMHHA register register, possible select whether entries should read out. This done setting ONE/ALL flag register. ONE/ALL_ flag "0," "ALL," addresses contents entries output according priority. sequence pointer incremented while there entries remaining table. After output corresponding entry completed, data register shifted next higher address, accordingly, data HSTAT register outputs pins renewed. last output cycle, becomes high level, indicating output entries, sequence pointer incremented. ONE/ALL_ flag "1," "ONE," sequence pointer incremented after entry, which highest priority, output. should noted that data register shifted, data HSTAT register, along with outputs pins also renewed this case. case single hit, behavior sequencer same whether ONE/ALL_ flag "1." ONE/ALL_ flag must HSTAT register register output, because there "ALL output" these registers.
Address Processor KE5B256B1 Output Segment Number AOSC register specifies which segment should read MEMHHA register HHA&MEMHHA register register. There eight AOSC registers, AOSC0 AOSC7, each register corresponds sub-sequence number respectively. Eight segment numbers specified most. control sequence moves sub-sequence, which defined AOSC register, when sequence goes step involving either MEMHHA register HHA&MEMHHA register. sequence number incremented until sub-sequence completed. sub-sequence number executed indicated sub-sequence pointer, sub-sequence pointer incremented pulse given. initial value sub-sequence pointer selected from explanation which described later. sub-sequence pointer starts from start sub-sequence number counts sub-sequence number which sub-sequence (described later) set. ONE/ALL_ flag register "ONE," sub-sequence completed incrementation sub-sequence pointer stopped sub-sequence number which sub-sequence set. Then, control goes back sequence defined register sequence number incremented. ONE/ALL_ flag register "ALL," sub-sequence continues until steps between start sub-sequence number sub-sequence number which sub-sequence executed entries. sub-sequence pointer goes round between start sub-sequence number sub-sequence number which sub-sequence set. sub-sequence completed incrementation sub-sequence pointer stopped when sub-sequence number which sub-sequence last entry executed. Then control goes back sequence defined register, sequence number incremented. content output first then that MEMHHA (segment data), which specified AOSC registers, output each entry, HHA&MEMHHA register specified register. Mixed Output HSTAT Register HSTAT register mixed with upper bits output data (OD<31:28> OD<27:22>) when register except HSTAT register output. Table 7.1.1 shows HSTAT register mixed MX<1:0> register MXS<1:0> AOSC register. MXS<1:0> AOSC register given priority when MEMHHA register register. MX<1:0> used output MXS<1:0> used MEMHHA output, when HHA&MEMHHA register register. Sequence sequence specified End-OfSequence flag (EOS bit) register. sub-sequence specified End-Of-Sub-Sequence flag (EOSS bit) AOSC register. EOSS AOSC register "1," step where EOSS point subsequence, sub-sequence end. When step that completed, sequence ended. output register that step MEMHHA HHA&MEMHHA, sequence ended when sub-sequence completed. ONE/ALL_ flag "ALL" that step, sequence ended when output entries completed. After sequence ended, pulse ignored. EOSS must suit-
Address Processor KE5B256B1
(MXS1) (MXS0)
Bits HSTAT register mixed OUTPUT port data
OD<31> OD<30> OD<29> OD<28> OD<27:25> OD<24:22>
mixed*1
mixed*1
active channel Device Device Device Multi-Hit Device Multi-Hit
active channel
System System
System Multi-Hit System Multi-Hit
mixed*1
active channel
active channel
data specified register AOSC register output. Table 7.1.1 Mixed output specified register AOSC register able register suitable AOSC register. Because might work correctly, sequence sub-sequence cannot detected. EOSS AOSC register must start sub-sequence number MEMHHA register HHA&MEMHHA register registers. sub-sequence pointer must pointed sub-sequence sub-sequence used because sequence ended when sequence sub-sequence detected. sequence used, recommended sequence sub-sequence avoid situation that sequence started accidentally with pulse given mistake ended. Multi-channel Configuration register AOSC register prepared Ach/Bch respectively previously described, sequences defined. There registers steps channels) register AOSC register respectively, multi-channel channel configuration sequence sequence multi-channel configuration. sequence multi-channel configuration realized setting start sequence number start sub-sequence number. Once step which indicated sequence pointer sub-sequence pointer) been executed, initial value sequence pointer named start sequence number, initial value subsequence pointer named start sub-sequence number. start sequence number start sub-sequence number sequence pointer sub-sequence pointer respectively sequence pointer reset. step start sequence number executed pointer incremented when first pulse given. Likewise when step which indicated sequence pointer executed pointer incremented pulse given. sequence pointer comes step output MEMHHA register, sequence pointer stays that step sub-sequence started from initial pointer sub-sequence number. segment data specified AOSC register then output
Address Processor KE5B256B1 register
sequence number sequence pointer Output register HSTAT(ONE) HHA(ALL) MEMHHA(ONE) HSTAT(ONE)
HHA&MEMHHA(ALL)
AOSC register
sub-sequence EOSS number Output segment
Segment Segment Segment sequence pointer
CMP2(ONE) CMP0(ONE) CMP1(ONE)
Fig. 7.1.3 Multi-channel configuration sub-sequence pointer incremented pulse given. When sub-sequence pointer comes step which sub-sequence set, sub-sequence completed sequence pointer moved next step. When sequence pointer arrives point where sequence set, sequence pointer stopped sequence ended. configuration shown Fig. 7.1.3. needed multi-channel configuration. sequence more than step, sequence separated plural independent sequences sequence end. sub-sequence also separated sub-sequence end. Various output achieved combination sequences sub-sequences. sequence number selected start sequence number, example Fig. 7.1.3, steps from sequence number executed sequence. this case, sub-sequence used because step output MEMHHA register HHA&MEMHHA register included sequence. sub-sequence used, sub-sequence must AOSC register start sub-sequence number detected start. this example, subsequence must AOSC0 register AOSC2, AOSC4, AOSC7). HSTAT register output defined AOC0 register when first pulse given, entry address highest priority output defined AOC1 register when second pulse given. next priority entry address output while entries exist with pulse, because ALL_/ONE_ flag AOC1 register "ALL." sequence ended when lowest priority entry address output. Only entry MEMHHA output start sequence number start sub-sequence number Because AOC2 register specified output MEMHHA "ONE," segments specified AOSC1 register AOSC2 register output. segment number output with first pulse segment number with second pulse. another start sub-sequence number selected same start sequence number segments different order output. start sequence number start sub-
Address Processor KE5B256B1 sequence number HSTAT register output first, followed highest priority entry address, then segment data entry output order segment segment address segment data entries output repeatedly until lowest priority entry output because AOC4 register specified output HHA&MEMHHA "ALL." Finally, CMP2 register output sequence ended. next section procedure select channel, start sequence number, start sub-sequence number. Remarks Configuration Only inactive channel registers configuration registers sequence (AOC, AOSC) accessed from port. sequence sub-sequence must appropriate step. sub-sequence used (not output MEMHHA HHA&MEMHHA), start sub-sequence number must sub-sequence number that sub-sequence set. sequence used, strongly recommended that start sequence number step that sequence set, start sub-sequence number step that sub-sequence set. HSTAT register register specified output step sequence, ONE/ALL_ flag must "ONE." Only registers, MEMHHA register, HHA&MEMHHA register output sequence which divided sequence end. Unexpected action will occur wrong channel wrong start sequence number selected. strongly recommended value registers sequence configuration some registers used, because registers sequence configuration don't have initial value.
Selection Channel Start Sequence Number
Channel Selection There methods selecting active channels (Ach Bch) Output Port follows: Hardware channel selection OPCH Software channel selection CNTL register Hardware channel selection used select active channels OPCH inputs. states OPCH registered Sequence Pointer Reset falling edge SQRST_ falling edge when SSQRST command executed). registered signal then selected, signal high then selected. selected channels changed until next Sequence Pointer Reset executed SQRST_ pulse SSQRST command. Software channel selection used select active channel OA<2:0> CNTL register. Software channel selection completed when Sequence Pointer Reset done after CNTL register set. Sequence Pointer Reset must done after CNTL register set. Whether Hardware Software channel selection used determined CNTL register. Software channel selection used when "0," Hardware channel selection used when "1." After device reset, Software channel selection ch-A selected initial value.
Address Processor KE5B256B1 currently selected (active) channel Output Port confirmed reading data OA<2:0> CNTL, HSTAT ESTAT registers regardless method selecting active channel. registers sequence configuration inactive channel accessed through port mode another mode. Start Sequence Number Selection Start Sub-sequence number Selection There methods select start sequence number start sub-sequence number. should known that these methods different from methods select sequence number. Start sequence number start sub-sequence number Numbers defined CNTL register used start sequence number start sub-sequence number signal level OPNS selects which method used. OPNS low, sequence starts from sequence number sub-sequence number OPNS high, OPN<2:0> CNTLH register used start sequence number OPNS<2:0> CNTLH register used start sub-sequence number sequence start. OPN<2:0> OPSN<2:0> bits CNTLH register "000" initial point after device reset. these bits written after device reset, start sequence number start sub-sequence number both spite signal level OPNS pin. sequence pointer reset must done after channel selection method, selection method start sequence number changed writing CNTL register. selection method channel start sequence number recognized sequence pointer reset.
Sequence Operation
sequence pointer sub-sequence pointer reset sequence pointer reset (SQRST_ pulse SSQRST command) sequence same manner sequence. initial values sequence pointer sub-sequence pointer start sequence number start sub-sequence number respectively. first pulse after sequence pointer reset starts sequence. sequence executed order sequence number from start sequence number output data defined register, OD<31:0>. sequence ends when step sequence end, which register, been executed. pulse ignored after sequence until sequence pointer reset executed. Invalid data output according sequence definition when search result mishit. Once sequence starts, sequence doesn't until sequence step executed, even case mishit. Fig. 7.3.1 shows example when start sequence number start sub-sequence number configuration like Fig. 7.1.3. There entries, entry entry level indicate multi-hits before sequence execution. start sequence number start sub-sequence number sequence pointer subsequence pointer respectively sequence pointer reset execution. There need execute sequence pointer reset just before sequence start. example, sequence pointer reset executed before sequence, only start sequence number also start sequence number start subsequence number that time. result,
SQRST_
OPCH ,OPNS
OPNS=1 chnnel)
OD<31:0> HSTAT MEMHHA Segment MEMHHA Segment MEMHHA Segment MEMHHA Segment CMP2
entry
entry
IPBUSY_/OPACT_
Address Processor KE5B256B1
sequence pointer reset done before sequence start,there need sequence pointer reset before sequence. cannel selected sequence pointer reset, start sequence number start sequence number recognized OPNS signal. Both start numbers stored <2:0> OPNS <2:0> CNTLH register respectively. When OE_is High, output high impedance. When CNTLH register BUSY When CNTLH register BUSY
Fig. 7.3.1 Timingexample sequence
Address Processor KE5B256B1 sequence started continuously after sequence end, when search result output after sequence. sequence takes place sequence pointer sub-sequence pointer incremented data output according definition register AOSC register. first pulse starts sequencer, IPBUSY_/OPACT_ changes level indicate that sequence starting. (When SP/TP_ device enters mode this time.) contents HSTAT register output this pulse sequence pointer incremented. subsequence starts with second pulse entry address entry output. segment entry output third pulse. segment entry output fourth pulse, output entry ended. signal goes high level this time indicates that entry remaining table. entry address entry output fifth pulse segment entry output sixth pulse. Segment entry output seventh pulse output entry ended. signal goes high level this time indicates that entry remaining table. sub-sequence ended this time sub-sequence pointer stopped control returns sequence. search data stored CMP2 registers output eighth pulse. this cycle, sequence pointer stopped, sequence ends, IPBUSY_/OPACT_ goes high level. timing changing IPBUSY_/OPACT_ sequence following ways: triggered first edge (falling edge) pulse triggered second edge (rising edge) pulse selected, timing changing IPBUSY_/ OPACT_ unified first edge (falling edge) pulse sequence start sequence end, timing monitor IPBUSY_/OPACT_ easy design. However, sequence completely ended timing when IPBUSY_/OPACT_ goes high. indicates that sequence will ended this cycle. When "ALL output" there multi-hits, sometimes can't known many times pulse will given. When IPBUSY_/OPACT_ monitored determine further pulse should given not, more efficient timing designed because using allows timing determined earlier. selected, IPBUSY_/OPACT_ goes high level when sequence completely ended. Method recommended when IPBUSY_/OPACT_ signal used control other signal generation. BUSY CNTL register selects which timing being used. Method selected when selected when "1". setting common IPBUSY_/OPACT_ OPBUSY_/ IPACT_. Suspension Resumption sequence After sequence ends, described before, sequence pointer sub-sequence pointer stopped pulses ignored. sequence pointer reset must executed start sequence again. sequence pointer reset should executed suspend sequence. rule recovery time (Min. must kept avoid overlappi
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