Intelligent 104-Bit EEPROM Counter 20000 Units with Security Logic

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Intelligent 104-Bit EEPROM Counter 20000 Units with Security Logic

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IZ4406
Intelligent 104-Bit EEPROM Counter 20000 Units with Security Logic
organisation Three memory areas with special characteristics ROM, PROM, EEPROM) Maximum 20480 count units Special security features Minimum write/erase cycles Data retention minimum years Contact configuration serial interface accordance standard 7816-3 (synchronous transmission)
Definitions Functions Card Contact
Symbol
Function
Bidirectional data line (open drain) Code entry "Input" only transport Clock input Control input (reset) Supply voltage N.C. connected Ground IZ4406 comes wire-bonded module embedding plastic cards customer packaging
General Description
chip contains EEPROM/PROM bits, mask bits sequencing control with security logic block diagram, Fig. Memory (104 bits) divided into following functional areas This area contains unalterable chip data application, design status). Part data entered mask remainder when testing. Both parts unalterable. this area user enter card data particular application. control flag safeguard this area against alteration. This area contains count data stores current count nonvolatile memory. individual counter stages with carry erased EEPROM), only uppermost counter stage being erasable PROM). Before control flag set, part EEPROM area contains secret transport code. Another part serves error counter. Function PROM area: Control flag bit: bits: Test bits manufacturer bits: user condition supplied, transport code error counter activated. chip only read (except transport-code area) only error counter written. Following correct entry transport code, entire memory read areas written EEPROM part area erased.
PROM PROM/EEPROM
IZ4406
After control flag been written, everything readable only area programmed, with following changes: transport code error counter longer activated. area former transport code error counter erased byte byte with carry. entire area written
When control flag written, counter stage below (the error counter) erased same time (see "Erasing Memory Byte with Carry").
Column Decoder, 1-out-of-8 (A0-A2)
Address Counter
Line Decoder
Counter Bits Blockable PROM Bits Manufacturer Data Bits
1-out-of-13 (A3-A6)
(RAM, EEPROM)
Chip Control, Security Logic
IEB01328
Figure Block Diagram
Absolute Maximum Ratings Parameter
Supply voltage Input voltage Storage temperature Power dissipation
Symbol
Tstg Ptot
Limit Values Min. Max.
-0.3 -0.3
Unit
Comments
IZ4406
Operating range Parameter
Supply voltage Ambient temperature
Symbol
Limit Values Min. Max.
4.75
Unit
Comments
Characteristics Parameter Symbo Min. Limit Values Typ. Max. Unit Test Condition
Supply
Supply voltage Supply current 4.75
Data Input
H-Input voltage (I/O,CLC,P,RST) L-Input voltage (I/O,CLC,RST) L-Input current (CLK) (VH=5 internal pull-down) L-Input current (RST) (VH=0 internal pull-up)
Data Output
L-Output current (VH=0.5 open drain) H-Output current (VH=5 open drain)
Pulse Duration
(address reset) (set flag) (count, H-level) (count, L-level) (write, H-level) (erase, H-level)
Characteristics
Delay time Delay time Delay time Delay time Delay time Delay time Delay time td10 td3, td4, td6,

Intelligent 104-Bit EEPROM Counter 20000 Units with Security Logic

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