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Volt Intel® Advanced+ Boot Block Flash Memory (C3) Stacked-Chip Scale Package Family
Flash Memory Plus SRAM Reduces Memory Board Space Required, Simplifying Design Complexity Stacked-Chip Scale Package (StackedCSP) Technology Smallest Memory Subsystem Footprint Area 16Mbit (0.13 Flash 2Mbit 4Mbit SRAM Area 32Mbit (0.13 Flash 4Mbit 8Mbit SRAM Height 1.20 16Mbit (0.13 Flash 2Mbit 4Mbit SRAM 32Mbit (0.13um) Flash 8Mbit SRAM Height 1.40 32Mbit (0.13 Flash 4Mbit SRAM This Family also includes 0.25 0.18 technologies Advanced SRAM Technology Access Time Power Operation Voltage Data Retention Mode Intel® Flash Data Integrator (FDI) Software Real-Time Data Storage Code Execution Same Memory Device Full Flash File Manager Capability
Advanced+ Boot Block Flash Memory Access Time Instant, Individual Block Locking Protection Register Production Programming Ultra Fast Program Erase Suspend Extended Temperature Blocking Architecture Block Sizes Code Data Storage 4-Kword Parameter Blocks (for data) 64-Kbyte Main Blocks (for code) 100,000 Erase Cycles Block Power Operation Async Read Current: (Flash) Standby Current: (Flash) Automatic Power Saving Mode Flash Technologies 0.25 ETOXVI, 0.18 ETOXVII 0.13 ETOXVIII Flash Technologies 28F160xC3, 28F320xC3
Volt Intel® Advanced+ Boot Block Flash Memory (C3) Stacked-Chip Scale Package (Stacked-CSP) device delivers feature-rich solution low-power applications. Stacked-CSP memory device incorporates flash memory static package with voltage capability achieve smallest system memory solution form-factor together with high-speed, low-power operations. Stacked-CSP memory device offers protection register flexible block locking enable next generation security capability. Combined with Intel® Flash Data Integrator (Intel® FDI) software, Stacked-CSP memory device provides cost-effective, flexible, code plus data storage solution.
Notice: This document contains information products production. specifications subject change without notice. Verify with your local Intel sales office that have latest datasheet before finalizing design.
252636-001 February, 2003
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Contents
Contents
Introduction.7 Document Conventions Product Overview Package Ballout.8 Signal Definitions Operation 2.1.1 Read 2.1.2 Output Disable 2.1.3 Standby.12 2.1.4 Flash Reset.13 2.1.5 Write Read Array (FFh) Read Identifier (90h) Read Status Register (70h) 3.3.1 Clear Status Register (50h) Query (98h) Word Program (40h/10h) 3.5.1 Suspending Resuming Program (B0h/D0h).15 Block Erase (20h) 3.6.1 Suspending Resuming Erase (B0h/D0h) Block Locking.18 3.7.1 Block Locking Operation Summary.19 3.7.2 Locked State 3.7.3 Unlocked State 3.7.4 Lock-Down State 3.7.5 Reading Block's Lock Status 3.7.6 Locking Operation during Erase Suspend 3.7.7 Status Register Error Checking Protection Register 3.8.1 Reading Protection Register 3.8.2 Programming Protection Register (C0h).21 3.8.3 Locking Protection Register Power-Up/Down Characteristics.23 Additional Flash Features 4.2.1 Improved Volt Production Programming 4.2.2 F-VPP VPPLK Complete Protection.23 Absolute Maximum Ratings Operating Conditions Capacitance
Principles Operation
Flash Memory Modes Operation.13
Power Reset Considerations
Electrical Specifications
Contents
5.10 5.11
Characteristics. Flash Characteristics. Flash Characteristics-Write Operations. Flash Erase Program Timings(1). Flash Reset Operations SRAM Characteristics-Read Operations. SRAM Characteristics-Write Operations SRAM Data Retention Characteristics-Extended Temperature
Migration Guide Information System Design Considerations. Background. 7.1.1 Flash SRAM Footprint Integration 7.1.2 Advanced+ Boot Block Flash Memory Features Flash Control Considerations 7.2.1 F-RP# Connected System Reset. 7.2.2 F-VCC, F-VPP F-RP# Transition Noise Reduction Simultaneous Operation 7.4.1 SRAM Operation during Flash "Busy" 7.4.2 Simultaneous Operations Printed Circuit Board Notes System Design Notes Summary.
Appendix Program/Erase Flowcharts Appendix Query Structure Appendix Word-Wide Memory Diagrams Appendix Device Table Appendix Protection Register Addressing. Appendix Mechanical Shipping Media Details. Appendix Additional Information Appendix Ordering Information.
Contents
Revision History
Date Revision 02/11/03 Version -001 Description Initial release, Stacked-Chip Scale Package
Contents
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Introduction
This document contains specifications Volt Intel® Advanced+ Boot Block Flash Memory (C3) Stacked-Chip Scale Package (Stacked-CSP) device. Stacked memory solutions offered following combinations: 32-Mbit flash 8-Mbit SRAM, 32-Mbit flash 4-Mbit SRAM, 16-Mbit flash 4-Mbit SRAM, 16-Mbit flash memory 2-Mbit SRAM.
Document Conventions
Throughout this document, following conventions have been adopted.
Voltages: "2.7 refers full voltage range, V-3.3V; refers 11.4 12.6 Main block(s): 32-Kword block Parameter block(s): 4-Kword block
Product Overview
Stacked-CSP device combines flash SRAM into single package, provides secure low-voltage memory solutions portable applications. This memory family combines memory technologies, flash memory SRAM, package. flash memory delivers enhanced security features, block locking capability that allows instant locking/unlocking flash block with zero-latency, 128-bit protection register that enable unique device identification, meet needs next generation portable applications. Improved production programming used improve factory throughput.
Table
Block Organization (x16)
Memory Device 32-Mbit Flash 16-Mbit Flash 2-Mbit SRAM 4-Mbit SRAM 8-Mbit SRAM NOTE: words bits each. Kwords 2048 1024
flash memory asymmetrically-blocked enable system integration code data storage single device. Each flash block erased independently others 100,000 times. flash eight 8-KB parameter blocks located either (denoted suffix) bottom suffix) address order accommodate different microprocessor protocols kernel code location. remaining flash memory grouped into 32-Kword main blocks. individual flash block locked unlocked instantly provide complete protection code data (see Section 5.7, "Flash Erase Program Timings(1)" page details). flash contains both Command User Interface (CUI) Write State Machine (WSM). serves interface between microcontroller internal operation flash memory. internal automatically executes algorithms timings necessary
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
program erase operations, including verification, thereby unburdening microprocessor microcontroller. flash's status register indicates status signifying block erase word program completion status. Flash program erase automation allows program erase operations executed using industry-standard two-write command sequence CUI. Program operations performed word increments. Erase operations erase locations within block simultaneously. Both program erase operations suspended system software order read from other flash block. addition, data programmed another flash block during erase suspend. Stacked-CSP memory device offers low-power savings features: Automatic Power Savings (APS) flash memory standby mode flash SRAM. device automatically enters mode following completion read cycle from flash memory. Standby mode initiated when system deselects device driving F-CE# S-CS1# S-CS2 inactive. Power savings features significantly reduce power consumption. flash memory reset lowering F-RP# GND. This provides CPU-memory reset synchronization additional protection against noise that occur during system reset power-up/-down sequences.
Package Ballout
Figure 66-Ball Stacked Chip Scale Package
F-VSS F-VCCQ
DQ15 S-WE# DQ14 DQ13
F-WE# S-VSS F-RP# F-WP# F-VPP S-LB# S-UB# S-OE# F-CE# F-VSS F-OE# S-CS1# DQ11 DQ10 DQ12 S-CS2 S-VCC F-VCC
View, Balls Down
NOTES: Flash upgrade balls shown (64-Mbit flash) (128-Mbit flash). flash SRAM combinations, balls populated lower density devices. (Upper address balls populated). Ball location "NC" 16/2 devices only.
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
maintain compatibility with JEDEC Variation options this ball location this land should connected directly land ball (A17).
Signal Definitions
Table defines signal definitions shown previous ballout.
Table
Symbol
Volt Intel® Advanced+ Boot Block Stacked-CSP Ball Descriptions (Sheet
Type Name Function ADDRESS INPUTS memory addresses. Addresses internally latched during program erase cycle. 2-Mbit A[16:0]
A[20:0]
INPUT
4-Mbit A[18:0] 16-Mbit A[19:0] 32-Mbit A[20:0] DATA INPUTS/OUTPUTS: Inputs array data SRAM write operations second F-CE# F-WE# cycle during flash program command. Inputs commands flash's Command User Interface when F-CE# F-WE# asserted. Data internally latched. Outputs array, configuration status register data. data balls float tri-state when chip de-selected outputs disabled. FLASH CHIP ENABLE: Activates flash internal control logic, input buffers, decoders sense amplifiers. F-CE# active low. F-CE# high de-selects flash memory device reduces power consumption standby levels. SRAM CHIP SELECT1: Activates SRAM internal control logic, input buffers, decoders sense amplifiers. S-CS1# active low. S-CS1# high de-selects SRAM memory device reduces power consumption standby levels. SRAM CHIP SELECT2: Activates SRAM internal control logic, input buffers, decoders sense amplifiers. S-CS2 active high. S-CS2 de-selects SRAM memory device reduces power consumption standby levels. FLASH OUTPUT ENABLE: Enables flash's outputs through data buffers during read operation. F-OE# active low. SRAM OUTPUT ENABLE: Enables SRAM's outputs through data buffers during read operation. S-OE# active low. FLASH WRITE ENABLE: Controls writes flash's command register memory array. F-WE# active low. Addresses data latched rising edge second F-WE# pulse. SRAM WRITE ENABLE: Controls writes SRAM memory array. S-WE# active low. SRAM UPPER BYTE ENABLE: Enables upper byte SRAM (DQ8-DQ15). S-UB# active low. SRAM LOWER BYTE ENABLE: Enables lower byte SRAM (DQ0-DQ7). S-LB# active low. FLASH RESET/DEEP POWER-DOWN: Uses voltage levels (VIL, VIH) control reset/deep power-down mode.
DQ[15:0]
INPUT OUTPUT
F-CE#
INPUT
S-CS1#
INPUT
S-CS2
INPUT
F-OE# S-OE# F-WE# S-WE# S-UB# S-LB#
INPUT INPUT INPUT INPUT INPUT INPUT
F-RP#
INPUT
When F-RP# logic low, device reset/deep power-down mode, which drives outputs High-Z, resets Write State Machine, minimizes current levels (ICCD). When F-RP# logic high, device standard operation. When F-RP# transitions from logic-low logic-high, device resets blocks locked defaults read array mode.
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Table
Symbol
Volt Intel® Advanced+ Boot Block Stacked-CSP Ball Descriptions (Sheet
Type Name Function FLASH WRITE PROTECT: Controls lock-down function flexible Locking feature. When F-WP# logic low, lock-down mechanism enabled blocks marked lockdown cannot unlocked through software.
F-WP#
INPUT
When F-WP# logic high, lock-down mechanism disabled blocks previously locked-down locked unlocked locked through software. After F-WP# goes low, blocks previously marked lock-down revert that state. Section 7.0, "System Design Considerations" page details block locking. FLASH POWER SUPPLY: [2.7 V-3.3 Supplies power device core operations. FLASH POWER SUPPLY: [2.7 V-3.3 Supplies power device operations. SRAM POWER SUPPLY: [2.7 V-3.3 Supplies power device operations. Section 7.2.2, "F-VCC, F-VPP F-RP# Transition" page details power connections. FLASH PROGRAM/ERASE POWER SUPPLY: [1.65 V-3.3 11.4 V-12.6 Operates input logic levels control complete flash protection. Supplies power accelerated flash program erase operations range. This ball cannot left floating. Lower F-VPP VPPLK, protect contents against Program Erase commands.
F-VCC F-VCCQ S-VCC
SUPPLY SUPPLY SUPPLY
F-VPP
INPUT SUPPLY
F-VPP F-VCC in-system read, program erase operations. this configuration, F-VPP drop 1.65 allow resistor diode drop from system supply. Note that F-VPP driven logic signal, 1.65 That F-VPP must remain above 1.65 perform in-system flash modifications. Raise F-VPP faster program erase production environment. Applying F-VPP only done maximum 1000 cycles main blocks 2500 cycles parameter blocks. F-VPP connected total hours maximum.
F-VSS S-VSS
SUPPLY SUPPLY
FLASH GROUND: internal circuitry. ground inputs must connected. SRAM GROUND: internal circuitry. ground inputs must connected. CONNECTED: Internally disconnected within device.
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Principles Operation
flash memory utilizes automated algorithms simplify program erase operations. automates program erase operations handling data address latches, WE#, system status requests.
Figure Volt Intel® Advanced+ Boot Block Stacked Chip Scale Package Block Diagram
F-VCC F-OE# F-CE# F-WP# F-RP#
Flash 28F160C3 28F320C3
F-VCCQ F-WE# F-VPP F-VSS
A[Max:0]
D[15:0]
S-VCC S-CS1 S-CS2 S-OE#
SRAM 8-Mbit
S-VSS S-WE# S-UB# S-LB#
Operation
cycles from Stacked-CSP conform standard microcontroller cycles. Four control signals dictate data flow flash component: F-CE#, F-OE#, F-WE# F-RP#. Four separate control signals handle data flow SRAM component: S-CS1#, S-CS2, S-OE#, S-WE#. These operations summarized Table Table
2.1.1
Read
flash memory four read modes: read array, read identifier, read status query. These flash memory read modes dependent F-VPP voltage. Upon initial device power-up after exit from reset, flash device automatically defaults read array mode. F-CE# F-OE# must asserted obtain data from flash component. SRAM read mode available. S-CS1#, S-CS2, S-OE# must asserted obtain data from SRAM device. Table Volt Intel Advanced+ Boot Block Flash Memory Stacked-CSP Operations" page summary operations.
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Table
Volt Intel Advanced+ Boot Block Flash Memory Stacked-CSP Operations
Flash Signals SRAM Signals Memory Output Memory Control
S-WE#
F-WE#
S-CS2
F-RP#
F-CE#
Modes
S-UB#,S-LB#(1)
S-OE1#
F-OE1#
S-CS1#
Notes
Read FLASH Write Standby Output Disable Reset Read Write SRAM Standby
SRAM must High SRAM mode allowable
Flash Flash Other Other Other SRAM SRAM Other Other Other
DOUT High High High DOUT High High High
2,3,4 4,5,6 4,5,6 4,5,7
FLASH must High
FLASH mode allowable Output Disable Data Retention same standby
NOTES: devices drive memory same time. SRAM placed into data retention mode lowering S-VCC range, specified.
2.1.2
Output Disable
With F-OE# S-OE# deasserted, Stacked-CSP outputs signals placed highimpedance state.
2.1.3
Standby
With F-CE# S-CS1# S-CS2 deasserted, Stacked-CSP enters standby mode, which substantially reduces device power consumption. standby, outputs placed highimpedance state independent F-OE# S-OE#. flash deselected during program erase operation, flash continues consume active power until program erase operation complete.
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
2.1.4
Flash Reset
device enters reset mode when driven low. reset mode, internal circuitry turned outputs placed high-impedance state. After return from reset, time tPHQV required until outputs valid, delay (tPHWL tPHEL) required before write sequence initiated. After this wake-up interval, normal operation restored. device defaults read array mode, status register 80h, read configuration register defaults asynchronous reads. taken during block erase program operation, operation will aborted memory contents aborted location longer valid.
2.1.5
Write
Writes flash take place when both F-CE# F-WE# asserted F-OE# deasserted. Writes SRAM take place when both S-CS1# S-WE# asserted S-OE# S-CS2 deasserted. Commands written flash memory's Command User Interface (CUI) using standard microprocessor write timings control flash operations. does occupy addressable memory location within flash component. address data buses latched rising edge second F-WE# F-CE# pulse, whichever occurs first. (See Figure Figure read write waveforms.)
Flash Memory Modes Operation
flash memory four read modes: read array, read configuration, read status, query. write modes program erase. Three additional modes (erase suspend program, erase suspend read program suspend read) available only during suspended operations. These modes reached using commands summarized Table "Flash Memory Command Definitions" page
Read Array (FFh)
When F-RP# transitions from (reset) VIH, device defaults read array mode will respond read control inputs without additional commands. addition, address desired location must applied address balls. device read array mode, would case after program erase operation, Read Array command (FFh) must written before array reads take place.
Read Identifier (90h)
read configuration mode outputs manufacturer/device identifier. device switched this mode writing read configuration command (90h). Once this mode, read cycles from addresses shown Table "Read Configuration Table" page retrieve specified information. return read array mode, write Read Array command (FFh).
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Read Configuration mode outputs three types information: manufacturer/device identifier, block locking status, protection register. device switched this mode writing Read Configuration command (90h). Once this mode, read cycles from addresses shown Table retrieve specified information. return read array mode, write Read Array command (FFh). Table Read Configuration Table
Item Manufacturer Code (x16) Device (See Appendix Block Lock Configuration Address 0x00000 0x00001 0xXX002 Data 0x0089 LOCK 0x80 0x81-0x88 PR-LK Notes
Block Unlocked Block Locked Block Locked-Down
Protection Register Lock Protection Register (x16)
NOTES: Section valid lock status outputs. "XX" specifies block address lock configuration being read. Section protection register information.
Other locations within configuration address space reserved Intel future use.
Read Status Register (70h)
status register indicates status device operations, success/failure that operation. Read Status Register (70h) command causes subsequent reads output data from status register until another command issued. return reading from array, issue Read Array (FFh) command. status register bits output DQ[7:0]. upper byte, DQ[15:8], outputs during Read Status Register command. contents status register latched falling edge F-OE# F-CE#, whichever occurs last. This prevents possible errors which might occur status register contents change while being read. F-CE# F-OE# must toggled with each subsequent status read, status register will indicate completion program erase operation. When active, will indicate status WSM; remaining bits status register indicate whether successful performing desired operation (see Table "Flash Memory Status Register Definition" page 18).
3.3.1
Clear Status Register (50h)
sets status bits through "1," clears bits "0," cannot clear status bits through "0." Because bits indicate various error conditions, these bits only cleared through Clear Status Register (50h) command. allowing system software control resetting these bits, several operations performed
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
(such cumulatively programming several addresses erasing multiple blocks sequence) before reading status register determine error occurred during that series. Clear status register before beginning another command sequence. Note that Read Array command must issued before data read from memory array. Resetting device also clears status register.
Query (98h)
query mode outputs Common Flash Interface (CFI) data when device read. This accessed writing Query Command (98h). data structure contains information such block size, density, command electrical specifications. Once this mode, read cycles from addresses shown Appendix retrieve specified information. return read array mode, write Read Array command (FFh).
Word Program (40h/10h)
Programming executed using two-write sequence. Program Setup command (40h) written followed second write which specifies address data programmed. will execute sequence internally timed events program desired bits addressed location, then verify bits sufficiently programmed. Programming memory results specific bits within address location being changed "0." user attempts program "1"s, memory cell contents change error occurs. status register indicates programming status: while program sequence executes, status "0." status register polled toggling either F-CE# F-OE#. While programming, only valid commands Read Status Register, Program Suspend, Program Resume. When programming complete, program status bits should checked. programming operation unsuccessful, SR.4 status register indicate program failure. SR.3 then F-VPP within acceptable limits, execute program command. SR.1 set, program operation attempted locked block operation aborted. status register should cleared before attempting next operation. instruction follow after programming completed; however, prevent inadvertent status register reads, sure reset read array mode.
3.5.1
Suspending Resuming Program (B0h/D0h)
Program Suspend command halts in-progress program operation that data read from other locations memory. Once programming process starts, writing Program Suspend command requests that suspend program sequence predetermined points program algorithm). device continues output status register data after Program Suspend command written. Polling status register bits SR.7 SR.2 will determine when program operation been suspended (both will "1"). tWHRH1/ tEHRH1 specify program suspend latency. Read Array command written read data from block other than suspended block. only other valid commands, while program suspended, Read Status Register, Read Configuration, Query, Program Resume. After Program Resume
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
command written flash memory, will continue with programming process status register bits SR.2 SR.7 will automatically cleared. device automatically outputs status register data when read (see Appendix Program Suspend/Resume Flowcharts) after Program Resume command written. F-VPP must remain same F-VPP level used program while program suspend mode. F-RP# must also remain VIH.
Block Erase (20h)
erase block, write Erase Set-up Erase Confirm commands CUI, along with address identifying block erased. This address latched internally when Erase Confirm command issued. Block erasure results bits within block being "1." Only block erased time. will execute sequence internally timed events program bits within block "0," erase bits within block "1," then verify that bits within block sufficiently erased. While erase executes, status "0." When status register indicates that erasure complete, check erase status verify that erase operation successful. Erase operation unsuccessful, SR.5 status register will "1," indicating erase failure. F-VPP within acceptable limits after Erase Confirm command issued, will execute erase sequence; instead, SR.5 status register indicate erase error, SR.3 identify that F-VPP supply voltage within acceptable limits. After erase operation, clear status register (50h) before attempting next operation. instruction follow after erasure completed; however, prevent inadvertent status register reads, advisable place flash read array mode after erase complete.
3.6.1
Suspending Resuming Erase (B0h/D0h)
erase operation take several seconds complete, therefore, Erase Suspend command provided allow erase-sequence interruption order read data from, program data another block memory. Once erase sequence started, writing Erase Suspend command causes device suspend erase sequence predetermined point erase algorithm. Block erase suspended when Status Register bits SR[7,6] set. Suspend latency specified Section 5.7, "Flash Erase Program Timings" page When erase operation been suspended, Word Program Read operation performed within block, except block that erase suspend state. erase operation cannot nested within another erase suspend operation. suspended erase operation cannot resume until nested program operation completed. Read Array, Read Status Register, Clear Status Register, Read Identifier, Query, Erase Resume, valid commands during Erase Suspend. Additionally, Program, Program Suspend, Program Resume, Lock Block, Unlock Block Lock-Down Block valid commands during Erase Suspend. resume erase suspend operation, issue Resume command. Resume command written device address. When program operation nested within Erase Suspend operation Program Suspend command issued, device will suspend program operation. When resume command issued, device will resume program operation first. Once nested program operation completed, additional Resume command required complete block operation.
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Table
Flash Memory Command Definitions
First Cycle Second Cycle Data 40h/10h Write Write Write Write Write FFFD Write Write Read Read Read Operation Address Data Note Operation Address Write Write Write Write Write Write Write Write Write Write Write Write Write Write
Command Read Array Read Identifier Query Read Status Register Clear Status Register Word Program Block Erase/Confirm Program/Erase Suspend Program/Erase Resume Lock Block Unlock Block Lock-Down Block Protection Register Program Lock Protection Register Don't Care Status Register Data
Program Address Program Data
Block Address
Identifier Address Identifier Data
Query Address Query Data
NOTES: When writing commands, upper data [DQ8-DQ15] should either VIH, minimize current draw. Following Read Configuration Query commands, read operations output device configuration query information, respectively. Either command valid, Intel standard 40h. When unlocking block, must held three clock cycles clock cycle after second command cycle).
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Table
WSMS
Flash Memory Status Register Definition
VPPS NOTES:
SR.7 WRITE STATE MACHINE STATUS Ready (WSMS) Busy SR.6 ERASE-SUSPEND STATUS (ESS) Erase Suspended Erase Progress/Completed SR.5 ERASE STATUS (ES) Error Block Erase Successful Block Erase SR.4 PROGRAM STATUS (PS) Error Programming Successful Programming SR.3 F-VPP STATUS (VPPS) F-VPP Detect, Operation Abort F-VPP
Check Write State Machine first determine Word Program Block Erase completion, before checking Program Erase Status bits. When Erase Suspend issued, halts execution sets both WSMS bits "1." remains until Erase Resume command issued. When this "1," applied max. number erase pulses still unable verify successful block erasure. When this "1," attempted failed program word/byte. F-VPP status does provide continuous indication level. interrogates F-VPP level only after Program Erase command sequences have been entered, informs system F-VPP been switched F-VPP also checked before operation verified WSM. F-VPP status guaranteed report accurate feedback between VPPLK VPP1 min. When Program Suspend issued, halts execution sets both WSMS bits "1." remains until Program Resume command issued. program erase operation attempted locked blocks, this WSM. operation specified aborted device returned read status mode. This reserved future should masked when polling status register.
SR.2 PROGRAM SUSPEND STATUS (PSS) Program Suspended Program Progress/Completed SR.1 BLOCK LOCK STATUS Prog/Erase attempted locked block; Operation aborted. operation locked blocks SR.0 RESERVED FUTURE ENHANCEMENTS
NOTE: Command Sequence Error indicated when SR.4, SR.5 SR.7 set.
Block Locking
instant, individual block locking feature that allows flash block locked unlocked with latency, which enables instant code data protection. This locking offers levels protection. first level allows software-only control block locking (useful data blocks that change frequently), while second level requires hardware interaction before locking changed (useful code blocks that change infrequently). following sections will discuss operation locking system. term "state [XYZ]" will used specify locking states; e.g., "state [001]," where value WP#, Block Lock status register, Block Lock status register. Table "Block Locking State Transitions" page defines these possible locking states.
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
3.7.1
Block Locking Operation Summary
following concisely summarizes locking functionality. blocks locked when powered-up, unlocked locked with Unlock Lock commands.
Lock-Down command locks block prevents from being unlocked when When Lock-Down overridden commands unlock/lock locked-down
blocks.
When returns locked-down blocks return Lock-Down. Lock-Down cleared only when device reset powered-down.
locking status each block Locked, Unlocked, Lock-Down, each which will described following sections. comprehensive state table locking functions shown Table page flowchart locking operations shown Figure page
3.7.2
Locked State
default status blocks upon power-up reset locked (states [001] [101]). Locked blocks fully protected from alteration. program erase operations attempted locked block will return error SR.1 status register. status locked block changed Unlocked Lock-Down using appropriate software commands. Unlocked blocks locked issuing "Lock" command sequence, followed 01h.
3.7.3
Unlocked State
Unlocked blocks (states [000], [100], [110]) programmed erased. unlocked blocks return Locked state when device reset powered down. status unlocked block changed Locked Locked-Down using appropriate software commands. Locked block unlocked writing Unlock command sequence, followed D0h.
3.7.4
Lock-Down State
Blocks that Locked-Down (state [011]) protected from program erase operations (just like Locked blocks), their protection status cannot changed using software commands alone. Locked Unlocked block Locked-down writing Lock-Down command sequence, followed 2Fh. Locked-Down blocks revert Locked state when device reset powered down. Lock-Down function dependent input ball. When blocks LockDown [011] protected from program, erase, lock status changes. When LockDown function disabled ([111]) locked-down blocks individually unlocked software command [110] state, where they erased programmed. These blocks then re-locked [111] unlocked [110] desired while remains high. When goes low, blocks that were previously locked-down return Lock-Down state [011] regardless changes made while high. Device reset power-down resets blocks, including those Lock-Down, Locked state.
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
3.7.5
Reading Block's Lock Status
lock status every block read configuration read mode device. enter this mode, write device. Subsequent reads Block Address 00002 will output lock status that block. lock status represented least significant outputs, DQ1. indicates Block Lock/Unlock status Lock command cleared Unlock command. also automatically when entering Lock-Down. indicates LockDown status Lock-Down command. cannot cleared software, only device reset power-down.
Table
Block Lock Status
Item Block Lock Configuration Address XX002 Data LOCK
Block Unlocked Block Locked Block Locked-Down 3.7.6
Locking Operation during Erase Suspend
Changes block lock status performed during erase suspend using standard locking command sequences unlock, lock, lock-down block. This useful case when another block needs updated while erase operation progress. change block locking during erase operation, first write erase suspend command (B0h), then check status register until indicates that erase operation been suspended. Next write desired lock command sequence block lock status will changed. After completing desired lock, read, program operations, resume erase operation with Erase Resume command (D0h). block locked locked-down during suspended erase same block, locking status bits will changed immediately, when erase resumed, erase operation will complete. Locking operations cannot performed during program suspend.
3.7.7
Status Register Error Checking
Using nested locking program command sequences during erase suspend introduce ambiguity into status register results. Since locking changes performed using cycle command sequence, e.g., followed lock block, following Configuration Setup command (60h) with invalid command will produce lock command error (SR.4 SR.5 will status register. lock command error occurs during erase suspend, SR.4 SR.5 will will remain after erase resumed. When erase complete, possible error during erase cannot detected status register because previous locking command error. similar situation happens error occurs during program operation error nested within erase suspend.
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Table
Block Locking State Transitions
Erase/ Program Allowed? Next State after Command Input Lock [001] [101] [111] Unlock [000] [100] [110] Lock-Down [011] [111] [011] [111] [111]
Current State Name Unlocked Unlocked Locked (Default) Locked Locked-Down Lock-Down Disabled
NOTES: indicates change current state. this table, notation [XYZ] denotes locking state block, where WP#, DQ1, DQ0. current locking state block defined state bits block lock status (DQ0, DQ1). indicates block locked unlocked (0). indicates block been locked-down (0). power-up device reset, blocks default Locked state [001] holding recommended default. "Erase/Program Allowed?" column shows whether erase program operations enabled (Yes) disabled (No) that block's current locking state. "Lock Command Input Result [Next State]" column shows result writing three locking commands (Lock, Unlock, Lock-Down) current locking state. example, "Goes [001]" would mean that writing command block current locking state would change [001]. bits protection register divided into 64-bit segments. segments programmed Intel factory with unique number, which unchangeable. other segment left blank customer designs program desired. Once customer segment programmed, locked prevent reprogramming.
Protection Register
Volt Intel® Advanced+ Stacked-CSP architecture includes 128-bit protection register than used increase security system design. example, number contained protection register used "mate" flash component with other system components such ASIC, preventing device substitution.
3.8.1
Reading Protection Register
protection register read configuration read mode. device switched this mode writing Read Configuration command (90h). Once this mode, read cycles from addresses shown Appendix retrieve specified information. return read array mode, write Read Array command (FFh).
3.8.2
Programming Protection Register (C0h)
protection register bits programmed using two-cycle Protection Program command. 64-bit number programmed bits time word-wide parts. First write Protection Program Setup command, C0h. next write device will latch address data program specified location. allowable addresses shown Appendix Figure "Protection Register Programming Flowchart" page
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attempt address Protection Program commands outside defined protection register address space will result status register error (program error SR.4 will Attempting program previously locked protection register segment will result status register error (program error SR.4 lock error SR.1 will
3.8.3
Locking Protection Register
user-programmable segment protection register lockable programming PR-LOCK location this location programmed Intel factory protect unique device number. This using Protection Program command program FFFDh PR-LOCK location. After these bits have been programmed, further changes made values stored protection register. Protection Program command locked words will result status register error (program error SR.4 Lock Error SR.1 will protection register lockout state reversible.
Figure Protection Register Memory
Words User Programmed Words Factory Programmed PR-LOCK
0645_05
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Power Reset Considerations
Power-Up/Down Characteristics
order prevent condition that result spurious write erase operation, recommended power-up F-VCC, F-VCCQ S-VCC together. Conversely, F-VCC, F-VCCQ S-VCC must power-down together. also recommended power-up F-VPP with slightly after F-VCC. Conversely, F-VPP must power down with slightly before F-VCC. F-VCCQ and/or F-VPP connected F-VCC supply, then F-VCC should attain FVCCMin before applying F-VCCQ F-VPP. Device inputs should driven before supply voltage F-VCCMin. Power supply transitions should only occur when F-RP# low.
Additional Flash Features
Intel Volt Advanced+ Stacked-CSP products provide in-system programming erase 1.65 V-3.3 range. fast production programming, also includes low-cost, backwardcompatible programming feature.
4.2.1
Improved Volt Production Programming
When F-VPP between 1.65 program erase current drawn through F-VCC signal. Note that F-VPP driven logic signal, 1.65 That F-VPP must remain above 1.65 perform in-system flash modifications. When F-VPP connected power supply, device draws program erase current directly from F-VPP signal. This eliminates need external switching transistor control voltage F-VPP. Figure "Example Power Supply Configurations" page shows examples flash power supplies configured various usage models. F-VPP mode enhances programming performance during short period time typically found manufacturing processes; however, intended extended use. applied F-VPP during program erase operations maximum 1000 cycles main blocks 2500 cycles parameter blocks. F-VPP connected total hours maximum. Stressing device beyond these limits cause permanent damage.
4.2.2
F-VPP VPPLK Complete Protection
addition flexible block locking, F-VPP programming voltage held absolute hardware write protection blocks flash device. When F-VPP below VPPLK, program erase operation will result error, prompting corresponding status register (SR.3) set.
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Warning:
Electrical Specifications
Absolute Maximum Ratings
Stressing device beyond "Absolute Maximum Ratings" cause permanent damage. These stress ratings only. Operation beyond "Operating Conditions" recommended extended exposure beyond "Operating Conditions" affect device reliability.
NOTICE: This datasheet contains information products full production. specifications subject change without notice. Verify with your local Intel Sales office that have latest datasheet before finalizing design.
Table
Absolute Maximum Ratings
Parameter Maximum Rating Notes
Extended Operating Temperature During Read During Flash Block Erase Program Temperature under Bias Storage Temperature Voltage Ball (except F-VCC /F-VCCQ S-VCC F-VPP) with Respect F-VPP Voltage (for Block Erase Program) with Respect F-VCC F-VCCQ S-VCC Supply Voltage with Respect Output Short Circuit Current -65°C +125°C -0.5 +3.3 -0.5 +13.5 -0.2V +3.3 1,2,4 -25°C +85°C
NOTES: Minimum voltage -0.5 input/output balls. During transitions, this level undershoot periods Maximum voltage input/output balls F-VCC F-VCCQ S-VCC which, during transitions, overshoot F-VCC F-VCCQ S-VCC periods Maximum voltage F-VPP overshoot +14.0 periods F-VPP voltage normally 1.65 V-3.3 Connection supply 11.4 V-12.6 only done 1000 cycles main blocks 2500 cycles parameter blocks during program/erase. F-VPP connected total hours maximum. Section 4.2.1 details Output shorted more than second. more than output shorted time.
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Operating Conditions
Table Temperature Voltage Operating Conditions
Symbol TCASE VCCQ VPP1 VPP2 Cycling Block Erase Cycling Parameter Operating Temperature F-VCC /F-VCCQ /S-VCC Supply Voltage Supply Voltage Notes 1.65 11.4 100,000 12.6 Units Volts Volts Volts Cycles
NOTES: F-VCC/F-VCCQ must share same supply. F-VCC/S-VCC must share same supply when data retention. Applying F-VPP 11.4 V-12.6 during program/erase only done maximum 1000 cycles main blocks 2500 cycles parameter blocks. F-VPP connected total hours maximum. Section 4.2.1 details.
Capacitance
TCASE +25°C,
COUT Parameter Input Capacitance Output Capacitance Notes Units Conditions VOUT
NOTE: Sampled, 100% tested.
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Characteristics
Table Characteristics (Sheet
Symbol Parameter Device Note Input Load Current Output Leakage Current Flash/ SRAM Flash/ SRAM 0.25µm Flash 0.13µm 0.18µm Flash 2-Mb SRAM 4-Mb SRAM 8-Mb SRAM 0.25µm Flash ICCD Deep Power-Down Current 0.13µm 0.18µm Flash 2-Mb SRAM 4-Mb SRAM 8-Mb SRAM Operating Power Supply Current (min cycle time) 2-Mb SRAM 4-Mb SRAM 8-Mb SRAM 0.25µm Flash ICCR Read Current 0.13µm 0.18µm Flash F-VCC F-CE# F-RP# F-WP# S-VCC S-CS1# VCC, S-CS2 S-CS2 F-VCC VCCMax F-RP# F-VCC/S-VCC VCCMax F-VCC/S-VCC Unit Test Conditions
ICCS
Standby Current
Operating Power Supply Current (cycle time
S-CS1# S-CS2 S-WE#
ICC2
Cycle time Min, 100% duty, S-CS1# VIL, S-CS2 VIH,
F-VCC VCCMax F-OE# VIH, F-CE# MHz, IOUT
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Table Characteristics (Sheet
Symbol Parameter Device Note ICCW Program Current Flash ICCE Erase Current Flash ICCES Erase Suspend Current Flash 0.25µm Flash ICCWS Program Suspend Current 0.13µm 0.18µm Flash Flash Flash Flash 0.05 IPPW F-VPP Program Current Flash IPPE F-VPP Erase Current Flash 0.05 IPPES F-VPP Erase Suspend Current Flash IPPWS F-VPP Program Suspend Current Flash F-VPP VPP2 Erase Suspend Progress F-VPP VPP1 Program Suspend Progress F-VPP VPP2 Program Suspend Progress F-VPP VPP2 Program Progress F-VPP VPP1 Erase Progress F-VPP VPP1 Erase Suspend Progress 1,3,4 1,3,4 1,3,4 F-CE# VCC, Program Suspend Progress F-VPP VPP2 Erase Progress F-CE# VCC, Erase Suspend Progress F-VPP VPP2 Program Progress F-VPP VPP1 Erase Progress F-VPP VPP1 Program Progress Unit Test Conditions
IPPD IPPS IPPR
F-VPP Deep Power-Down Current F-VPP Standby Current F-VPP Read Current
F-RP# F-VPP F-VPP F-VPP F-VPP F-VPP =VPP1 Program Progress
NOTES: currents unless otherwise noted. Typical values nominal F-VCC/S-VCC, TCASE Automatic Power Savings (APS) reduces ICCR approximately standby levels static operation (CMOS inputs). Sampled, 100% tested. ICCES ICCWS specified with device de-selected. device read while erase suspend, current draw ICCES ICCR. device read while program suspend, current draw ICCWS ICCR.
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Table Characteristics
Symbol Parameter Device Flash/ SRAM Flash/ SRAM Flash/ SRAM Flash/ SRAM Flash Flash Flash Flash 1.65 11.4 Note VPPLK VPP1 VPP2 VLKO VLKO2 Input Voltage Input High Voltage Output Voltage Output High Voltage F-VPP Lock-Out Voltage F-VPP during Program Erase Operations Prog/Erase Lock Voltage VCCQ Prog/Erase Lock Voltage -0.2 -0.10 12.6 +0.2 0.10 F-VCC/S-VCC F-VCC/S-VCC -100 Complete Write Protection Units Test Conditions
NOTES: Erase Program inhibited when F-Vpp VPPLK guaranteed outside valid F-Vpp ranges VPP1 VPP2. Applying F-Vpp 11.4V-12.6V during program/erase only done maximum 1000 cycles main blocks 2500 cycles parameter blocks. F-Vpp connected total hours maximum. Section 4.2.1 details.
Figure Input/Output Reference Waveform
INPUT
NOTE: test inputs driven VCCQ logic 0.0V logic "0." Input timing begins, output timing ends, VCCQ/2. Input rise fall times (10%-90%) Worst case speed conditions when VCCQ VCCQMin.
0645_07
TEST POINTS
OUTPUT
Figure Test Configuration
Device Under Test
0666_05
NOTE: includes capacitance.
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Flash Test Configuration Component Values Table
Test Configuration V-3.3 Standard Test (pF)
Flash Characteristics.
Table Flash Characteristics-Read Operations
Density Product Parameter Voltage Range Note tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ Read Cycle Time Address Output Delay F-CE# Output Delay F-OE# Output Delay F-RP# Output Delay F-CE# Output F-OE# Output F-CE# Output High F-OE# Output High Output Hold from Address F-CE#, F-OE# Change, Whichever Occurs First 16-Mbit -110 32-Mbit Unit
NOTES: F-OE# delayed tELQV-tGLQV after falling edge without impact tELQV Sampled, 100% tested. Figure Waveform: Flash Read Operations" page Figure "Input/Output Reference Waveform" page timing measurements maximum allowable input slew rate.
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Figure Waveform: Flash Read Operations
Device Address Selection Address Stable Data Valid
ADDRESSES DATA (D/Q) RP#(P) High
Standby
Valid Output High
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Flash Characteristics-Write Operations
Table Flash Characteristics-Write Operations
Density Product Parameter Voltage Range Note tPHWL tPHEL tELWL tWLEL tELEH tWLWH tDVWH tDVEH tAVWH tAVEH tWHEH tEHWH tWHDX tEHDX tWHAX tEHAX tWHWL tEHEL tVPWH tVPEH tQVVL F-RP# High Recovery F-WE# (F-CE#) Going F-CE# (F-WE#) Setup F-WE# (F-CE#) Going F-WE# (F-CE#) Pulse Width Data Setup F-WE# (F-CE#) Going High Address Setup F-WE# (F-CE#) Going High F-CE# (F-WE#) Hold Time from F-WE# (F-CE#) High Data Hold Time from F-WE# (F-CE#) High Address Hold Time from F-WE# (F-CE#) High F-WE# (F-CE#) Pulse Width High F-VPP Setup F-WE# (F-CE#) Going High F-VPP Hold from Valid 16-Mbit -110 32-Mbit Unit
NOTES: Write pulse width (tWP) defined from F-CE# F-WE# going (whichever goes last) F-CE# F-WE# going high (whichever goes high first). Hence, tWLWH tELEH tWLEH tELWH. Similarly, write pulse width high (tWPH) defined from F-CE# F-WE# going high (whichever goes high first) F-CE# F-WE# going (whichever goes first). Hence, tWPH tWHWL tEHEL tWHEL tEHWL. Refer Table "Flash Memory Command Definitions" page valid DIN. Sampled, 100% tested.
Figure "Input/Output Reference Waveform" page timing measurements maximum allowable input slew rate. Figure Waveform: Flash Program Erase Operations" page
Flash Erase Program Timings(1)
Table Flash Erase Program Timings (Sheet
F-VPP Symbol tBWPB tBWMB tWHQV1 tEHQV1 tWHQV2 tEHQV2 Parameter Note 4-KW Parameter Block Program Time (Word) 32-KW Main Block Program Time (Word) 0.25 Word Program Time 0.13 0.18 Word Program Time 4-KW Parameter Block Erase Time (Word) Typ(1) 0.10 0.30 Typ(1) 0.03 0.24 0.12 1.65 11.4 12.6 Unit
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Table Flash Erase Program Timings (Sheet
F-VPP Symbol Parameter Note tWHQV3 tEHQV3 32-KW Main Block Erase Time (Word) tWHRH1 tEHRH1 Program Suspend Latency tWHRH2 tEHRH2 Erase Suspend Latency NOTES: Typical values measured TCASE nominal voltages. Excludes external system-level overhead. Sampled, 100% tested. Typ(1) Typ(1) 1.65 11.4 12.6 Unit
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Figure Waveform: Flash Program Erase Operations
ADDRESSES
CE#(WE#) [E(W)]
(Note
WE#(CE#) [W(E)]
(Note
DATA [D/Q]
High
Valid
VPPH VPPH1 VPPLK
NOTES: F-CE# must toggled when reading Status Register Data. F-WE# must inactive (high) when reading Status Register Data. F-VCC Power-Up Standby. Write Program Erase Setup Command. Write Valid Address Data (for Program) Erase Confirm Command. Automated Program Erase Delay. Read Status Register Data (SRD): reflects completed program/erase operation. Write Read Array Command.
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Flash Reset Operations
Figure Waveform: Reset Operation
PLPH Reset during Read Mode
PHQV PHWL PHEL
Abort Complete
PLRH
PHQV PHWL PHEL
PLPH Reset during Program Block Erase, PLPH PLRH
Abort Deep Complete PowerDown
PLRH
PHQV PHWL PHEL
PLPH
Reset Program Block Erase, PLPH PLRH
Table Reset Specifications(1)
F-VCC Symbol Parameter F-RP# Reset during Read F-RP# tied VCC, this specification applicable) F-RP# Reset during Block Erase F-RP# Reset during Program Note tPLPH tPLRH1 tPLRH2 Unit
NOTES: Section 2.1.4, "Flash Reset" page full description these conditions. tPLPH device still reset this guaranteed. F-RP# asserted while block erase word program operation executing, reset will complete within Sampled, 100% tested.
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SRAM Characteristics-Read Operations
Table SRAM Characteristics-Read Operations(1)
Density Parameter Voltage Range Note tCO1, tCO2 tLZ1, tLZ2 tOLZ tHZ1, tHZ2 tOHZ tBLZ tBHZ Read Cycle Time Address Output Delay S-CS1#, S-CS2 Output Delay S-OE# Output Delay S-UB#, Output Delay S-CS1#, S-CS2 Output S-OE# Output S-CS1#, S-CS2 Output High S-OE# Output High Output Hold from Address, S-CS1#, S-CS2, S-OE# Change, Whichever Occurs First S-UB#, S-LB# Output S-UB#, S-LB# Output High 2,3,4 2/4/8-Mbit Unit
NOTE: Figure Waveform: SRAM Read Operations" page given temperature voltage condition, (Max) less than (Max) both given device from device device interconnection. Sampled, 100% tested. Timings tOHZ defined time which outputs achieve open circuit conditions referenced output voltage levels.
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Figure Waveform: SRAM Read Operations
Device Address Selection Address Stable
Standby
Data Valid
ADDRESSES
CS1# (E1) (E2)
High Valid Output High
DATA (D/Q)
UB#,
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5.10
SRAM Characteristics-Write Operations
Table SRAM Characteristics-Write Operations(1,2)
Density Parameter Volt Note Write Cycle Time Address Setup S-WE# (S-CS1#) S-UB#, S-LB# Going S-WE# (S-CS1#) Pulse Width Data Write Time Overlap Address Setup S-WE# (S-CS1#) Going High S-CE# (S-WE#) Setup S-WE# (S-CS1#) Going High Data Hold Time from S-WE# (S-CS1#) High Write Recovery S-UB#, S-LB# Setup S-WE# (S-CS1#) Going High 2/4/8-Mbit Unit
NOTES: Figure Waveform: SRAM Write Operations" page write occurs during overlap (tWP) S-CS1# S-WE#. write begins when S-CS1# goes S-WE# goes with asserting S-UB# S-LB# single byte operation simultaneously asserting S-UB# S-LB# double byte operation. write ends earliest transition when S-CS1# goes high S-WE# goes high. measured from beginning write write. measured from address valid beginning write. measured from S-CS1# going write. measured from write address change. applied case write ends S-CS1# S-WE# going high.
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Figure Waveform: SRAM Write Operations
Device Address Selection Address Stable
Standby
ADDRESSES
CS1# (E1) (E2)
High High
DATA (D/Q)
Data
UB#,
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5.11
SRAM Data Retention Characteristics-Extended Temperature
Table SRAM Data Retention Characteristics(1)-Extended Temperature
Parameter S-VCC Data Retention Deep Retention Current 8-Mbit Deep Retention Current 4-Mbit Deep Retention Current 2-Mbit tSDR tRDR Data Retention Set-up Time Recovery Time Note Unit Data Retention Waveform S-VCC CS1# Test Conditions CS1#
NOTES: Typical values nominal S-VCC, TCASE S-CS1# S-CS2 (S-CS1# controlled) S-CS2 (S-CS2 controlled).
Figure SRAM Data Retention Waveform
tSDR Data Retention Mode tRDR
CS1# Controlled 3.0/2.7V
CS1# (E1) 2.2V
Controlled tSDR 3.0/2.7V Data Retention Mode tRDR
(E2)
0.4V
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Migration Guide Information
Typically, important discuss footprint migration compatibility between product existing products. this specific case, Stacked-CSP allows system designer remove separate memory footprints individual flash SRAM replace them with single footprint, thus resulting overall reduction board space required. This implies that printed circuit board would used take advantage this feature. Since flash Stacked-CSP shares same features Advanced+ Boot Block Features, conversions from Advanced Boot Block described AP-658 Designing Upgrade Advanced+ Boot Block Flash Memory, order number 292216. Please contact your local Intel representation detailed information about specific Flash SRAM system migrations.
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System Design Considerations
This section contains information that would have been contained product design guide earlier generations. effort simplify amount documentation, relevant system design considerations have been combined into this document.
Background
Intel Advanced+ Boot Block Stacked chip scale package combines features Advanced+ Boot Block flash memory architecture with low-power SRAM achieve overall reduction system board space. This enables applications integrate security with simple software hardware configurations, while also combining system SRAM flash into common footprint. This section discusses take full advantage Volt Advanced+ Boot Block Stacked Chip Scale Package.
7.1.1
Flash SRAM Footprint Integration
Stacked Chip Scale Package memory solution used replace subset memory subsystem within design. Where previous design have used separate footprints SRAM Flash, replace with industry-standard I-ballout Stacked-CSP device. This allows overall reduction board space, which allows design integrate both flash SRAM into component.
7.1.2
Advanced+ Boot Block Flash Memory Features
Advanced+ Boot Block adds following features Intel Advanced Boot Block architecture:
Instant, individual block locking provides software/hardware controlled, independent locking/
unlocking block with zero latency protect code data.
128-bit Protection Register enables system security implementations. Improved production programming simplifies system configuration required
implement fast programming.
Common Flash Interface (CFI) provides component information chip allow softwareindependent device upgrades. more information specific advantages Advanced+ Boot Block Flash Memory, please AP-658 Designing with Advanced+ Boot Block Flash Memory Architecture.
Flash Control Considerations
flash device protected against accidental block erasure programming during power transitions. Power supply sequencing required, since device indifferent which power supply, F-VPP F-VCC, powers-up first. Example flash power supply configurations shown Figure "Example Power Supply Configurations" page
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7.2.1
F-RP# Connected System Reset
F-RP# during system reset important with automated program/erase devices since system expects read from flash memory when comes reset. reset occurs without flash memory reset, proper initialization will occur because flash memory providing status information instead array data. Intel recommends connecting F-RP# system RESET# signal allow proper CPU/flash initialization following system reset. System designers must guard against spurious writes when F-VCC voltages above VLKO. Since both F-WE# F-CE# must command write, driving either signal will inhibit writes device. architecture provides additional protection since alteration memory contents only occur after successful completion two-step command sequences. device also disabled until F-RP# brought VIH, regardless state control inputs. holding device reset (F-RP# connected system PowerGood) during power-up/down, invalid conditions during power-up masked, providing another level memory protection.
7.2.2
F-VCC, F-VPP F-RP# Transition
latches commands issued system software altered F-VPP F-CE# transitions actions. default state upon power-up, after exit from reset mode after F-VCC transitions above VLKO (Lockout voltage), read array mode. After program block erase operation complete (even after F-VPP transitions down VPPLK), must reset read array mode Read Array command access flash memory array desired.
Figure Example Power Supply Configurations
System Supply
System Supply Supply Fast Programming Absolute Write Protection With VPPLK System Supply
(Note
Prot# (Logic Signal)
Low-Voltage Programming Absolute Write Protection Logic Signal System Supply
Low-Voltage Programming
Supply Voltage Fast Programming
NOTE: resistor used F-VCC supply sink adequate current based resistor value.
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Noise Reduction
Stacked-CSP memory's power switching characteristics require careful device decoupling. System designers should consider three supply current issues both flash SRAM:
Standby current levels (ICCS) Read current levels (ICCR) Transient peaks produced falling rising edges F-CE#, S-CS1#, S-CS2.
Transient current magnitudes depend device outputs' capacitive inductive loading. Twoline control proper decoupling capacitor selection will suppress these transient voltage peaks. Each device should have capacitors between individual power (F-VCC, F-VCCQ, F-VPP, S-VCC) ground (GND) signals. High-frequency, inherently low-inductance capacitors should placed close possible package leads. Noise issues within system cause devices operate erratically adequately filtered. order avoid noise interaction issues within system, recommended that design contain appropriate number decoupling capacitors system. Noise issues also reduced leads device kept very short, order reduce inductance. Decoupling capacitors between reduce voltage spikes supplying extra current needed during switching. Placing these capacitors close device possible reduces line inductance. capacitors should inductance capacitors; surface mount capacitors typically exhibit lower inductance. highly recommended that systems capacitor each D10, grid ballout locations (see Figure "66-Ball Stacked Chip Scale Package" page ballout). These capacitors necessary avoid undesired conditions created excess noise. Smaller capacitors used decouple higher frequencies.
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Figure Typical Flash SRAM Substrate Power Ground Connections
SUBSTRATE FLASH SRAM S-VSS S-VCCQ F-VCCQ F-VPP F-VSS
Substrate connection package ball SRAM bond connection Flash bond connection
NOTES: Substrate connections refer ballout locations shown Figure "66-Ball Stacked Chip Scale Package" page 0.1µf capacitors should used with D10, A10and Some SRAM devices have S-VSSQ; this case, this S-VSS. Some SRAM devices have S-VSSQ; this case, this VCC.
Simultaneous Operation
term simultaneous operation used describe ability read write SRAM while also programming erasing flash. addition, F-CE#, S-CS1# S-CS2 should enabled same time. (See Table Volt Intel® Advanced+ Boot Block Stacked-CSP Ball Descriptions" page summary recommended operating modes.) Simultaneous operation summarized following:
SRAM read/write during Flash Program Erase Operation allowed. Simultaneous Operations between Flash SRAM allowed (because
contention).
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7.4.1
SRAM Operation during Flash "Busy"
This functionality provides ability both flash SRAM same time" within system, similar operation devices with separate footprints. This operation achieved following appropriate timing constraints within system.
7.4.2
Simultaneous Operations
Operations that require both SRAM Flash active mode disallowed. example these cases would include simultaneous reads both flash SRAM, which would result contention data bus. Finally, read device while attempting write other (similar conditions direct memory access (DMA) operation) also within recommended operating conditions. Basically, only memory drive outputs device given point time.
Printed Circuit Board Notes
Intel Stacked-CSP will save significant space your combining chips into style package. Intel Stacked-CSP pitch that routed your Printed Circuit Board with conventional design rules. Trace widths 0.127 (0.005 inches) typical. Unused balls center package populated further increase routing options. Standard surface mount process equipment used Intel Stacked-CSP.
Figure Standard Design Rules Used with Stacked-CSP Device
Land Diameter: 0.35 (0.0138 Solder Mask Opening: 0.50 (0.0198
Trace Width: 0.127 (0.005 Trace Spaces: 0.160 (0.00625 Capture Pad: 0.51 (0.020 Drill Size: 0.25 (0.010
NOTE: View
System Design Notes Summary
Advanced+ Boot Block Stacked-CSP allows higher levels memory component integration. Different power supply configurations used within system achieve different objectives. least three different capacitors should used decouple devices within system. SRAM reads writes during flash program erase supported operations. Standard printed circuit board technology used.
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Appendix Program/Erase Flowcharts
Figure Automated Word Programming Flowchart
Start
Operation Write Write Command Program Setup Program Comments Data Data Data Program Addr Location Program Status Register Data Toggle Update Status Register Data Check SR.7 Ready Busy
Write
Program Address/Data
Read
Read Status Register
Standby
SR.7 Full Status Check Desired
Repeat subsequent programming operations. Full Status Check done after each program after sequence program operations. Write after last program operation reset device read array mode.
Program Complete
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 SR.4 SR.1 Program Successful
error detected, clear status register before attempting retry other error recovery.
Operation Standby
Command
Comments Check SR.3 Detect Check SR.4 Program Error Check SR.1 Attempted Program Locked Block Program Aborted
Range Error Programming Error
Standby
Standby
SR.3 MUST cleared, during program attempt, before further attempts allowed Write State Machine.
Attempted Program Locked Block Aborted
SR.1, SR.3 SR.4 only cleared Clear Staus Register Command, cases where multiple bytes programmed before full status checked.
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Figure Program Suspend/Resume Flowchart
Start
Operation Write Command Program Suspend Read Status Comments Data Addr Data Addr Status Register Data Toggle Update Status Register Data Addr Check SR.7 Ready Busy Check SR.2 Program Suspended Program Completed Read Array Data Addr Read array data from block other than being programmed. Program Resume Data Addr
Write
Write
Write
Read
Read Status Register
Standby
SR.7 SR.2
Standby
Write
Program Completed
Read
Write
Write
Read Array Data
Done Reading Write
Write
Program Resumed
Read Array Data
0645_13
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Figure Automated Block Erase Flowchart
Start
Operation Command Comments Data Addr Within Block Erased Data Addr Within Block Erased Status Register Data Toggle Update Status Register Data Check SR.7 Ready Busy
Write
Write
Erase Setup
Write Block Address
Write
Erase Confirm
Read
Read Status Register
Suspend Erase Loop Suspend Erase
Standby
SR.7 Full Status Check Desired
Repeat subsequent block erasures. Full Status Check done after each block erase after sequence block erasures. Write after last write operation reset device read array mode.
Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 SR.4,5 SR.5 SR.1 Block Erase Successful
0645_14
Operation Standby
Command
Comments Check SR.3 Detect Check SR.4,5 Both Command Sequence Error Check SR.5 Block Erase Error Check SR.1 Attempted Erase Locked Block Erase Aborted
Range Error
Standby
Command Sequence Error
Standby
Standby
Block Erase Error
MUST cleared, during erase attempt, before further attempts allowed Write State Machine. SR.1, only cleared Clear Staus Register Command, cases where multiple bytes erased before full status checked. error detected, clear status register before attempting retry other error recovery.
Attempted Erase Locked Block Aborted
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Figure Erase Suspend/Resume Flowchart
Start
Operation Write
Command Erase Suspend Read Status
Comments Data Addr Data Addr Status Register Data Toggle Update Status Register Data Addr Check SR.7 Ready Busy Check SR.6 Erase Suspended Erase Completed
Write
Write
Write
Read
Read Status Register
Standby
SR.7 SR.6
Standby
Write
Read Array
Data Addr Read array data from block other than being erased.
Erase Completed
Read
Write
Erase Resume
Write
Data Addr
Read Array Data
Done Reading Write
Write
Erase Resumed
Read Array Data
0645_15
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Figure Locking Operations Flowchart
Operation Write
Start
Command Config. Setup
Comments Data Addr Data= (Lock Block) (Unlock Block) (Lockdown Block) Addr=Within block lock Data Addr Block Lock Status Data Addr Second addr block Confirm Locking Change DQ1, DQ0. (See Block Locking State Table valid combinations.)
Write (Configuration Setup) Write 01H, D0H,
Write
Lock, Unlock, Lockdown Read Configuration Block Lock Status
Write (Optional) Read (Optional) Standby (Optional)
Write (Read Configuration)
Optional
Read Block Lock Status
Locking Change Confirmed? Write (Read Array)
Locking Change Complete
0645_16
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Figure Protection Register Programming Flowchart
Start
Operation Write Write
Command Protection Program Setup Protection Program
Comments Data Data Data Program Addr Location Program Status Register Data Toggle Update Status Register Data Check SR.7 Ready Busy
Write (Protection Reg. Program Setup) Write Protect. Register Address/Data
Read
Standby
Read Status Register
SR.7 Full Status Check Desired
Protection Program operations only addressed within protection register address space. Addresses outside defined space will return error. Repeat subsequent programming operations. Full Status Check done after each program after sequence program operations. Write after last program operation reset device read array mode.
Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3, SR.4 Range Error SR.1, SR.4
Standby Operation Standby Command Comments SR.1 SR.3 SR.4 Prot. Reg. Prog. Error Register Locked: Aborted
Protection Register Programming Error Attempted Program Locked Register Aborted
Standby
SR.3 MUST cleared, during program attempt, before further attempts allowed Write State Machine.
SR.1, SR.4
SR.1, SR.3 SR.4 only cleared Clear Staus Register Command, cases multiple protection register program operations before full status checked. error detected, clear status register before attempting retry other error recovery.
Program Successful
0645_17
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Appendix Query Structure
This appendix defines data structure "database" returned Common Flash Interface (CFI) Query command. System software should parse this structure gain critical information such block size, density, x8/x16, electrical specifications. Once this information been obtained, software will know which command sets enable flash writes, block erases, otherwise control flash component. Query part overall specification multiple command control interface descriptions called Common Flash Interface, CFI.
Query Structure Output
Query "database" allows system software gain information controlling flash component. This section describes device's CFI-compliant interface that allows host system access Query data. Query data always presented lowest-order data outputs (DQ0-7) only. numerical offset value address relative maximum width supported device. this family devices, Query table device starting address 10h, which word address devices. word-wide (x16) device, first bytes Query structure, ASCII, appear byte word addresses 11h. This CFI-compliant device outputs data upper bytes. Thus, device outputs ASCII byte (DQ0-7) high byte (DQ8-15). Query addresses containing more bytes information, least significant data byte presented lower address, most significant data byte presented higher address. following tables, addresses data represented hexadecimal notation, suffix been dropped. addition, since upper byte word-wide devices always "00h," leading "00" been dropped from table notation only lower byte value shown. device outputs assumed have upper byte this mode.
Table Summary Query Structure Output Function Device Mode
Device Device Address Offset Code ASCII Value
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Table Example Query Structure Output Devices
Word Addressing Offset A15-A0 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0051 0052 0059 P_IDLO P_IDHI A_IDLO A_IDHI Code D15-D0 PrVendor PrVendor TblAdr AltVendor Value Offset A7-A0 P_IDLO P_IDLO P_IDHI Byte Addressing Code D7-D0 PrVendor Value
Query Structure Overview
Query command causes flash component display Common Flash Interface (CFI) Query structure "database." structure sub-sections address locations summarized below.
Table Query Structure
Offset (BA+2)h 04-0Fh Block Status Register Reserved Query Identification String System Interface Information Device Geometry Definition Primary Intel-Specific Extended Query Table Sub-Section Name Manufacturer Code Device Code Block-specific information Reserved vendor-specific information Command vendor data offset Device timing voltage information Flash device layout Vendor-defined additional information specific Primary Vendor Algorithm Description Notes
NOTES: Refer Query Structure Output section offset detailed definition offset address function device width mode. beginning location Block Address (e.g., 08000h beginning location block when block size Kword). Offset defines which points Primary Intel-specific Extended Query Table.
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Block Lock Status Register
Block Status Register indicates whether erase operation completed successfully whether given block locked accessed flash program/erase operations. Block Erase Status (BSR.1) allows system software determine success last block erase operation. BSR.1 used just after power-up verify that supply accidentally removed during erase operation. This only reset issuing another erase operation block. Block Status Register accessed from word address within each block.
Table Block Status Register
Offset (BA+2)h Length Description Block Lock Status Register BSR.0 Block Lock Status Unlocked Locked BSR.1 Block Lock-Down Status locked down Locked down 2-7: Reserved future Address BA+2: BA+2: Value (bit Notes
BA+2: BA+2:
(bit (bit 2-7):
NOTE: beginning location Block Address (i.e., 008000h beginning location block word mode.)
Query Identification String
Identification String provides verification that component supports Common Flash Interface specification. also indicates specification version supported vendor-specified command set(s).
Table Identification
Offset Length Description Query-unique ASCII string "QRY" Addr. Code Value
Primary vendor command control interface code. 16-bit code vendor-specified algorithms Extended Query Table primary algorithm address Alternate vendor command control interface code 0000h means second vendor-specified algorithm exists Secondary algorithm Extended Query Table address. 0000h means none exists
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
System Interface Information
Table System Interface Information
Offset Length Description logic supply minimum program/erase voltage bits bits volts logic supply maximum program/erase voltage bits bits volts [programming] supply minimum program/erase voltage bits bits volts [programming] supply maximum program/erase voltage bits bits volts such that typical single word program time-out logic supply minimum program/erase voltage bits bits volts logic supply maximum program/erase voltage bits bits volts [programming] supply minimum program/erase voltage bits bits volts [programming] supply maximum program/erase voltage bits bits volts such that typical single word program time-out logic supply minimum program/erase voltage bits bits volts logic supply maximum program/erase voltage bits bits volts [programming] supply minimum program/erase voltage bits bits volts such that typical max. buffer write time-out such that typical block erase time-out such that typical full chip erase time-out such that maximum word program time-out times typical such that maximum buffer write time-out times typical such that maximum block erase time-out times typical such that maximum chip erase time-out times typical Addr. Code Value
11.4
12.6
11.4
12.6
11.4
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Device Geometry Definition
Table Device Geometry Definition
Offset Length Description such that device size number bytes Flash device interface: async async x8/x16 async 28:00,29:00 28:01,29:00 28:02,29:00 such that maximum number bytes write buffer Number erase block regions within device: means erase blocking; device erases "bulk" specifies number device partition regions with more contiguous same-size erase blocks. Symmetrically blocked partitions have blocking region Partition size (total blocks) (individual block size) Erase Block Region Information bits 0-15 number identical-size erase blocks bits 16-31 region erase block(s) size bytes Erase Block Region Information bits 0-15 number identical-size erase blocks bits 16-31 region erase block(s) size bytes Code Table Below
Device Geometry Definition 16-Mbit Address 32-Mbit
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Intel-Specific Extended Query Table
Certain flash features commands optional. Intel-Specific Extended Query table specifies this other similar types information.
Table Primary-Vendor Specific Extended Query
Offset(1) (P+0)h (P+1)h (P+2)h (P+3)h (P+4)h (P+5)h (P+6)h (P+7)h (P+8)h Length Description (Optional Flash Features Commands) Primary extended query table Unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Optional feature command support (1=yes, 0=no) bits 9-31 reserved; undefined bits "0." then another field optional features follows bit-30 field. Chip erase supported Suspend erase supported Suspend program supported Legacy lock/unlock supported Queued erase supported Instant individual block locking supported Protection bits supported Page mode read supported Synchronous read supported Supported functions after suspend: read array, status, query Other supported operations are: bits reserved; undefined bits Program supported after erase suspend Block status register mask bits 2-15 Reserved; undefined bits Block Lock-Bit Status register active Block Lock-Down Status active logic supply highest performance program/erase voltage bits value bits value volts optimum program/erase supply voltage bits value bits value volts Addr. Code Value
(P+9)h
(P+A)h (P+B)h
(P+C)h
(P+D)h
12.0
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Table Protection Register Information
Offset(1) (P+E)h (P+F)h Length Description (Optional Flash Features Commands) Number Protection register fields JEDEC space. "00h," indicates that protection bytes available Protection Field Protection Description This field describes user-available Time Programmable (OTP) Protection register bytes. Some pre-programmed with deviceunique serial numbers. Others user programmable. Bits 0-15 point Protection register Lock byte, section's first byte. following bytes factory pre-programmed user-programmable. bits Lock/bytes JEDEC-plane physical address bits 8-15 Lock/bytes JEDEC -plane physical high address bits 16-23 such that factory pre- programmed bytes bits 24-31 such that user programmable bytes Addr. Code Value
(P+10)h (P+11)h
byte byte
(P+12)h (P+13)h Reserved future NOTE: variable pointer which defined offset 15h.
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Appendix Word-Wide Memory Diagrams
16-Mbit, 32-Mbit 64-Mbit [future], Word-Wide Memory Addressing
Boot Size (KW) 16-Mbit 32-Mbit 64-Mbit Size (KW) 16-Mbit Bottom Boot 32-Mbit 64-Mbit
FF000-FFFFF FE000-FEFFF FD000-FDFFF FC000-FCFFF FB000-FBFFF FA000-FAFFF F9000-F9FFF F8000-F8FFF F0000-F7FFF E8000-EFFFF E0000-E7FFF D8000-DFFFF D0000-D7FFF C8000-CFFFF C0000-C7FFF B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 00000-07FFF
1FF000-1FFFFF 3FF000-3FFFFF 1FE000-1FEFFF 3FE000-3FEFFF 1FD000-1FDFFF 3FD000-3FDFFF 1FC000-1FCFFF 3FC000-3FCFFF 1FB000-1FBFFF 3FB000-3FBFFF 1FA000-1FAFFF 3FA000-3FAFFF 1F9000-1F9FFF 3F9000-3F9FFF 1F8000-1F8FFF 3F8000-3F8FFF 1F0000-1F7FFF 3F0000-3F7FFF 1E8000-1EFFFF 3E8000-3EFFFF 1E0000-1E7FFF 3E0000-3E7FFF 1D8000-1DFFFF 3D8000-3DFFFF 1D0000-1D7FFF 3D0000-3D7FFF 1C8000-1CFFFF 3C8000-3CFFFF 1C0000-1C7FFF 3C0000-3C7FFF 1B8000-1BFFFF 3B8000-3BFFFF 1B0000-1B7FFF 3B0000-3B7FFF 1A8000-1AFFFF 3A8000-3AFFFF 1A0000-1A7FFF 3A0000-3A7FFF 198000-19FFFF 398000-39FFFF 190000-197FFF 390000-397FFF 188000-18FFFF 388000-38FFFF 180000-187FFF 380000-387FFF 178000-17FFFF 378000-37FFFF 170000-177FFF 370000-377FFF 168000-16FFFF 368000-36FFFF 160000-167FFF 360000-367FFF 158000-15FFFF 358000-35FFFF 150000-157FFF 350000-357FFF 148000-14FFFF 348000-34FFFF 140000-147FFF 340000-347FFF 138000-13FFFF 338000-33FFFF 130000-137FFF 330000-337FFF 128000-12FFFF 328000-32FFFF 120000-127FFF 320000-327FFF 118000-11FFFF 318000-31FFFF 110000-117FFF 310000-317FFF 108000-10FFFF 308000-30FFFF 100000-107FFF 300000-307FFF 0F8000-0FFFFF 2F8000-2FFFFF 0F0000-0F7FFF 2F0000-2F7FFF 0E8000-0EFFFF 2E8000-2EFFFF 0E0000-0E7FFF 2E0000-2E7FFF 0D8000-0DFFFF 2D8000-2DFFFF 0D0000-0D7FFF 2D0000-2D7FFF 0C8000-0CFFFF 2C8000-2CFFFF 0C0000-0C7FFF 2C0000-2C7FFF 0B8000-0BFFFF 2B8000-2BFFFF 0B0000-0B7FFF 2B0000-2B7FFF 0A8000-0AFFFF 2A8000-2AFFFF This column continues next page
This column continues next page
3F8000-3FFFFF 3F0000-3F7FFF 3E8000-3EFFFF 3E0000-3E7FFF 3D8000-3DFFFF 3D0000-3D7FFF 3C8000-3CFFFF 3C0000-3C7FFF 3B8000-3BFFFF 3B0000-3B7FFF 3A8000-3AFFFF 3A0000-3A7FFF 398000-39FFFF 390000-397FFF 388000-38FFFF 380000-387FFF 378000-37FFFF 370000-377FFF 368000-36FFFF 360000-367FFF 358000-35FFFF 350000-357FFF 348000-34FFFF 340000-347FFF 338000-33FFFF 330000-337FFF 328000-32FFFF 320000-327FFF 318000-31FFFF 310000-317FFF 308000-30FFFF 300000-307FFF 2F8000-2FFFFF 2F0000-2F7FFF 2E8000-2EFFFF 2E0000-2E7FFF 2D8000-2DFFFF 2D0000-2D7FFF 2C8000-2CFFFF 2C0000-2C7FFF 2B8000-2BFFFF 2B0000-2B7FFF 2A8000-2AFFFF 2A0000-2A7FFF 298000-29FFFF 290000-297FFF 288000-28FFFF 280000-287FFF 278000-27FFFF 270000-277FFF
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
16-Mbit, 32-Mbit, 64-Mbit [future], Word-Wide Memory Addressing
Boot Size (KW) 16-Mbit 32-Mbit 64-Mbit Size (KW) 16-Mbit Bottom Boot 32-Mbit 64-Mbit
2A0000-2A7FFF 298000-29FFFF 290000-297FFF 288000-28FFFF 280000-287FFF 278000-27FFFF 270000-277FFF 268000-26FFFF 260000-267FFF 258000-25FFFF 250000-257FFF 248000-24FFFF 240000-247FFF 238000-23FFFF 230000-237FFF 228000-22FFFF 220000-227FFF 218000-21FFFF 210000-217FFF 208000-21FFFF 200000-207FFF 1F8000-1FFFFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF 1D8000-1DFFFF 1D0000-1D7FFF 1C8000-1CFFFF 1C0000-1C7FFF 1B8000-1BFFFF 1B0000-1B7FFF 1A8000-1AFFFF 1A0000-1A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF 178000-17FFFF 170000-177FFF 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 128000-12FFFF 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF 0F8000-0FFFFF This column continues next page
0A0000-0A7FFF 098000-09FFFF 090000-097FFF 088000-08FFFF 080000-087FFF 078000-07FFFF 070000-077FFF 068000-06FFFF 060000-067FFF 058000-05FFFF 050000-057FFF 048000-04FFFF 040000-047FFF 038000-03FFFF 030000-037FFF 028000-02FFFF 020000-027FFF 018000-01FFFF 010000-017FFF 008000-00FFFF 000000-007FFF
1F8000-1FFFFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF 1D8000-1DFFFF 1D0000-1D7FFF 1C8000-1CFFFF 1C0000-1C7FFF 1B8000-1BFFFF 1B0000-1B7FFF 1A8000-1AFFFF 1A0000-1A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF 178000-17FFFF 170000-177FFF 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 128000-12FFFF 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF F8000-FFFFF F8000-FFFFF F0000-F7FFF F0000-F7FFF E8000-EFFFF E8000-EFFFF E0000-E7FFF E0000-E7FFF D8000-DFFFF D8000-DFFFF D0000-D7FFF D0000-D7FFF C8000-CFFFF C8000-CFFFF C0000-C7FFF C0000-C7FFF This column continues next page
268000-26FFFF 260000-267FFF 258000-25FFFF 250000-257FFF 248000-24FFFF 240000-247FFF 238000-23FFFF 230000-237FFF 228000-22FFFF 220000-227FFF 218000-21FFFF 210000-217FFF 208000-20FFFF 200000-207FFF 1F8000-1FFFFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF 1D8000-1DFFFF 1D0000-1D7FFF 1C8000-1CFFFF 1C0000-1C7FFF 1B8000-1BFFFF 1B0000-1B7FFF 1A8000-1AFFFF 1A0000-1A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF 178000-17FFFF 170000-177FFF 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 128000-12FFFF 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF F8000-FFFFF F0000-F7FFF E8000-EFFFF E0000-E7FFF D8000-DFFFF D0000-D7FFF C8000-CFFFF C0000-C7FFF
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
16-Mbit, 32-Mbit, 64-Mbit Word-Wide Memory Addressing
Boot Size (KW) 16-Mbit 32-Mbit 64-Mbit Size (KW) 16-Mbit Bottom Boot 32-Mbit 64-Mbit
0F0000-0F7FFF 0E8000-0EFFFF 0E0000-0E7FFF 0D8000-0DFFFF 0D0000-0D7FFF 0C8000-0CFFFF 0C0000-0C7FFF 0B8000-0BFFFF 0B0000-0B7FFF 0A8000-0AFFFF 0A0000-0A7FFF 098000-09FFFF 090000-097FFF 088000-08FFFF 080000-087FFF 078000-07FFFF 070000-077FFF 068000-06FFFF 060000-067FFF 058000-05FFFF 050000-057FFF 048000-04FFFF 040000-047FFF 038000-03FFFF 030000-037FFF 028000-02FFFF 020000-027FFF 018000-01FFFF 010000-017FFF 008000-00FFFF 000000-007FFF
B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF
B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF
B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Appendix Device Table
Table Device
Read Configuration Address Data Item Manufacturer Code Device Code 16-Mbit 16-T 16-Mbit 16-B 32-Mbit 16-T 32-Mbit 16-B 00001 00001 00001 00001 88C2 88C3 88C4 88C5 Address 00000 Data 0089
NOTE: Other locations within configuration address space reserved Intel future use.
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Appendix Protection Register Addressing
Table Protection Register Addressing
Word-Wide Protection Register Addressing Word LOCK Both Factory Factory Factory Factory User User User User
NOTE: address lines specified above table must when accessing Protection Register, i.e., A21-A8
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Appendix Mechanical Shipping Media Details
Mechanical Specification
Figure Stacked-CSP: Ball Matrix
Index
View Ball Down
Bottom View Ball
NOTE:
Shaded pins indicate upper address balls 64-Mbit 128-Mbit devices. Flash SRAM combinations, balls populated lower density devices. (Upper address balls populated).
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Table Packaging Specifications (0.18µm 0.25µm)
Millimeters Package Height Ball Height Package Body Thickness Ball Lead Diameter Package Body Length 16-Mbit/2-Mbit Package Body Length 32-Mbit/4-Mbit, 16-Mbit/4-Mbit Package Body Length 32-Mbit/8-Mbit Package Body Width 16-Mbit/2-Mbit, 16-Mbit/4-Mbit, 32-Mbit/4-Mbit, 32-Mbit/8-Mbit Pitch Ball (Lead) Count Seating Plane Coplanarity Corner Ball Distance Along 16-Mbit/2-Mbit, 16-Mbit/4-Mbit, 32-Mbit/4-Mbit, 32-Mbit/8-Mbit Corner Ball Distance Along 16-Mbit/2-Mbit Corner Ball Distance Along 32-Mbit/4-Mbit, 16-Mbit/4-Mbit Corner Ball Distance Along 32-Mbit/8-Mbit 0.500 1.500 2.500 0.600 1.600 2.600 0.700 1.700 2.700 0.0197 0.0591 0.0984 0.0236 0.0630 0.1024 0.0276 0.0669 0.1063 1.100 1.200 1.300 0.0433 0.0472 0.0512 0.800 0.100 0.0315 0.0039 7.900 8.000 8.100 0.3110 0.3150 0.3189 0.350 9.900 11.900 13.900 0.250 0.960 0.400 10.00 12.000 14.000 0.450 10.100 12.100 14.100 0.0138 0.3898 0.4685 0.5472 0.0098 0.0378 0.0157 0.3937 0.4724 0.5512 0.0177 0.3976 0.4764 0.5551 Inches 0.0551
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Table Packaging Specifications (0.13µm)
Millimeters Package Height 16/02-Mb, 16/04-Mb, 32/08-Mb Package Height 32/04-Mb Ball Height 16/02-Mb, 16/04-Mb, 32/08-Mb Ball Height 32/04-Mb Package Body Thickness 16/02-Mb, 16/04-Mb, 32/08-Mb Package Body Thickness 32/04-Mb Ball (Lead) Width 16/02-Mb, 16/04-Mb, 32/08-Mb Ball (Lead) Width 32/04-Mb Package Body Length 16/02-Mb, 16/04-Mb Package Body Length 32/04-Mb, 32/08-Mb Package Body Width 16/02-Mb, 16/04-Mb, 32/04-Mb, 32/08-Mb Pitch Ball (Lead) Count Seating Plane Coplanarity Corner Ball Distance Along 16/02-Mb, 16/04-Mb, 32/04-Mb, 32/08-Mb Corner Ball Distance Along 16/02-Mb, 16/04-Mb Corner Ball Distance Along 32/04-Mb, 32/08-Mb 0.500 1.500 0.600 1.600 0.700 1.700 0.0197 0.0591 0.0236 0.0630 0.0276 0.0669 1.100 1.200 11.900 7.900 12.000 8.000 0.800 0.100 1.300 0.0433 0.0472 12.100 8.100 0.4685 0.3110 0.4724 0.3150 0.0315 0.0039 0.0512 0.4764 0.3189 0.350 9.900 0.40 10.000 0.450 10.100 0.0138 0.3898 0.0157 0.3937 0.0177 0.3976 0.325 0.960 0.375 0.425 0.0128 0.0378 0.0148 0.0167 0.250 0.860 0.0098 0.0339 0.200 0.0079 0.0551 Inches 0.0472
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Media Information
Figure Stacked-CSP Device Tray Orientation
Device
Tray Chamfer
NOTE: Drawing scale only designed show orientation devices.
Figure Stacked-CSP Device Tape
Device
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Appendix Additional Information
Order Number 292216 292215 Contact Your Intel Representative 297874 Document/Tool AP-658 Designing Upgrade Advanced+ Boot Block Flash Memory AP-657 Designing with Advanced+ Boot Block Flash Memory Architecture Flash Data Integrator (FDI) Software Developer's Interactive: Play with Intel's Flash Data Integrator Your
NOTES: Please call Intel Literature Center (800) 548-4725 request Intel documentation. International customers should contact their local Intel distribution sales office. Visit Intel's World Wide home page http://www.Intel.com http://developer.intel.com technical documentation tools.
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Appendix Ordering Information
Table Ordering Information 0.25 0.18
Package
8x12 Ball Matrix
Access Speed (ns)
Mbit Mbit Blocking Bottom Blocking
Product Line Designator Intel Flash products Flash Density
Mbit) Mbit)
Product Family
Advanced+ Boot Block 1.65 11.4 12.6
SRAM Device Density
Mbit) Mbit) Mbit)
Table Ordering Information Combinations with 0.13 Flash
Package
Stacked-CSP
Access Speed (ns)
Mbit
Product Line Designator Intel Flash Stacked Memory Flash Density
Mbit) Mbit)
Technology Differentiator
0.13µm
Parameter Location
Blocking Bottom Blocking
SRAM Device Density
Mbit) Mbit)
Product Family
Advanced+ Boot Block Flash Memory
Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Table Ordering Information Combinations with 0.13 Flash
Package
Stacked-CSP
Device Details
Original Version this product: Flash Speed Flash Process 0.13 Vccq
Product Line Designator Intel Flash Stacked Memory Density
Flash Mbit Flash Flash Mbit SRAM Mbit SRAM Flash
Pinout Indicator
ball "I"-ballout
Parameter Location
Blocking Bottom Blocking
Product Family
Advanced+ Boot Block Flash Memory
Voltage
3.0V
Table Ordering Information Valid Combinations
0.25µm Stacked-CSP longer available. 0.18µm Stacked-CSP RD28F3208C3T70 RD28F3208C3B70 32-Mbit RD28F3208C3T90 RD28F3208C3B90 RD28F3204C3T70 RD28F3204C3B70 RD28F1604C3T90 RD28F1604C3B90 RD28F1604C3T110 16-Mbit RD28F1604C3B110 RD28F1602C3T90 RD28F1602C3B90 RD28F1602C3T110 RD28F1602C3B110 RD28F1602C3T70 RD28F1602C3B70 RD28F1602C3TD70 RD28F1602C3BD70 RD28F1604C3TD70 RD28F1604C3BD70 0.13µm Stacked-CSP RD38F1010C0ZTL0 RD38F1010C0ZBL0 RD38F1020C0ZTL0 RD38F1020C0ZBL0
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