HN27C4000G Series 524288-Word 8-Bit/262144-Word 16-Bit CMOS Erasa
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ADE-203-311A
HN27C4000G Series
524288-Word 8-Bit/262144-Word 16-Bit CMOS Erasable Programmable
Rev. Nov. 1994
Hitachi HN27C4000 4-Mbit erasable electrically programmable that organized either 524288-word 262144-word bit, featuring extra-high speed burst mode that gives times faster 4-word 8byte serial access than normal. also high speed fast programming served well existing Hitachi device HN27C4096 HN27C4001. Fabricated advanced fine process high speed circuitry technique, HN27C4000 makes high speed access time power dissipation either active stand-by mode. Therefore, suitable systems featuring high speed microprocessor such 80386, 80486, 68030, 68040
Features
Organization: 524288-word 8-bit/262144word 16-bit (BYTE/VPP enables selection byte-wide word-wide) High speed: Access time ns/120 ns/150 (max) Burst access time ns/60 ns/60 (max) power dissipation: Standby mode; (typ), Active mode; mW/MHz (typ) Fast high reliability page programming, fast high-reliability programming option programming: Program voltage; +12.5 Program time; (min) (Theoretical Page programming) Inputs outputs compatible during both read program modes arrangement: 40-pin EIAJ standard compatible with HN62414/ HN62434 Device identifier mode: Manufacturer code device code
HN27C4000G Series
Arrangement
HN27C4000G Series I/O0 I/O8 I/O1 I/O9 I/O2 I/O10 I/O3 I/O11 BYTE/VPP I/O15/A-1 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4
(Top view)
Ordering Information
Type HN27C4000G-10 HN27C4000G-12 HN27C4000G-15 Access time Package 600-mil 40-pin cerdip (DG-40A)
Description
name I/O0 I/O14 I/O15/A-1 BYTE/VPP Function Address Input/output Input/output/address Chip enable Output enable Power supply Byte/word selection/ Programming power supply Ground
HN27C4000G Series
Block Diagram
XDecoder
2,048 2,048 Memory Matrix
I/O0
I/O15
Input Data Control
Y-Gating Y-Decoder
High threshold inverter
Mode Selection
Mode Read (X16 bit) Read bit) Output disable (X16 bit) Output disable bit) DG-40A (10) (12) (39) BYTE/VPP (31) (21) I/O0 I/O7, I/O8 I/O14, I/O15/A-1 Dout Dout High-Z High-Z Dout High-Z High-Z High-Z Dout VIH/VIL High-Z VIH/VIL
HN27C4000G Series
Mode Selection (cont)
Mode Standby Page Page program prog. Page data latch Page program DG-40A (10) (12) VH*2 VH*2 (39)
BYTE/VPP (31) (21)
I/O0 I/O7, I/O8 I/O14, I/O15/A-1 High-Z High-Z High-Z Dout High-Z Dout Dout High-Z Code High-Z High-Z High-Z Dout High-Z Dout Dout High-Z Code High-Z High-Z High-Z Dout High-Z Dout Dout High-Z Code
Page program verify Page program reset Word Program prog. Program verify Optional verify Program inhibit Identifier
Notes: Don't care. 12.0
Absolute Maximum Ratings
Item input output
Symbol voltages*1 Vin, Vout Topr Tstg Tbias
Value -0.6*2 -0.6*2 +7.0 +13.0
Unit
Voltage voltage voltage
-0.6 +13.5 -0.6 +7.0 +125
Operating temperature range Storage temperature range
Storage temperature under bias
Notes: Relative VSS. Vin, Vout, -2.0 pulse width Storage temperature range device before programming.
HN27C4000G Series
Capacitance 25°C, MHz)
Item Input capacitance Output capacitance Symbol Cout Unit Test conditions Vout Notes Except BYTE/VPP
Read Operation
Characteristics (VCC 10%, VCC, +70°C)
Item Input leakage current Output leakage current current Standby current Operating current Input voltage Symbol IPP1 ISB1 ISB2 ICC1 ICC2 Output voltage -0.3*1 0.45 Unit -400 Test conditions Vout V/0.45 Iout Iout
Notes: -1.0 pulse width -2.0 pulse width +1.5 pulse width over specified maximum value, read operation cannot guaranteed.
HN27C4000G Series
Characteristics (VCC 10%, VCC, +70°C)
Test Conditions Input pulse levels: 0.45 Input rise fall times: Output load: gate +100 Reference levels measuring timing:
HN27C4000 HN27C4000 HN27C4000 Item Address output delay output delay output delay Burst address output delay high output float Address output hold Note: Symbol tACC tBAC Unit Test conditions
defined time which output achieves open circuit condition data longer driven.
Read Timing Waveform
Address
Standby mode
Active mode
Standby mode
Data Data Valid
HN27C4000G Series
Read Timing Waveform (Burst access mode)
Burst Access mode, fast read-out word data selected address (Valid only Read mode)
tBAC tBAC
Valid Output Valid Output Valid Output
Data
Valid Output
HN27C4000G Series
Burst Access mode, fast read-out byte data selected address A-1, (Valid only Read mode)
tBAC tBAC tBAC tBAC tBAC tBAC tBAC
A-1,
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Data
Valid Output
HN27C4000G Series
Fast High-Reliability Page Programming
This device applied high performance page programming algorithm shown following flowchart. This algorithm allows obtain faster programming time without voltage stress device deterioration reliability programmed data. Page Program Apply after applying 12.5 page program mode. device operates page program mode until reset. Page Program Reset level less reset page program mode.
START PAGE PROG LATCH MODE VPP= 12.5 6.25 0.25 12.0 Address Latch Address Address Latch Address Address Latch Address Address Latch PAGE PROG./VERIFY MODE 12.5 6.25 0.25 Address Address Program VERIFY LAST address? NOGO
READ MODE READ address Fast High-Reliability Page Programming Flowchart NOGO
FAIL
HN27C4000G Series
Characteristics (VCC 6.25 0.25 12.5 25°C 5°C)
Item Input leakage current Output voltage during verify Symbol Operating current Input voltage supply current -0.1*5 11.5 12.0 0.45 0.5*6 12.5 Unit Test conditions V/0.45 -400
Notes: must applied simultaneously before removed simultaneously after VPP. must exceed including overshoot. influence upon device reliability device installed removed while 12.5 alter either 12.5 12.5 when low. -0.6 pulse width over specified maximum value, programming operation cannot guaranteed.
HN27C4000G Series
Characteristics (VCC 6.25 0.25 12.5 25°C 5°C)
Test Conditions Input pulse levels: 0.45 Input rise fall times: Reference levels measuring timing: Inputs; Outputs;
Item Address setup time setup time Data setup time Address hold time Data hold time high output float delay setup time setup time initial programming pulse width setup time Data valid from pulse width during data latch setup time hold time hold time*2 Symbol tOES
47.5
50.0
52.5
Unit
Test conditions
tVPS tVCS tCES tOHS tOHH tVRS
Notes: defined time which output achieves open circuit condition data longer driven. Page program mode will reset when less.
HN27C4000G Series
Fast High-Reliability Page Programming Timing Waveform
Page program mode Program data latch Data Data stable Data valid
Page program
Program verify
1.25
HN27C4000G Series
Fast High-Reliability Programming
This device applied fast high-reliability programming algorithm shown following flowchart. This algorithm allows obtain faster programming time without voltage stress device deterioration reliability programmed data.
START PROG./VERIFY MODE 12.5 6.25 0.25 Address
Program Address Address VERIFY LAST address? NOGO
READ MODE READ address NOGO
FAIL
Fast High-Reliability Programming Flowchart
HN27C4000G Series
Characteristics (VCC 6.25 0.25 =12.5 Ta=25°C 5°C)
Item Input leakage current supply current Operating current Input voltage Symbol Output voltage -0.1*5 0.5*6 0.45 Unit -400 Test conditions V/0.45
Notes: must applied simultaneously before removed simultaneously after VPP. must exceed including overshoot. influence upon device reliability device installed removed while 12.5 alter either 12.5 12.5 when low. -0.6 pulse width over specified maximum value, programming operation cannot guaranteed.
Characteristics (VCC 6.25 0.25 12.5 25°C 5°C) Test Conditions Input pulse levels: 0.45 Input rise fall times: Reference levels measuring timings:
Item Address setup time setup time Data setup time Address hold time Data hold time output float delay setup time setup time initial programming pulse width Data valid from Note: Symbol tOES tDF*1 tVPS tVCS 47.5 50.0 52.5 Unit Test conditions
defined time which output achieves open circuit condition data longer driven.
HN27C4000G Series
Fast High-Reliability Programming Timing Waveform
Program Address Data CC+1.25 Data Stable
Program Verify
Data Valid
Optional Page Programming
This device applied optional page programming algorithm shown following flowchart. This algorithm allows obtain faster programming time without voltage stress device deterioration reliability programmed data. This programming algorithm combination page programming word verify. avoid increase programming verify time when programmer with slow machine cycle used, shorten total programming time. Regarding timing specifications page programming word verify, please refer specifications fast high-reliability page programming fast high-reliability programming.
HN27C4000G Series
START PAGE PROG LATCH MODE VPP= 12.5 6.25 0.25 12.0 Address Latch Address Latch Address Latch Address Latch PAGE PROG. MODE 12.5 6.25 0.25 Address Address Program LAST address? Address Address Address
PAGE PROG. RESET 6.25 0.25 WORD PROG./VERIFY MODE 12.5 6.25 0.25 Address VERIFY NOGO Address Address Program VERIFY LAST address? READ MODE READ address Optional Page Programming Flowchart FAIL NOGO NOGO
HN27C4000G Series
Characteristics (VCC 6.25 0.25 =12.5 25°C 5°C)
Item Input leakage current Output voltage during verify Symbol Operating current Input voltage supply current -0.1*5 11.5 12.0 0.45 0.5*6 12.5 Unit Test conditions V/0.45 -400
Notes: must applied simultaneously before removed simultaneously after VPP. must exceed including overshoot. influence upon device reliability device installed removed while 12.5 alter either 12.5 12.5 when low. -0.6 pulse width over specified maximum value, programming operation cannot guaranteed.
HN27C4000G Series
Characteristics (VCC 6.25 0.25 12.5 25°C 5°C) Test Conditions Input pulse levels: 0.45 Input rise fall times: Reference levels measuring timings: Inputs; Outputs;
Item Address setup time setup time Data setup time Address hold time Data hold time high output float delay setup time setup time initial programming pulse width setup time Data valid from pulse width during data latch setup time hold time Page programming reset time hold time Symbol tOES
47.5
50.0
52.5
Unit
Test conditions
tVPS tVCS tCES tOHS tOHH tVLW tVRS
Notes: defined time which output achieves open circuit condition data longer driven. Page program mode will reset when less.
HN27C4000G Series
Option Page Programming Timing Waveform
Page program mode Program data latch Page program
Word program mode Program verify
Program
Data stable
Data valid
Data stable
Data
VCC+ 1.25
HN27C4000G Series
Erase
Erasure this device performed exposure ultraviolet light 2537 output data changed after this erasure procedure. minimum integrated dose (i.e. intensity exposure time) erasure
Mode Description
Device Identifier Mode device identifier mode allows reading binary codes that identify manufacturer type device, from outputs EPROM. this mode, device will automatically matched corresponding programming algorithm, using programming equipment.
HN27C4000G Identifier Code
Identifier DG-40 I/O8 I/O15 I/O7 (28) I/O6 (26) I/O5 (24) I/O4 (22) I/O3 (19) I/O2 (17) I/O1 (15) I/O0 (13) Data
Manufacturer code Device code Notes:
12.0 A17: Don't care. Don't care.
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