Base datasheet: GS88219/37AB, Rev.1.00, 3/2002 Product(s) co

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GS88219/37AB
Base datasheet:
GS88219/37AB, Rev.1.00, 3/2002
Product(s) covered this supplement:
Product specification(s) addressed this supplement:
Bump Note: specifications cited base datasheet products addressed this errata remain force except where superseded information this errata.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
GS88219/37AB
GS88237A
Bump BGA-Top View
VDDQ DQC4 DQC3 VDDQ DQC2 DQC1 VDDQ DQD1 DQD2 VDDQ DQD3 DQD4 VDDQ
DQC9 DQC8 DQC7 DQC6 DQC5 DQD5 DQD6 DQD7 DQD8 DQD9
ADSP ADSC
VDDQ/
DQB9 DQB8 DQB7 DQB6 DQB5 DQA5 DQA6 DQA7 DQA8 DQA9
VDDQ DQB4 DQB3 VDDQ DQB2 DQB1 VDDQ DQA1 DQA2 VDDQ DQA3 DQA4 VDDQ
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
GS88219/37AB
GS88219A
Bump BGA-Top View
VDDQ DQB1 VDDQ DQB4 VDDQ DQB6 VDDQ DQB8 VDDQ
DQB2 DQB3 DQB5 DQB7 DQB9
ADSP ADSC
VDDQ/
DQA9 DQA7 DQA5 DQA3 DQA2
VDDQ DQA8 VDDQ DQA6 VDDQ DQA4 VDDQ DQA1 VDDQ
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
GS88219/37AB
GS88219/37A Description
Location
Symbol
DQA1-DQA9 DQB1-DQB9 DQC1-DQC9 DQD1-DQD9 DQA1-DQA9 DQB1-DQB9 ADSP, ADSC
Type
Description
Address field LSBs Address Counter Preset Inputs Address Inputs Address Input (x36 Versions) Connect (x36 Versions) Address Input (x18 Version) Data Input Output pins (x36 Versions) Byte Write Enable DQA, DQB, DQC, I/Os; active (x36 Version) Data Input Output pins (x18 Version) Byte Write Enable DQA, I/Os; active (x18 Version) Connect Connect (x18 Version) Clock Input Signal; active high Byte Write-Writes enabled bytes; active Global Write Enable-Writes bytes; active Chip Enable; active Output Enable; active Burst address counter advance enable; active Address Strobe (Processor, Cache Controller); active Sleep Mode control; active high Linear Burst Order mode; active Single Cycle Deselect/Dual Cycle Deselect Mode Control Parity Enable; active (High x16/32 Mode, x18/36 Mode) FLXDrive Output Impedance Control (Low Impedance [High Drive], High High Impedance [Low Drive]) Scan Test Mode Select
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
GS88219/37AB
GS88219/37A Description
Location
Symbol
VDDQ VDDQ/DNU
Type
Description
Scan Test Data Scan Test Data Scan Test Clock Core power supply Core Ground Output driver power supply VDDQ (must tied high) (must left floating)
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary 119-Bump Commercial Temp Industrial Temp Features
Single/Dual Cycle Deselect selectable IEEE 1149.1 JTAG-compatible Boundary Scan mode user-selectable high/low output drive +10%/-10% core power supply supply Linear Interleaved Burst mode Internal input resistors mode pins allow floating mode pins Default x18/x36 Interleaved Pipeline mode Byte Write (BW) and/or Global Write (GW) operation Internal self-timed write cycle Automatic power-down portable applications JEDEC-standard 119-bump package
512K 256K SCD/DCD Sync Burst SRAMs
MHz-133MHz
captured input registers. RAMs hold deselect command full cycle then begin turning their outputs just after second rising edge clock. user configure this SRAM either mode operation using mode input.
Byte Write Global Write
Byte write operation performed using Byte Write enable (BW) input combined with more individual byte write signals (Bx). addition, Global Write (GW) available writing bytes time, regardless Byte Write control inputs.
FLXDriveallows selection between high drive strength low) multi-drop applications normal drive strength floating high) point-to-point applications. Output Driver Characteristics chart details.
Pipeline 3-1-1-1
tCycle Curr (x18) Curr (x36) Curr (x18) Curr (x36)
-250 -225 -200 -166 -150 -133 Unit
Sleep Mode
power (Sleep mode) attained through assertion (High) signal, stopping clock (CK). Memory data retained during Sleep mode.
Core Interface Voltages
GS88219/37AB operates power supply. input compatible. Separate output power (VDDQ) pins used decouple output noise from internal circuits compatible.
Functional Description
Applications
GS88219/37AB 9,437,184-bit high performance synchronous SRAM with 2-bit burst address counter. Although type originally developed Level Cache applications supporting high performance CPUs, device finds application synchronous SRAM applications, ranging from main store networking chip support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), write control inputs (Bx, synchronous controlled positive-edgetriggered clock input (CK). Output enable power down control (ZZ) asynchronous inputs. Burst cycles initiated with either ADSP ADSC inputs. Burst mode, subsequent burst addresses generated internally controlled ADV. burst address counter configured count either linear interleave order with Linear Burst Order (LBO) input. Burst function need used. addresses loaded every cycle with degradation chip performance.
Pipelined Reads
GS88219/37AB (Single Cycle Deselect) (Dual Cycle Deselect) pipelined synchronous SRAM. SRAMs pipeline disable commands same degree read commands. SRAMs pipeline deselect commands stage less than read commands. RAMs begin turning their outputs immediately after deselect command been
Rev: 1.00 3/2002
1/36
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary GS88237A
Bump BGA-Top View
VDDQ DQC4 DQC3 VDDQ DQC2 DQC1 VDDQ DQD1 DQD2 VDDQ DQD3 DQD4 VDDQ
DQC9 DQC8 DQC7 DQC6 DQC5 DQD5 DQD6 DQD7 DQD8 DQD9
ADSP ADSC
DQB9 DQB8 DQB7 DQB6 DQB5 DQA5 DQA6 DQA7 DQA8 DQA9
VDDQ DQB4 DQB3 VDDQ DQB2 DQB1 VDDQ DQA1 DQA2 VDDQ DQA3 DQA4 VDDQ
Rev: 1.00 3/2002
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2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary GS88219A
Bump BGA-Top View
VDDQ DQB1 VDDQ DQB4 VDDQ DQB6 VDDQ DQB8 VDDQ
DQB2 DQB3 DQB5 DQB7 DQB9
ADSP ADSC
DQA9 DQA7 DQA5 DQA3 DQA2
VDDQ DQA8 VDDQ DQA6 VDDQ DQA4 VDDQ DQA1 VDDQ
BPR1999.05.18
Rev: 1.00 3/2002
3/36
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary GS88219/37A Description
Location
Symbol
DQA1-DQA9 DQB1-DQB9 DQC1-DQC9 DQD1-DQD9 DQA1-DQA9 DQB1-DQB9 ADSP, ADSC
Type
Description
Address field LSBs Address Counter Preset Inputs Address Inputs Address Input (x36 Versions) Connect (x36 Versions) Address Input (x18 Version) Data Input Output pins (x36 Versions) Byte Write Enable DQA, DQB, DQC, I/Os; active (x36 Version) Data Input Output pins (x18 Version) Byte Write Enable DQA, I/Os; active (x18 Version) Connect Connect (x18 Version) Clock Input Signal; active high Byte Write-Writes enabled bytes; active Global Write Enable-Writes bytes; active Chip Enable; active Output Enable; active Burst address counter advance enable; active Address Strobe (Processor, Cache Controller); active Sleep Mode control; active high Linear Burst Order mode; active Single Cycle Deselect/Dual Cycle Deselect Mode Control Parity Enable; active (High x16/32 Mode, x18/36 Mode) FLXDrive Output Impedance Control (Low Impedance [High Drive], High High Impedance [Low Drive])
Rev: 1.00 3/2002
4/36
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary GS88219/37A Description
Location
Symbol
VDDQ
Type
Description
Scan Test Mode Select Scan Test Data Scan Test Data Scan Test Clock Core power supply Core Ground Output driver power supply
Rev: 1.00 3/2002
5/36
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary
GS88219/37A Block Diagram
Register
A0-An
Counter Load
ADSC ADSP
Register
Memory Array
Register
Register
Register
Register
Register
Register
Register
Parity Encode Parity Compare
Register
Power Down Control
DQx1-DQx9
Note: Only version shown simplicity.
Rev: 1.00 3/2002
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2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Register
Preliminary
GS88219/37A Mode Block Diagram
Register
A0-An
Counter Load
ADSC ADSP
Register
Memory Array
Parity Encode
Register
Register
Register
Register
Register
Register
Register
Register
Parity Encode Parity Compare
Register
Register
Power Down Control
DQx1-DQx9
Note: Only version shown simplicity.
Rev: 1.00 3/2002
7/36
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary
Mode Functions Mode Name
Burst Order Control Power Down Control Single/Dual Cycle Deselect Control FLXDrive Output Impedance Control
Name
State
Function
Linear Burst Interleaved Burst Active Standby, Dual Cycle Deselect Single Cycle Deselect High Drive (Low Impedance) Drive (High Impedance)
Note: Thereis pull-down device pin, this input unconnected chip will operate default states specified above tables.
Enable Disable Parity Pins
This SRAM allows user configure device operate Parity active (x18, x36, x72) Parity inactive (x16, x32, x64) mode. Holding bump letting float will activate each byte RAM. Grounding deactivates each byte.
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0]
address address address address
A[1:0] A[1:0] A[1:0] A[1:0]
address address address address
Note: burst counter wraps initial state clock.
Note: burst counter wraps initial state clock.
1999.05.18
Rev: 1.00 3/2002
8/36
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary
Byte Write Truth Table Function
Read Read Write byte Write byte Write byte Write byte Write bytes Write bytes
Notes
Notes: byte outputs active read cycles regardless state Byte Write Enable inputs. Byte Write Enable inputs and/or used combination with write single multiple bytes. byte I/Os remain High-Z during write operations regardless state Byte Write Enable inputs. Bytes only available version.
Rev: 1.00 3/2002
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2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary
Synchronous Truth Table Operation
Deselect Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst
Address Used
None External External External Next Next Next Next Current Current Current Current
State Diagram Key5
ADSP
ADSC
High-Z
Notes: Don't Care, High, (True) (False) defined Byte Write Truth Table preceding asynchronous input. driven high time disable active output drivers. only enable active drivers (shown Truth Table above). input combinations shown above tested supported. Input combinations shown gray boxes need used accomplish basic synchronous synchronous burst operations avoided simplicity. Tying ADSP high ADSC allows simple non-burst synchronous operations. BOLD items above. Tying ADSP high while using ADSC load addresses allows simple burst operations. ITALIC items above.
Rev: 1.00 3/2002
10/36
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary Simplified State Diagram
Deselect Simple Synchronous Operation
First Write
First Read
Simple Burst Synchronous Operation
Burst Write
Burst Read
Notes: diagram shows only supported (tested) synchronous state transitions. diagram presumes tied low. upper portion diagram assumes active only Enable (E1) Write (BA, control inputs, that ADSP tied high ADSC tied low. upper lower portions diagram together assume active only Enable, Write, ADSC control inputs assumes ADSP tied high tied low.
Rev: 1.00 3/2002
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2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary Simplified State Diagram with
Deselect
First Write
First Read
Burst Write
Burst Read
Notes: diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon "Dummy Reads" (Read Cycles with High) used make transition from read cycles write cycles without passing through Deselect cycle. Dummy Read cycles increment address counter just like normal read cycles. Transitions shown grey tone assume been pulsed high long enough turn RAM's drivers incoming data meet Data Input Time.
Rev: 1.00 3/2002
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2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary
Absolute Maximum Ratings
(All voltages reference VSS)
Symbol
VDDQ VI/O IOUT TSTG TBIAS
Description
Voltage Pins Voltage VDDQ Pins Voltage Clock Input Voltage Pins Voltage Other Input Pins Input Current Output Current Package Power Dissipation Storage Temperature Temperature Under Bias
Value
-0.5 -0.5 -0.5 -0.5 VDDQ +0.5 max.) -0.5 +0.5 max.) +/-20 +/-20
Unit
Note: Permanent damage device occur Absolute Maximum Ratings exceeded. Operation should restricted Recommended Operating Conditions. Exposure conditions exceeding Absolute Maximum Ratings, extended period time, affect reliability this component.
Rev: 1.00 3/2002
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2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary
Power Supply Voltage Ranges Parameter
Supply Voltage Supply Voltage VDDQ Supply Voltage VDDQ Supply Voltage
Symbol
VDD3 VDD2 VDDQ3 VDDQ2
Min.
Typ.
Max.
Unit
Notes
Notes: part numbers Industrial Temperature Range versions character "I". Unless otherwise noted, performance specifications quoted evaluated worst case temperature range marked device. Input Under/overshoot voltage must VDDn+2 exceed maximum, with pulse width exceed tKC.
VDDQ3 Range Logic Levels Parameter
Input High Voltage Input Voltage VDDQ Input High Voltage VDDQ Input Voltage
Symbol
VIHQ VILQ
Min.
-0.3 -0.3
Typ.
Max.
VDDQ
Unit
Notes
Notes: part numbers Industrial Temperature Range versions character "I". Unless otherwise noted, performance specifications quoted evaluated worst case temperature range marked device. Input Under/overshoot voltage must VDDn+2 exceed maximum, with pulse width exceed tKC. VIHQ (max) voltage VDDQ pins plus
VDDQ2 Range Logic Levels Parameter
Input High Voltage Input Voltage VDDQ Input High Voltage VDDQ Input Voltage
Symbol
VIHQ VILQ
Min.
0.6*VDD -0.3 0.6*VDD -0.3
Typ.
Max.
0.3*VDD VDDQ 0.3*VDD
Unit
Notes
Notes: part numbers Industrial Temperature Range versions character "I". Unless otherwise noted, performance specifications quoted evaluated worst case temperature range marked device. Input Under/overshoot voltage must VDDn+2 exceed maximum, with pulse width exceed tKC. VIHQ (max) voltage VDDQ pins plus
Rev: 1.00 3/2002
14/36
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary
Recommended Operating Temperatures Parameter
Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions)
Symbol
Min.
Typ.
Max.
Unit
Notes
Note: part numbers Industrial Temperature Range versions character "I". Unless otherwise noted, performance specifications quoted evaluated worst case temperature range marked device. Input Under/overshoot voltage must VDDn+2 exceed maximum, with pulse width exceed tKC.
Undershoot Measurement Timing
Overshoot Measurement Timing
Capacitance
25oC, MHZ,
Parameter
Input Capacitance Input/Output Capacitance Note: These parameters sample tested.
Symbol
CI/O
Test conditions
VOUT
Typ.
Max.
Unit
Package Thermal Characteristics Rating
Junction Ambient lfm) Junction Ambient lfm) Junction Case (TOP)
Layer Board
single four
Symbol
Unit
°C/W °C/W °C/W
Notes
Notes: Junction temperature function SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature flow, board density, thermal resistance. SCMI G-38-87 Average thermal resistance between surface, SPEC-883, Method 1012.1
Rev: 1.00 3/2002
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2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary
Test Conditions Parameter
Input high level Input level Input slew rate Input reference level Output reference level
Conditions
V/ns VDD/2 VDDQ/2
Output load Fig. Notes: Include scope capacitance. Test conditions specified with output loading shown Fig. unless otherwise noted. Device deselected defined Truth Table.
Output Load VDDQ/2 Distributed Test Capacitance 30pF*
Electrical Characteristics Parameter
Input Leakage Current (except mode pins) Input Current Input Current Output Leakage Current Output High Voltage Output High Voltage Output Voltage
Symbol
IIN1 IIN2 VOH2 VOH3
Test Conditions
Output Disable, VOUT VDDQ 2.375 VDDQ 3.135
-100
Rev: 1.00 3/2002
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2002, Giga Semiconductor, Inc.
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Operating Currents
-250 Mode IDDQ IDDQ IDDQ IDDQ Symbol 70°C 85°C Unit
-225 70°C 85°C 85°C 85°C 85°C 85°C 70°C 70°C 70°C 70°C
-200
-166
-150
-133
Rev: 1.00 3/2002 (x36) (x18) (x36) (x18) Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline
Parameter
Test Conditions
Operating Current
Device Selected; other inputs Output open
Operating Current
Device Selected; other inputs Output open
Standby Current
17/36
Deselect Current
Device Deselected; other inputs
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Notes: IDDQ apply combination VDD3, VDD2, VDDQ3, VDDQ2 operation. parameters listed worst case scenario.
Preliminary
2002, Giga Semiconductor, Inc.
Preliminary Electrical Characteristics
Parameter Clock Cycle Time Clock Output Valid Clock Output Invalid Pipeline Clock Output Low-Z Setup time Hold time Output Valid output High-Z Clock HIGH Time Clock Time Clock Output High-Z output Low-Z setup time hold time recovery Symbol tKQX tOHZ1 tHZ1 tOLZ1 tZZS2 tZZH2 tZZR
-250
-225
-200
-166
-150
-133
Unit
Notes: These parameters sampled 100% tested. asynchronous signal. However, order recognized given clock cycle, must meet specified setup hold times specified above.
Rev: 1.00 3/2002
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2002, Giga Semiconductor, Inc.
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Preliminary Write Cycle Timing
Single Write
Burst Write
Write
Deselected
ADSP blocked inactive
ADSP
ADSC initiated write
ADSC
must inactive ADSP Write
A0-An
BA-BD
masks ADSP
only sampled with ADSP ADSC
Write specified byte bytes
DQA-DQD
Hi-Z
Rev: 1.00 3/2002
19/36
2002, Giga Semiconductor, Inc.
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Preliminary Pipelined Read Cycle Timing
Single Read Burst Read ADSC initiated read ADSP blocked inactive
ADSP ADSC
Suspend Burst
A0-An
BWA-BWD
masks ADSP
DQA-DQD
Hi-Z tOLZ
tOHZ tKQX
tKQX
Rev: 1.00 3/2002
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2002, Giga Semiconductor, Inc.
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Preliminary Pipelined Read-Write Cycle Timing
Single Read
Single Write
Burst Read
ADSP blocked inactive
ADSP
ADSC initiated read
ADSC
A0-An
BWA-
masks ADSP
tOHZ
DQA-DQD
Hi-Z
Rev: 1.00 3/2002
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2002, Giga Semiconductor, Inc.
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Preliminary Pipelined Read Cycle Timing
Single Read Burst Read
ADSP blocked inactive
ADSP
ADSC initiated read
ADSC
Suspend Burst
A0-An
BA-BD
masks ADSP
tOHZ Hi-Z tOLZ tKQX tKQX
DQA-DQD
Rev: 1.00 3/2002
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2002, Giga Semiconductor, Inc.
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Preliminary Pipelined Read-Write Cycle Timing
Single Write Single Read Burst Read
ADSP blocked inactive
ADSP
ADSC initiated read
ADSC
A0-An
BA-BD
masks ADSP
tOHZ
DQA-DQD
Hi-Z
Rev: 1.00 3/2002
23/36
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary
Sleep Mode
During normal operation, must pulled low, either user it's internal pull down resistor. When pulled high, SRAM will enter Power Sleep mode after cycles. this time, internal state SRAM preserved. When returns low, SRAM operates normally after recovery time. Sleep mode current, power-down mode which device deselected current reduced ISB2. duration Sleep mode dictated length time high state. After entering Sleep mode, inputs except become disabled outputs High-Z asynchronous, active high input that causes device enter Sleep mode. When driven high, ISB2 guaranteed after time tZZI met. Because asynchronous input, pending operations operations progress properly completed asserted. Therefore, Sleep mode must initiated until valid pending operations completed. Similarly, when exiting Sleep mode during tZZR, only Deselect Read commands applied while SRAM recovering from Sleep mode.
Sleep Mode Timing Diagram
ADSP ADSC
tZZS
tZZH
tZZR
Snooze
Application Tips
Single Dual Cycle Deselect
devices (like this one) force "dummy read cycles" (read cycles that launched normally, that ended with output drivers inactive) fully synchronous environment. Dummy read cycles waste performance, their usually assures there will contention transitions from reads writes between banks RAMs. SRAMs waste bandwidth dummy cycles logically simpler manage multiple bank application (wait states need inserted bank address boundary crossings), greater care must exercised avoid excessive contention.
JTAG Port Operation
Overview
JTAG Port this operates manner that compliant with IEEE Standard 1149.1-1990, serial boundary scan interface standard (commonly referred JTAG). JTAG Port input interface levels scale with VDD. JTAG output drivers powered VDDQ.
Disabling JTAG Port
possible this device without utilizing JTAG port. port reset power-up will remain inactive unless clocked. TCK, TDI, designed with internal pull-up circuits.To assure normal operation with JTAG Port unused, TCK, TDI, left floating tied either VSS. should left unconnected. Rev: 1.00 3/2002 24/36 2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary
JTAG Descriptions
Name
Test Clock Test Mode Select
Description
Clocks events. inputs captured rising edge outputs propagate from falling edge TCK. input sampled rising edge TCK. This command input controller state machine. undriven input will produce same result logic input level. input sampled rising edge TCK. This input side serial registers placed between TDO. register placed between determined state Controller state machine instruction that currently loaded Instruction Register (refer Controller State Diagram). undriven will produce same result logic input level.
Test Data
Test Data
Output that active depending state state machine. Output changes response falling edge TCK. This output side serial registers placed between TDO.
Note: This device does have TRST (TAP Reset) pin. TRST optional IEEE 1149.1. Test-Logic-Reset state entered while held high five rising edges TCK. Controller also reset automaticly power-up.
JTAG Port Registers
Overview
various JTAG registers, refered Test Access Port orTAP Registers, selected (one time) sequences applied strobed. Each Registers serial shift register that captures serial input data rising edge pushes serial data next falling edge TCK. When register selected, placed between pins.
Instruction Register
Instruction Register holds instructions that executed controller when moved into Run, Test/Idle, various data register states. Instructions bits long. Instruction Register loaded when placed between pins. Instruction Register automatically preloaded with IDCODE instruction power-up whenever controller placed Test-Logic-Reset state.
Bypass Register
Bypass Register single register that placed between TDO. allows serial test data passed through RAM's JTAG Port another device scan chain with little delay possible.
Boundary Scan Register
Boundary Scan Register collection flip flops that preset logic level found RAM's input pins. flip flops then daisy chained together levels found shifted serially JTAG Port's pin. Boundary Scan Register also includes number place holder flip flops (always logic relationship between device pins bits Boundary Scan Register described Scan Order Table following. Boundary Scan Register, under control Controller, loaded with contents RAMs ring when controller Capture-DR state then placed between pins when controller moved Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD EXTEST instructions used activate Boundary Scan Register.
Rev: 1.00 3/2002
25/36
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary
JTAG Block Diagram
Bypass Register
Instruction Register Code Register
Boundary Scan Register
Test Access Port (TAP) Controller
Identification (ID) Register
Register 32-bit register that loaded with device vendor specific 32-bit code when controller Capture-DR state with IDCODE command loaded Instruction Register. code loaded from 32-bit on-chip ROM. describes various attributes indicated below. register then placed between pins when controller moved into Shift-DR state. register first reach when shifting begins.
Register Contents
Presence Register
Revision Code
Used
Configuration
Technology JEDEC Vendor Code
Controller Instruction
Overview
There classes instructions defined Standard 1149.1-1990; standard (Public) instructions, device specific (Private) instructions. Some Public instructions mandatory 1149.1 compliance. Optional Public instructions must implemented prescribed ways. this device used monitor input pads, used load address, data control signals into preload buffers. When controller placed Capture-IR state least significant bits instruction register loaded with When controller moved Shift-IR state Instruction Register placed between TDO. this state desired instruction serially loaded through input (while previous contents shifted TDO). instructions, executes newly loaded instructions only when controller moved Update-IR state. instruction this device listed following table. Rev: 1.00 3/2002 26/36 2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary
JTAG Controller State Diagram
Test Logic Reset
Test Idle
Select
Select
Capture
Capture
Shift
Shift
Exit1
Exit1
Pause
Pause
Exit2
Exit2
Update
Update
Instruction Descriptions
BYPASS When BYPASS instruction loaded Instruction Register Bypass Register placed between TDO. This occurs when controller moved Shift-DR state. This allows board level scan path shortened facilitate testing other devices scan path.
SAMPLE/PRELOAD SAMPLE/PRELOAD Standard 1149.1 mandatory public instruction. When SAMPLE PRELOAD instruction loaded Instruction Register, moving controller into Capture-DR state loads data RAMs input buffers into Boundary Scan Register. Boundary Scan Register locations associated with input pin, loaded with default state identified Boundary Scan Chain table this section datasheet. Because clock independent from Clock (TCK) possible attempt capture ring contents while input buffers transition (i.e. metastable state). Although allowing sample metastable inputs will harm device, repeatable results cannot expected. input signals must stabilized long enough meet TAPs input data capture set-up plus hold time (tTS plus tTH). RAMs clock inputs need paused other operation except capturing ring contents into Boundary Scan Register. Moving controller ShiftDR state then places boundary scan register between pins. EXTEST Rev: 1.00 3/2002 27/36 2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary
EXTEST IEEE 1149.1 mandatory public instruction. executed whenever instruction register loaded with logic EXTEST command does block override RAM's input pins; therefore, RAM's internal state still determined input pins. Typically, Boundary Scan Register loaded with desired pattern data with SAMPLE/PRELOAD command. Then EXTEST command used output Boundary Scan Register's contents, parallel, RAM's data output drivers falling edge when controller Update-IR state. Alternately, Boundary Scan Register loaded parallel using EXTEST command. When EXTEST instruction selected, sate RAM's input pins, well default values Scan Register locations associated with pin, transferred parallel into Boundary Scan Register rising edge Capture-DR state, RAM's output pins drive value Boundary Scan Register location with which each output associated. IDCODE IDCODE instruction causes loaded into register when controller Capture-DR mode places register between pins Shift-DR mode. IDCODE instruction default instruction loaded power time controller placed Test-Logic-Reset state. SAMPLE-Z SAMPLE-Z instruction loaded instruction register, outputs forced inactive drive state (high-Z) Boundary Scan Register connected between when controller moved Shift-DR state. These instructions Reserved Future Use. this device they replicate BYPASS instruction.
JTAG Instruction Summary
Instruction
EXTEST IDCODE SAMPLE-Z SAMPLE/PRELOAD BYPASS
Code
Description
Places Boundary Scan Register between TDO. Preloads Register places between TDO. Captures ring contents. Places Boundary Scan Register between TDO. Forces output drivers High-Z. this instruction; Reserved Future Use. Replicates BYPASS instruction. Places Bypass Register between TDO. Captures ring contents. Places Boundary Scan Register between TDO. private instruction. this instruction; Reserved Future Use. Replicates BYPASS instruction. Places Bypass Register between TDO. Places Bypass Register between TDO.
Notes
Notes: Instruction codes expressed binary, left, right. Default instruction automatically loaded power-up test-logic-reset state.
Rev: 1.00 3/2002
28/36
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary
JTAG Port Recommended Operating Conditions Characteristics Parameter
Test Port Input High Voltage Test Port Input Voltage Test Port Input High Voltage Test Port Input Voltage TMS, Input Leakage Current TMS, Input Leakage Current Output Leakage Current Test Port Output High Voltage Test Port Output Voltage Test Port Output CMOS High Test Port Output CMOS
Symbol
VIHJ3 VILJ3 VIHJ2 VILJ2 IINHJ IINLJ IOLJ VOHJ VOLJ VOHJC VOLJC
Min.
-0.3 VDD2 -0.3 -300 VDDQ
Max.
VDD3 +0.3 VDD2 +0.3 VDD2
Unit Notes
Notes: Input Under/overshoot voltage must VDDn exceed maximum, with pulse width exceed tTKC. VILJ VDDn VILJn Output Disable, VOUT VDDn output driver served VDDQ supply. IOHJ IOLJ IOHJC -100 IOHJC +100
JTAG Port Test Conditions Parameter
Input high level Input level Input slew rate Input reference level Output reference level
Conditions
V/ns 1.25 1.25
JTAG Port Test Load
1.25
Distributed Test Capacitance
30pF*
Notes: Include scope capacitance. Test conditions shown unless otherwise noted.
Rev: 1.00 3/2002
29/36
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary
JTAG Port Timing Diagram
tTKH tTKL tTKC
tTKQ
JTAG Port Electrical Characteristics
Parameter Cycle Time Valid High Pulse Width Pulse Width Time Hold Time Symbol tTKC tTKQ tTKH tTKL Unit
Rev: 1.00 3/2002
30/36
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary
GS88219/37A Boundary Scan Chain Order GS88219/37A Boundary Scan Chain Order Order
Order
Bump
Bump
2002, Giga Semiconductor, Inc.
ADSP ADSC
31/36
Rev: 1.00 3/2002
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary
GS88219/37A Boundary Scan Chain Order Order
GS88219/37A Boundary Scan Chain Order Order
Bump
Bump
32/36
Rev: 1.00 3/2002
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary
GS88219/37A Boundary Scan Chain Order Order
Bump
Notes: Depending package, some input pads scan chain connected external pin. such case: Every consists scan registers-D input capture, output capture. single register (#121) controlling tristate pins scan chain (i.e., last shifted this tristate control effective after JTAG EXTEST instruction executed. connect, internally logic value connect, internally logic value connect, value undefined
Rev: 1.00 3/2002
33/36
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary Package Dimensions-119-Pin PBGA
Corner
View Bottom View
Package Dimensions-119-Pin PBGA
Symbol Description Width Length Package Height (including ball) Ball Size Ball Height Package Height (excluding balls) Width between Balls Package Height above board Width package between balls Length package between balls Variance Ball Height 0.65 Min. 13.9 21.9 1.73 0.60 0.50 1.16 Nom. 14.0 22.0 1.86 0.75 0.60 1.26 1.27 0.70 7.62 20.32 0.15 0.75 14.1 22.1 1.99 0.90 0.70 1.36
Unit:
Side View
Rev: 1.00 3/2002
34/36
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary Ordering Information Synchronous Burst RAMs
512K 512K 512K 512K 512K 512K 256K 256K 256K 256K 256K 256K 512K 512K 512K 512K 512K 512K 256K 256K 256K 256K 256K 256K
Part Number1
GS88219AB-250 GS88219AB-225 GS88219AB-200 GS88219AB-166 GS88219AB-150 GS88219AB-133 GS88237AB-250 GS88237AB-225 GS88237AB-200 GS88237AB-166 GS88237AB-150 GS88237AB-133 GS88219AB-250I GS88219AB-225I GS88219AB-200I GS88219AB-166I GS88219AB-150I GS88219AB-133I GS88237AB-250I GS88237AB-225I GS88237AB-200I GS88237AB-166I GS88237AB-150I GS88237AB-133I
Type
S/DCD Pipeline S/DCD Pipeline S/DCD Pipeline S/DCD Pipeline S/DCD Pipeline S/DCD Pipeline S/DCD Pipeline S/DCD Pipeline S/DCD Pipeline S/DCD Pipeline S/DCD Pipeline S/DCD Pipeline S/DCD Pipeline S/DCD Pipeline S/DCD Pipeline S/DCD Pipeline S/DCD Pipeline S/DCD Pipeline S/DCD Pipeline S/DCD Pipeline S/DCD Pipeline S/DCD Pipeline S/DCD Pipeline S/DCD Pipeline
Package
Speed2 (MHz)
Status
Notes: Customers requiring delivery Tape Reel should character part number. Example: GS88219AB-150IB. Commercial Temperature Range. Industrial Temperature Range. offers other versions this type device many different configurations with variety different features, only some which covered this data sheet. Technology site (www.gsitechnology.com) complete listing current offerings.
Rev: 1.00 3/2002
35/36
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary
Sync SRAM Datasheet Revision History
DS/DateRev. Code: Old; 88219A_r1 Types Changes Format Content Page;Revisions;Reason Creation datasheet
Rev: 1.00 3/2002
36/36
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.

Base datasheet: GS88219/37AB, Rev.1.00, 3/2002 Product(s) co

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