Base datasheet: GS816019/33/37T, Rev.1.00, 3/2002 Product(s)

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Base datasheet: GS816019/33/37T, Rev.1.00, 3/2002 Product(s)

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GS816019/33/37T
Base datasheet:
GS816019/33/37T, Rev.1.00, 3/2002
Product(s) covered this supplement:
Product specification(s) addressed this supplement:
Note: specifications cited base datasheet products addressed this errata remain force except where superseded information this errata.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
GS816019/33/37T
GS816019 100-Pin TQFP Pinout
VDDQ DQB1 DQB2 VDDQ DQB3 DQB4 VDDQ/DNU DQB5 DQB6 VDDQ DQB7 DQB8 DQB9 VDDQ
View
ADSC ADSP
VDDQ DQA9 DQA8 DQA7 VDDQ DQA6 DQA5 DQA4 DQA3 VDDQ DQA2 DQA1 VDDQ
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
GS816019/33/37T
GS816033 100-Pin TQFP Pinout
DQC8 DQC7 VDDQ DQC6 DQC5 DQC4 DQC3 VDDQ DQC2 DQC1 VDDQ/DNU DQD1 DQD2 VDDQ DQD3 DQD4 DQD5 DQD6 VDDQ DQD7 DQD8
512K View
ADSC ADSP
DQB8 DQB7 VDDQ DQB6 DQB5 DQB4 DQB3 VDDQ DQB2 DQB1 DQA1 DQA2 VDDQ DQA3 DQA4 DQA5 DQA6 VDDQ DQA7 DQA8
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
GS816019/33/37T
GS816037 100-Pin TQFP Pinout
DQC9 DQC8 DQC7 VDDQ DQC6 DQC5 DQC4 DQC3 VDDQ DQC2 DQC1 VDDQ/DNU DQD1 DQD2 VDDQ DQD3 DQD4 DQD5 DQD6 VDDQ DQD7 DQD8 DQD9
512K View
ADSC ADSP
DQB9 DQB8 DQB7 VDDQ DQB6 DQB5 DQB4 DQB3 VDDQ DQB2 DQB1 DQA1 DQA2 VDDQ DQA3 DQA4 DQA5 DQA6 VDDQ DQA7 DQA8 DQA9
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
GS816019/33/37T
TQFP Description Location
100, 5,10,17,
Symbol
A2-A18 DQA1-DQA8 DQB1-DQB8 DQC1-DQC8 DQD1-DQD8 DQA9, DQB9, DQC9, DQD9 DQA1-DQA9 DQB1-DQB9 ADSP, ADSC VDDQ VDDQ/DNU
Type
Description
Address field LSBs Address Counter preset Inputs Address Inputs Address Inputs (x18 versions) Data Input Output pins (x32, Version)
Data Input Output pins (x36 Version) Connect (x32 Version)
Data Input Output pins (x18 Version)
Connect (x18 Version) Byte Write-Writes enabled bytes; active Byte Write Enable DQA, Data I/Os; active Byte Write Enable DQC, Data I/Os; active (x32, Version) Clock Input Signal; active high Global Write Enable-Writes bytes; active Chip Enable; active Chip Enable; active high Output Enable; active Burst address counter advance enable; active Address Strobe (Processor, Cache Controller); active Sleep Mode control; active high Linear Burst Order mode; active Core power supply Core Ground Output driver power supply Connect VDDQ (must tied high) (must left floating)
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary 100-Pin TQFP Commercial Temp Industrial Temp Features
Single Cycle Deselect (SCD) operation +10%/-10% core power supply supply Linear Interleaved Burst mode Internal input resistors mode pins allow floating mode pins Default Interleaved Pipeline mode Byte Write (BW) and/or Global Write (GW) operation Internal self-timed write cycle Automatic power-down portable applications JEDEC-standard 100-lead TQFP package -250 -225 -200 -166 -150 -133 Unit
512K 512K 18Mb Sync Burst SRAMs
Byte Write Global Write
MHz-133
Byte write operation performed using Byte Write enable (BW) input combined with more individual byte write signals (Bx). addition, Global Write (GW) available writing bytes time, regardless Byte Write control inputs.
Sleep Mode
power (Sleep mode) attained through assertion (High) signal, stopping clock (CK). Memory data retained during Sleep mode.
Core Interface Voltages
GS816019/33/37T operates power supply. input compatible. Separate output power (VDDQ) pins used decouple output noise from internal circuits compatible.
Pipeline 3-1-1-1
tCycle Curr (x18) Curr (x32/x36) Curr (x18) Curr (x32/x36)
Functional Description
Applications
GS816019/33/37T 18,874,368-bit (16,777,216-bit version) high performance synchronous SRAM with 2-bit burst address counter. Although type originally developed Level Cache applications supporting high performance CPUs, device finds application synchronous SRAM applications, ranging from main store networking chip support.
Controls
Addresses, data I/Os, chip enables (E1, E3), address burst control inputs (ADSP, ADSC, ADV), write control inputs (Bx, synchronous controlled positive-edge-triggered clock input (CK). Output enable power down control (ZZ) asynchronous inputs. Burst cycles initiated with either ADSP ADSC inputs. Burst mode, subsequent burst addresses generated internally controlled ADV. burst address counter configured count either linear interleave order with Linear Burst Order (LBO) input. Burst function need used. addresses loaded every cycle with degradation chip performance.
Rev: 1.00 3/2002
1/24
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary
GS816019 100-Pin TQFP Pinout
VDDQ DQB1 DQB2 VDDQ DQB3 DQB4 DQB5 DQB6 VDDQ DQB7 DQB8 DQB9 VDDQ
View
ADSC ADSP
VDDQ DQA9 DQA8 DQA7 VDDQ DQA6 DQA5 DQA4 DQA3 VDDQ DQA2 DQA1 VDDQ
Rev: 1.00 3/2002
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
2/24 2002, Giga Semiconductor, Inc.
Preliminary
GS816033 100-Pin TQFP Pinout
DQC8 DQC7 VDDQ DQC6 DQC5 DQC4 DQC3 VDDQ DQC2 DQC1 DQD1 DQD2 VDDQ DQD3 DQD4 DQD5 DQD6 VDDQ DQD7 DQD8
512K View
ADSC ADSP
DQB8 DQB7 VDDQ DQB6 DQB5 DQB4 DQB3 VDDQ DQB2 DQB1 DQA1 DQA2 VDDQ DQA3 DQA4 DQA5 DQA6 VDDQ DQA7 DQA8
Rev: 1.00 3/2002
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
3/24 2002, Giga Semiconductor, Inc.
Preliminary
GS816037 100-Pin TQFP Pinout
DQC9 DQC8 DQC7 VDDQ DQC6 DQC5 DQC4 DQC3 VDDQ DQC2 DQC1 DQD1 DQD2 VDDQ DQD3 DQD4 DQD5 DQD6 VDDQ DQD7 DQD8 DQD9
512K View
ADSC ADSP
DQB9 DQB8 DQB7 VDDQ DQB6 DQB5 DQB4 DQB3 VDDQ DQB2 DQB1 DQA1 DQA2 VDDQ DQA3 DQA4 DQA5 DQA6 VDDQ DQA7 DQA8 DQA9
Rev: 1.00 3/2002
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
4/24 2002, Giga Semiconductor, Inc.
Preliminary
TQFP Description Location
100, 5,10,17,
Symbol
A2-A18 DQA1-DQA8 DQB1-DQB8 DQC1-DQC8 DQD1-DQD8 DQA9, DQB9, DQC9, DQD9 DQA1-DQA9 DQB1-DQB9 ADSP, ADSC VDDQ
Type
Description
Address field LSBs Address Counter preset Inputs Address Inputs Address Inputs (x18 versions) Data Input Output pins (x32, Version)
Data Input Output pins (x36 Version) Connect (x32 Version)
Data Input Output pins (x18 Version)
Connect (x18 Version) Byte Write-Writes enabled bytes; active Byte Write Enable DQA, Data I/Os; active Byte Write Enable DQC, Data I/Os; active (x32, Version) Clock Input Signal; active high Global Write Enable-Writes bytes; active Chip Enable; active Chip Enable; active high Output Enable; active Burst address counter advance enable; active Address Strobe (Processor, Cache Controller); active Sleep Mode control; active high Linear Burst Order mode; active Core power supply Core Ground Output driver power supply Connect
Rev: 1.00 3/2002
5/24
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary
GS816019/33/37 Block Diagram
Register
A0-An
Counter Load
ADSC ADSP
Register
Memory Array
Register
Register
Register
Register
Register
Register
Register
Register
Power Down Control
DQx1-DQx9
Note: Only version shown simplicity.
Rev: 1.00 3/2002
6/24
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary
Mode Functions Mode Name
Burst Order Control Power Down Control
Name
State
Function
Linear Burst Interleaved Burst Active Standby,
Note: Thereis pull-down device pin, this input unconnected chip will operate default states specified above tables.
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0]
address address address address
A[1:0] A[1:0] A[1:0] A[1:0]
address address address address
Note: burst counter wraps initial state clock.
Note: burst counter wraps initial state clock.
1999.05.18
Byte Write Truth Table Function
Read Read Write byte Write byte Write byte Write byte Write bytes Write bytes
Notes
Notes: byte outputs active read cycles regardless state Byte Write Enable inputs. Byte Write Enable inputs and/or used combination with write single multiple bytes. byte I/Os remain High-Z during write operations regardless state Byte Write Enable inputs. Bytes only available versions. Rev: 1.00 3/2002 7/24 2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary
Synchronous Truth Table Operation
Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst
Address Used
None None None External External External Next Next Next Next Current Current Current Current
State Diagram Key5
ADSP ADSC
High-Z High-Z High-Z
Notes: Don't Care, High, (True) (False) (True) (False) defined Byte Write Truth Table preceding. asynchronous input. driven high time disable active output drivers. only enable active drivers (shown Truth Table above). input combinations shown above tested supported. Input combinations shown gray boxes need used accomplish basic synchronous synchronous burst operations avoided simplicity. Tying ADSP high ADSC allows simple non-burst synchronous operations. BOLD items above. Tying ADSP high while using ADSC load addresses allows simple burst operations. ITALIC items above.
Rev: 1.00 3/2002
8/24
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary Simplified State Diagram
Deselect Simple Synchronous Operation
First Write
First Read
Simple Burst Synchronous Operation
Burst Write
Burst Read
Notes: diagram shows only supported (tested) synchronous state transitions. diagram presumes tied low. upper portion diagram assumes active only Enable (E1, Write (BA, control inputs, that ADSP tied high ADSC tied low. upper lower portions diagram together assume active only Enable, Write, ADSC control inputs, assumes ADSP tied high tied low.
Rev: 1.00 3/2002
9/24
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary Simplified State Diagram with
Deselect
First Write
First Read
Burst Write
Burst Read
Notes: diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon "Dummy Reads" (Read Cycles with High) used make transition from Read cycles Write cycles without passing through Deselect cycle. Dummy Read cycles increment address counter just like normal read cycles. Transitions shown gray tone assume been pulsed high long enough turn RAM's drivers incoming data meet Data Input Time.
Rev: 1.00 3/2002
10/24
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary
Absolute Maximum Ratings
(All voltages reference VSS)
Symbol
VDDQ VI/O IOUT TSTG TBIAS
Description
Voltage Pins Voltage VDDQ Pins Voltage Clock Input Voltage Pins Voltage Other Input Pins Input Current Output Current Package Power Dissipation Storage Temperature Temperature Under Bias
Value
-0.5 -0.5 -0.5 -0.5 VDDQ +0.5 max.) -0.5 +0.5 max.) +/-20 +/-20
Unit
Note: Permanent damage device occur Absolute Maximum Ratings exceeded. Operation should restricted Recommended Operating Conditions. Exposure conditions exceeding Absolute Maximum Ratings, extended period time, affect reliability this component.
Rev: 1.00 3/2002
11/24
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary
Power Supply Voltage Ranges Parameter
Supply Voltage Supply Voltage VDDQ Supply Voltage VDDQ Supply Voltage
Symbol
VDD3 VDD2 VDDQ3 VDDQ2
Min.
Typ.
Max.
Unit
Notes
Notes: part numbers Industrial Temperature Range versions character "I". Unless otherwise noted, performance specifications quoted evaluated worst case temperature range marked device. Input Under/overshoot voltage must VDDn+2 exceed maximum, with pulse width exceed tKC.
VDDQ3 Range Logic Levels Parameter
Input High Voltage Input Voltage VDDQ Input High Voltage VDDQ Input Voltage
Symbol
VIHQ VILQ
Min.
-0.3 -0.3
Typ.
Max.
VDDQ
Unit
Notes
Notes: part numbers Industrial Temperature Range versions character "I". Unless otherwise noted, performance specifications quoted evaluated worst case temperature range marked device. Input Under/overshoot voltage must VDDn+2 exceed maximum, with pulse width exceed tKC. VIHQ (max) voltage VDDQ pins plus
VDDQ2 Range Logic Levels Parameter
Input High Voltage Input Voltage VDDQ Input High Voltage VDDQ Input Voltage
Symbol
VIHQ VILQ
Min.
0.6*VDD -0.3 0.6*VDD -0.3
Typ.
Max.
0.3*VDD VDDQ 0.3*VDD
Unit
Notes
Notes: part numbers Industrial Temperature Range versions character "I". Unless otherwise noted, performance specifications quoted evaluated worst case temperature range marked device. Input Under/overshoot voltage must VDDn+2 exceed maximum, with pulse width exceed tKC. VIHQ (max) voltage VDDQ pins plus
Rev: 1.00 3/2002
12/24
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary
Recommended Operating Temperatures Parameter
Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions)
Symbol
Min.
Typ.
Max.
Unit
Notes
Note: part numbers Industrial Temperature Range versions character "I". Unless otherwise noted, performance specifications quoted evaluated worst case temperature range marked device. Input Under/overshoot voltage must VDDn+2 exceed maximum, with pulse width exceed tKC.
Undershoot Measurement Timing
Overshoot Measurement Timing
Capacitance
25oC, MHZ,
Parameter
Input Capacitance Input/Output Capacitance Note: These parameters sample tested.
Symbol
CI/O
Test conditions
VOUT
Typ.
Max.
Unit
Package Thermal Characteristics Rating
Junction Ambient lfm) Junction Ambient lfm)
Layer Board
single four
Symbol
Unit
°C/W °C/W
Notes
Junction Case (TOP) °C/W Notes: Junction temperature function SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature flow, board density, thermal resistance. SCMI G-38-87 Average thermal resistance between surface, SPEC-883, Method 1012.1
Rev: 1.00 3/2002
13/24
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary
Test Conditions Parameter
Input high level Input level Input slew rate Input reference level Output reference level Output load
Conditions
V/ns VDD/2 VDDQ/2 Fig.
Notes: Include scope capacitance. Test conditions specified with output loading shown Fig. unless otherwise noted. Device deselected defined Truth Table.
Output Load VDDQ/2 Distributed Test Capacitance 30pF*
Electrical Characteristics Parameter
Input Leakage Current (except mode pins) Input Current Output Leakage Current Output High Voltage Output High Voltage Output Voltage
Symbol
IIN1 VOH2 VOH3
Test Conditions
Output Disable, VOUT VDDQ 2.375 VDDQ 3.135
Rev: 1.00 3/2002
14/24
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Operating Currents
-250 Mode Symbol 70°C 85°C Unit
-225 70°C 85°C 85°C 85°C 85°C 85°C 70°C 70°C 70°C 70°C
-200
-166
-150
-133
Rev: 1.00 3/2002 (x32/ x36) Pipeline Pipeline Pipeline Pipeline IDDQ Pipeline IDDQ IDDQ (x18) (x32/ x36) (x18) IDDQ Pipeline
Parameter
Test Conditions
Operating Current
Device Selected; other inputs Output open
Operating Current
Device Selected; other inputs Output open
Standby Current
15/24
Deselect Current
Device Deselected; other inputs
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Notes: IDDQ apply combination VDD3, VDD2, VDDQ3, VDDQ2 operation. parameters listed worst case scenario.
Preliminary
2002, Giga Semiconductor, Inc.
Preliminary Electrical Characteristics
Parameter Clock Cycle Time Clock Output Valid Clock Output Invalid Pipeline Clock Output Low-Z Setup time Hold time Output Valid output High-Z Clock HIGH Time Clock Time Clock Output High-Z output Low-Z setup time hold time recovery Symbol tKQX tOHZ1 tHZ1 tOLZ1 tZZS2 tZZH2 tZZR
-250
-225
-200
-166
-150
-133
Unit
Notes: These parameters sampled 100% tested. asynchronous signal. However, order recognized given clock cycle, must meet specified setup hold times specified above.
Rev: 1.00 3/2002
16/24
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary Write Cycle Timing
Single Write
Burst Write
Write
Deselected
ADSP blocked inactive
ADSP
ADSC initiated write
ADSC
must inactive ADSP Write
A0-An
BA-BD
masks ADSP
Deselected with
only sampled with ADSP ADSC
Write specified byte bytes
DQA-DQD
Hi-Z
Rev: 1.00 3/2002
17/24
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary Pipelined Read Cycle Timing
Single Read Burst Read ADSC initiated read ADSP blocked inactive
ADSP ADSC
Suspend Burst
A0-An
BWA-BWD
masks ADSP
only sampled with ADSP ADSC Deselected with
DQA-DQD
Hi-Z tOLZ
tOHZ tKQX
tKQX
Rev: 1.00 3/2002
18/24
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary Pipelined Read-Write Cycle Timing
Single Read Single Write Burst Read
ADSP blocked inactive
ADSP
ADSC initiated read
ADSC
A0-An
BWA-BWD
masks ADSP
only sampled with ADSP ADSC
Deselected with
tOHZ
DQA-DQD
Hi-Z Q2Bb
Rev: 1.00 3/2002
19/24
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary
Sleep Mode
During normal operation, must pulled low, either user internal pull down resistor. When pulled high, SRAM will enter Power Sleep mode after cycles. this time, internal state SRAM preserved. When returns low, SRAM operates normally after recovery time. Sleep mode current, power-down mode which device deselected current reduced ISB2. duration Sleep mode dictated length time High state. After entering Sleep mode, inputs except become disabled outputs High-Z asynchronous, active high input that causes device enter Sleep mode. When driven high, ISB2 guaranteed after time tZZI met. Because asynchronous input, pending operations operations progress properly completed asserted. Therefore, Sleep mode must initiated until valid pending operations completed. Similarly, when exiting Sleep mode during tZZR, only Deselect Read commands applied while SRAM recovering from Sleep mode.
Sleep Mode Timing Diagram
ADSP ADSC
tZZS
tZZH
tZZR
Snooze
Application Tips
Single Dual Cycle Deselect
devices (like this one) force "dummy read cycles" (read cycles that launched normally that ended with output drivers inactive) fully synchronous environment. Dummy read cycles waste performance their usually assures there will contention transitions from reads writes between banks RAMs. SRAMs waste bandwidth dummy cycles logically simpler manage multiple bank application (wait states need inserted bank address boundary crossings) greater care must exercised avoid excessive contention.
Rev: 1.00 3/2002
20/24
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary TQFP Package Drawing
Symbol
Description
Standoff Body Thickness Lead Width Lead Thickness Terminal Dimension Package Body Terminal Dimension Package Body Lead Pitch Foot Length Lead Length Coplanarity Lead Angle
Min. Nom.
0.05 1.35 0.20 0.09 21.9 19.9 15.9 13.9 0.45 0.10 1.40 0.30 22.0 20.0 16.0 14.0 0.65 0.60 1.00 0.15 1.45 0.40 0.20 22.1 20.1 16.1 14.1 0.75 0.10
Notes: dimensions millimeters (mm). Package width length include mold protrusion.
Rev: 1.00 3/2002
21/24
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary Ordering Information Synchronous Burst RAMs
512K 512K 512K 512K 512K 512K 512K 512K 512K 512K 512K 512K 512K 512K 512K 512K 512K 512K 512K
Part Number1
GS816019T-250 GS816019T-225 GS816019T-200 GS816019T-166 GS816019T-150 GS816019T-133 GS816033T-250 GS816033T-225 GS816033T-200 GS816033T-166 GS816033T-150 GS816033T-133 GS816037T-250 GS816037T-225 GS816037T-200 GS816037T-166 GS816037T-150 GS816037T-133 GS816019T-250I GS816019T-225I GS816019T-200I GS816019T-166I GS816019T-150I GS816019T-133I GS816033T-250I GS816033T-225I GS816033T-200I GS816033T-166I GS816033T-150I GS816033T-133I GS816037T-250I
Type
Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline
Package
TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP TQFP
Speed (MHz/ns)
Status
Notes: Customers requiring delivery Tape Reel should character part number. Example: GS816019T-150IT. Commercial Temperature Range. Industrial Temperature Range. offers other versions this type device many different configurations with variety different features, only some which covered this data sheet. Technology site (www.gsitechnology.com) complete listing current offerings. Rev: 1.00 3/2002 22/24 2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary
512K 512K 512K 512K 512K
Part Number1
GS816037T-225I GS816037T-200I GS816037T-166I GS816037T-150I GS816037T-133I
Type
Pipeline Pipeline Pipeline Pipeline Pipeline
Package
TQFP TQFP TQFP TQFP TQFP
Speed (MHz/ns)
Status
Notes: Customers requiring delivery Tape Reel should character part number. Example: GS816019T-150IT. Commercial Temperature Range. Industrial Temperature Range. offers other versions this type device many different configurations with variety different features, only some which covered this data sheet. Technology site (www.gsitechnology.com) complete listing current offerings.
Rev: 1.00 3/2002
23/24
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.
Preliminary
18Mb Sync SRAM Datasheet Revision History DS/DateRev. Code: Old;
816019_r1
Types Changes Format Content
Page;Revisions;Reason
Creation datasheet
Rev: 1.00 3/2002
24/24
2002, Giga Semiconductor, Inc.
Specifications cited subject change without notice. latest documentation http://www.gsitechnology.com.

Base datasheet: GS816019/33/37T, Rev.1.00, 3/2002 Product(s)

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