128K Embedded DRAM Macro Logical organization: 128Kx32 bits Physi
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GLT44032-E
128K Embedded DRAM Macro
Logical organization: 128Kx32 bits Physical organization: 512x256x32 Single 3.3v 0.3v power supply 512-cycle refresh Refresh modes: only, CBR, Hidden Single with Byte Write control Non-multiplex column addresses Separate operation 80/100 page mode cycle
GENERAL DESCRIPTION
GLT44032-E 4Mbit Embedded DRAM (EmDRAM) asynchronous design with non-multiplexed column addressing scheme. RAS, CAS, control memory operations. Byte Write operation controlled DQM[0], DQM[1], DQM[2], DQM[3]. DQM[0] going will mask DI[0:7] from writing into memory; DQM[1] going will mask DI[8:15] from writing into memory; DQM[2] going will mask DI[16:23] from writing into memory; DQM[3] going will mask DI[24:31] from writing into memory. output drivers, DO[0:31], will Threestated during Write operation.
Performance Data
Parameter Max. access time, tRAC Max. precharge time, Max. column address access time, Max. access time, tCAC Min. extended data page mode cycle time, Min. read/write cycle time, 12.5
1997 (Rev.
GLT44032-E
FUNCTIONAL BLOCK DIAGRAM
Clock Generator
Clock Generator
Clock Generator Column Address Buffers AY[7:0] Column Decoders Sense Amplifiers Refresh Counter Controller AX[8:0] Decoders
Data Control
CA[7:0]
DO[31:0] Data DI[31:0]
RA[8:0]
Address Buffers Clock Generator
Memory Array
Figure GLT44032-E 128K Descriptions
Symbol DI[31:0] DO[31:0] RA[8:0] CA[7:0] DQM[3:0] Type Input Output Input Input Input Input Input Input Supply Supply Data input. Data output. address. Column address. address strobe. Column address strobe. Write enable. Output enable. Data-in mask (active low) 3.3v voltage supply, pairs double bond minimum Ground (voltage return), pairs double bond minimum Description
EmDRAM should separated from Logic portion chip.
G-LINK Technology
1997 (Rev.
GLT44032-E
Truth Table
Function Standby Read Write (Early) Write DI[7:0] Write [15:8] Write [23:16] Write [31:24] Read-Write Page-Mode Read (First Cycle) Page-Mode Read (Subsequent Cycles) Page-Mode Write (First Cycle) Page-Mode Write (Subsequent Cycle) Page-Mode (First Cycle) Page-Mode (Subsequent Cycle) Refresh RAS-only Refresh Address Row/Col Row/Col Row/Col Row/Col Row/Col Row/Col Row/Col Row/Col Row/Col Row/Col DQM0 DQM1 DQM2 DQM3 DI[31:0] Data Data Data Data Data Data Data Data Data Data DO[31:0] High-Z Data High-Z High-Z High-Z High-Z High-Z Data Data Data High-Z High-Z Data Data High-Z High-Z
G-LINK Technology
1997 (Rev.
GLT44032-E
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter Ambient Operating Temperature Storage Temperature Voltage Relative Power Dissipation
Operation above Absolute Maximum ratings adversely affect device reliability.
Rating +125 -0.5 0.8W
Recommended Operating Conditions
Symbol Power Supply Input High Voltage Input Voltage Parameter -0.5 Unit
Capacitance
Symbol Input Capacitance Input/Output Capacitance Description Units
Notes
Capacitance sampled 100% tested
Characteristics (VCC 3.3V 10%,
Symbol ICC1 ICC2 ICC3 ICC4 ICC4 Description Input High (Logic Voltage Input (Logic Voltage Output High Voltage Output Voltage Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS-only Refresh) Average Power Supply Current (Fast Page Mode) Average Power Supply Current (CAS-before-RAS Refresh) -2.0 RAS, cycling; Min. RAS, cycling; VIH; Min. VIL; cycling; Min. cycling; before Conditions -0.5 -0.5 Units
G-LINK Technology
1997 (Rev.
GLT44032-E
Characteristics (VCC
Symbol tOFF tDOH tRAC tCAC tCPA tRAS tRCD tCAS tASR tRAH tASC tCAH tCSH tCRP tRSH tRCS tRCH tRRH tWCS tWCH tRWL tCWL tDMS tDMH tODW Description Random Read/Write cycle time Page Mode Read/Write cycle Read Data valid from high Read Data valid from next Access time from Column Address Access time from Access time from Access time from precharge pulse width delay time pulse width Address setup time Address hold time Column Address setup time Column Address hold time precharge time hold time from Write Data setup time Write Data hold time precharge time precharge time high hold time Read command setup time Read command hold time from high Read command hold time from high Write command setup time Write command hold time pulse width Transition time (rise fall) Write command high Write command high mask write setup time mask write hold time from control output disable 12.5 Units
Notes
better performance margin, switch column addresses data-in rising edge CAS. Switch falling edge CAS. Set-up time going active (low) hold-time from going non-active (high) going will mask write.
G-LINK Technology
1997 (Rev.
GLT44032-E
tRAS
tCRP
tRCD
tCAS
tASR ADDR
tRAH
tASC Column
tCAH
tWRP tCAC tRAC DOUT Hi-Z
tRCH
Valid Data
Don't Care
Figure Read Cycle
tRASP tCSH tRCD tCAS tRSH
tASC ADDR Column Column tCPA
tCAH Column
tWRP tCAC tRAC DOUT Hi-Z
tRCH
tCAC tDOH Valid Data
tOFF tOFF
(note (note
Don't Care
Figure Page Mode Read Cycle
G-LINK Technology
1997 (Rev.
GLT44032-E
tRAS tRWL tCRP tRCD tCAS
tASR ADDR
tRAH
tASC Column
tCAH
tCWL
tWRP tCAC tRAC DOUT Hi-Z DOUT
tODW
tDMS
tDMH
Don't Care
Figure Read/Write Cycle
tRASP tCAS tRWL
tASR ADDR
tRAH
tASC Column
tCAH
tCWL
tASC Column
tCAH
tCWL
tCAC tWRP tCAC tRAC DOUT Hi-Z DOUT tODW DOUT tCPA tODW
tDMS
tDMH
tDMS
tDMH
Don't Care
Figure Page Mode Read/Write Cycle
G-LINK Technology
1997 (Rev.
GLT44032-E
tRAS
tRCD tRWL tCWL ADDR Column tWCS
tCAS
tWCH
tDMS
tDMH
Valid Data
Don't Care
Figure Early Write Cycle
tRASP tCSH tRCD tCAS tRSH tWCH
tASC ADDR Column Column
tCAH Column
tWCS
tDMS
tDHS
tDMS
tDHS
tDMS
tDMH
Valid Data
Valid Data Valid Data
Don't Care
Figure Page Mode Early Write Cycle
G-LINK Technology
1997 (Rev.
GLT44032-E
G-LINK Technology
1997 (Rev.
GLT44032-E
G-LINK Technology
1997 (Rev.
GLT44032-E
G-LINK Technology
1997 (Rev.
GLT44032-E
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