April 1988 Revised August 1999 8-Bit Registered Transceiver

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April 1988 Revised August 1999 8-Bit Registered Transceiver

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8-Bit Registered Transceiver
April 1988 Revised August 1999
8-Bit Registered Transceiver
29F52 29F53 8-bit registered transceivers. 8-bit back back registers store data flowing both directions between bidirectional buses. Separate clock, clock enable 3-STATE output enable signals provided each register. A0-A7 output pins guaranteed sink while B0-B7 output pins designed 29F53 inverting option 29F52. Both transceivers Am2952/2953 functional equivalents.
Features
8-bit registered transceivers Separate clock, clock enable 3-STATE output enable provided each register Am2952/2953 functional equivalents Both inverting non-inverting options available 24-Pin slimline package
Ordering Code:
Order Number 29F52SC 29F52SPC 29F53SPC Package Number M24B N24C N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Devices also available Tape Reel. Specify appending suffix letter ordering code.
Logic Symbols
29F52 29F53
IEEE/IEC 29F52
IEEE/IEC 29F53
1999 Fairchild Semiconductor Corporation
DS009606
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Connection Diagrams
Assignment SOIC 29F52 Assignment 29F53
Unit Loading/Fan
Names A0-A7 B0-B7 Description A-Register Inputs/ B-Register 3-STATE Outputs Register Inputs/ A-Register 3-STATE Outputs Output Enable A-Register A-Register Clock A-Register Clock Enable Output Enable B-Register B-Register Clock B-Register Clock Enable U.L. HIGH/LOW 3.5/1.083 150/40 (33.3) 3.5/1.083 600/106.6 (80) 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 Input IIH/IIL Output IOH/IOL µA/0.65 mA/24 µA/0.65 mA/64 µA/-0.6 µA/-0.6 µA/-0.6 µA/-0.6 µA/-0.6 µA/-0.6
Output Control
Internal Y-Output 29F52 29F53 Function
Register Function Table (Applies Register)
Inputs Disable Outputs Enable Outputs Internal Function Hold Data Load Data
HIGH Voltage Level Voltage Level Immaterial HIGH Impedance LOW-to-HIGH Transition Change
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Block Diagrams
29F52
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Block Diagrams (continued) 29F53
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Absolute Maximum Ratings(Note
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Potential Ground Input Voltage (Note Input Current (Note Voltage Applied Output HIGH State (with Standard Output 3-STATE Output Current Applied Output State (Max) twice rated (mA) -0.5V -0.5V +5.5V -65°C +150°C -55°C +125°C -55°C +150°C -0.5V +7.0V -0.5V +7.0V +5.0
Recommended Operating Conditions
Free Ambient Temperature Supply Voltage +70°C +4.5V +5.5V
Note Absolute maximum ratings values beyond which device damaged have useful life impaired. Functional operation under these conditions implied. Note Either voltage limit current limit sufficient protect inputs.
Electrical Characteristics
Symbol Parameter Input HIGH Voltage Input Voltage Input Clamp Diode Voltage Output HIGH Voltage IBVI IBVIT IOZH IOZL ICEX ICCH ICCL ICCZ Output Voltage Input HIGH Current Input HIGH Current Breakdown Test Input HIGH Current Breakdown Test (I/O) Input Current Output Leakage Current Output Leakage Current Output Short-Circuit Current Output HIGH Leakage Current Drainage Test Power Supply Current Power Supply Current Power Supply Current -100 0.55 -0.6 -650 -150 -225 0.0V -1.2 Units Conditions Recognized HIGH Signal Recognized Signal (Non Pins) (An) (An, (Bn) (An) (An, 2.7V (Non-I/O Pins) 7.0V (Non-I/O Pins) 5.5V (An, 0.5V (Non-I/O Pins) VOUT 2.7V (An, VOUT 0.5V (An, VOUT (An) VOUT (Bn) VOUT (An, VOUT 5.25V (An, HIGH HIGH
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Electrical Characteristics
+25°C Symbol Parameter tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay Output Enable Time Output Disable Time +5.0V -55°C +125°C +5.0V +70°C +5.0V 10.0 10.5 10.0 Units
Operating Requirements
+25°C Symbol Parameter +5.0V tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) Setup Time, HIGH Hold Time, HIGH Setup Time, HIGH Hold Time, HIGH Pulse Width, HIGH -55°C +125°C +5.0V +70°C +5.0V Units
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Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B
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8-Bit Registered Transceiver
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Package Number N24C
Fairchild does assume responsibility circuitry described, circuit patent licenses implied Fairchild reserves right time without notice change said circuitry specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT FAIRCHILD SEMICONDUCTOR CORPORATION. used herein: Life support devices systems devices systems which, intended surgical implant into body, support sustain life, whose failure perform when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. www.fairchildsemi.com critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness. www.fairchildsemi.com

April 1988 Revised August 1999 8-Bit Registered Transceiver

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