32-Bit RISC Processor, supported RTOS, C/C++ compilers 32-bit cap

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CS98100 Processor Cost Players
32-Bit RISC Processor, supported RTOS, C/C++
compilers 32-bit capable AC-3, MPEG, DTS, MP3, Progressive Scan (480p) with pull down support Interlaced (PAL/NTSC) video encoding, both modes with Macrovision encoding, three 10-bit Video DACs Serial data interface direct connection cost (track buffer-less) loader Flexible interface connects ATAPI, local microcontroller-less loaders without external logic MPEG decoder supports VCD, 3.0, SVCD, video standards Advanced subpicture unit handles SVCD, PAL<->NTSC scaling High quality video scaling zoom NTSC/PAL conversion 4-bit multi-region special video effects Simultaneous channels audio output IEC-958. 2-Channel audio input high-end karaoke applications Three serial control/status ports Low-power, ~0.5 power dissipation
Description
Building innovative, market-leading technology, Cirrus Logic presents most complete processor solution available: CS98100. CS98100 provides highperformance typical Cirrus Logic integrated circuits, on-chip integration that allows seamless integration functions. Among integrated functions this system-on-chip architecture high quality NTSC/PAL encoder with triple 10-bit video DAC, allowing significant decrease system cost. only CS98100 equipped with intuitive onscreen display user interface, CS98100 also offers progressive output, decoding, HDCD support, plus decoding. Other advanced features include karaoke down-mix. cost extended feature makes CS98100 ideal both low-end high-end system manufacturers. ORDERING INFORMATION CS98100-CM 208-pin MQFP
Preliminary Product Information
P.O. 17847, Austin, Texas 78760 (512) 7222 FAX: (512) 7581 http://www.cirrus.com
This document contains information product. Cirrus Logic reserves right modify this product without notice.
Copyright Cirrus Logic, Inc. 2002 (All Rights Reserved)
DS552PP4
CS98100
TABLE CONTENTS
CHARACTERISTICS SPECIFICATIONS Parametric Specifications 1.1.1 Absolute Maximum Rating 1.1.2 Recommended Operating Conditions 1.1.3 Electrical Characteristics Characteristics 1.2.1 ATAPI Interface 1.2.2 SDRAM Interface 1.2.3 Serial Interface Timing 1.2.4 Digital Video Interface Timing 1.2.5 Digital Audio Interface Timing 1.2.6 ROM/NVRAM Interface 1.2.7 Miscellaneous Timings TYPICAL APPLICATION CS98100 Device Summary FUNCTIONAL DESCRIPTION RISC Processor Processor Memory Control Dataflow Control (DMA) System Control Functions DVD/ATAPI Interface Serial Interface MPEG Video Decoding Audio Processing 3.10 Video Processing 3.11 Video Encoder MEMORY REGISTERS Processor Memory
Contacting Cirrus Logic Support
complete listing Direct Sales, Distributor, Sales Representative contacts, visit Cirrus Logic site
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CS98100
Host Port Memory Internal Space CS98100 Register Space DESCRIPTIONS ASSIGNMENTS Miscellaneous Pins Serial Interface SDRAM Interface ROM/NVRAM Interface Digital Video Output Interface Audio Output/Input Interface Host Master/ATAPI Interface Channel Interface Serial Data Interface 6.10 Video Encoder Interface 6.11 General Purpose Input/Output (GPIO) 6.12 Power Ground MQFP PACKAGE SPECIFICATIONS
LIST FIGURES
Figure ATAPI Interface Timing Diagram Figure SDRAM Refresh Transaction. Figure SDRAM Burst Read Transaction Figure SDRAM Burst Write Transaction Figure CS98100 SDRAM Read Write Figure CS98100 Serial Interface Timing Diagram. Figure CS98100 Digital Video Interface Timing Diagram Figure Digital Audio Timing Diagram Figure Digital Audio Timing Diagram. Figure ROM/NVRAM Reading Timing Figure ROM/NVRAM Write Timing Figure Miscellaneous Timings. Figure CS98100 Application Figure CS98100 Layout Figure CS98100 208-Pin MQFP Package Drawing
LIST TABLES
Table ATAPI Interface Characteristics Table SDRAM Interface Characteristics Table CS98100 Interface Characteristics. Table CS98100 Digital Video Interface Characteristics Table Digital Audio Characteristics Table Digital Audio Characteristics Table RAM/NVROM Characteristics Table Miscellaneous Timing Characteristics. Table Memory RISC Processor Table Host Port Memory Table Internal Space Table CS98100 Register Blocks Table CS98100 Registers
CS98100
Table Type Direction Legend Table Assignments. Table Miscellaneous Interface Pins. Table Serial Interface Assignments Table SDRAM Interface Assignments. Table ROM/NVRAM Interface Assignments Table Video Output Interface Assignments. Table Audio Output Interface Assignments. Table Host Master Interface Assignments Table Channel Interface Assignments. Table Serial Data Interface Assignments Table Video Encoder Interface Assignments Table General Purpose Interface Assignments. Table Power Ground
CS98100
CHARACTERISTICS SPECIFICATIONS
PARAMETRIC SPECIFICATIONS (AGND, DGND=0V, voltages with respect
1.1.1 ABSOLUTE MAXIMUM RATING
Symbol VDDIO VDDCORE TSOL TVSOL TSTOR TAMB Ptotal Description Power Supply Voltage ring Power Supply Voltage core logic Digital Input Applied Voltage (power applied) Digital Input Forced Current Digital Output Forced Current Lead Soldering Temperature Vapor Phase Soldering Temperature Storage Temperature power applied) Ambient Temperature (power applied) Total Power consumption -0.5 -0.5 -0.5 Unit Volts Volts Volts
CAUTION: Operating beyond these Minimum Maximum limits result permanent damage device. Cirrus Logic recommends that CS98000 devices operate settings described next table.
1.1.2
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol TAMB 1.62 1.98 Units Volts Volts
Supply Voltage, Supply Voltage, core Ambient Temperature (power applied)
1.1.3
ELECTRICAL CHARACTERISTICS
Parameter Power Supply Supply Voltage, Supply Voltage, core Supply Current, Supply Current, core Digital Pins Input Voltage, High Input Voltage, Symbol Normal Operating Normal Operating Conditions 1.62 1.98 Units Volts Volts Volts Volts
CS98100
Parameter Input Current Input Pull up/down resistor Output Voltage, High Output Voltage, High-Z-state Leakage Analog Video Pins Full Scale Current Output Voltage Range matching1 Output Voltage Range Differential Gain Differential Phase Signal Noise Chrominance Noise Chrominance Noise 1.Only applies each three. Symbol Vout 37.5 buffer rating buffer rating VOUT 37.5 37.5 1.28 1.28 Conditions Units Volts Volts Volts Volts
CS98100
CHARACTERISTICS (TA= 25°C; VDD_PLL=VDD_CORE=1.8 V±10%, VDD_IO=3.3 V±10%)
1.2.1 ATAPI Interface
CS98100 interface with ATAPI-type slave loader gluelessly. Figure illustrates read ATAPI transaction write ATAPI transaction. mode implemented sufficient data transfer rate between ATAPI device CS98100. Table ATAPI symbols characterization data.
Symbol
Description Cycle Time Address Valid HMRD-/HMWR- Setup
Unit
acyc1
aavr
Address Hold from HMRD-/HMWR Setup H_RD/H_WR Pulse Width H_RD/H_WR Recovery Time H_WR Data Setup H_WR Data Hold H_RD Data Setup H_RD Data hold H_RD Data three-state H_RDY Setup Time H_RDY Hold Time
tarww
arec
tawsu tawh tardsu
arddh
ardts
tarsu tarh1
Table ATAPI Interface Characteristics 1.Values guaranteed design only
H_A[2:0] H_CS[3:0] aavr H_RD/H_WR arww
acyc
tarec
H_D[15:0](WRITE) awsu H_D[15:0](READ) tarsu H_RDY(deasserted before tarsu) H_RDY(asserted before tarsu) tardsu arddh ardts tawh
Figure ATAPI Interface Timing Diagram
CS98100
1.2.2 SDRAM Interface
CS98100 interfaces with either SDRAM SGRAM, high data bandwidth transfer. Figure Table show interface timing. Figure shows refresh cycle performed CS98100. Figure shows burst read (length transaction, while Figure shows burst write (length=8) transaction. both Figure Figure latency programmed
Symbol
Description Output Delay from DR_CKO active edge DR_CKO Period DR_D[31:0] delay from DR_CKO DR_D[31:0] valid time after DR_CKO DR_D[31:0] setup DR_CKO
12.2
Unit
mper
mdow
msur1
msurd1 mhr1
DR_D[31:0] setup DR_CKO with delay DR_D[31:0] hold time after DR_CKO 1.85
tmhrd1
DR_D[31:0] hold time after DR_CKO with delay Table SDRAM Interface Characteristics
1.Delay programmable selecting DRAM_Input_Speed Command Register(0x000)
DR_CKO DR_A[11:0] DR_BS_N DR_RAS_N DR_CAS_N DR_WE_N DR_D[31:0] DR_DQM_[3:0] DR_AP
Figure SDRAM Refresh Transaction
CS98100
DR_CKO DR_A_[11:0] DR_CKE DR_RAS_N DR_CAS_N DR_WE_N DR_D[31:0] DR_DQM[3:0]
Figure SDRAM Burst Read Transaction
DR_CKO DR_A_[11:0] DR_CKE DR_RAS_N DR_CAS_N DR_WE_N DR_D[31:0] DR_DQM[3:0]
Figure SDRAM Burst Write Transaction
CS98100
tmco DR_CKO DR_RAS_N,DR_CAS_N DR_WE_N,DR_AP,DR_DQM[3:0], DR_CKE,DR_A[11:0] DR_D[31:0](WRITE)
tmper
tmdow
tmhw
DR_D[31:0](READ) tmsur tmhr
Figure CS98100 SDRAM Read Write
CS98100
1.2.3 Serial Interface Timing
Figure Table illustrate signal timing serial interface input pins.
Symbol
Description DVDS_CLK Period DVDS_CLK Time DVDS_CLK High Time
Unit
dsckper1
dsckl1
dsckh1
dsdsu
DVDS_DATA Setup DVDS_CLK active edge DVDS_DATA Hold after DVDS_CLK active edge DVDS_VLD,DVDS_SOS Setup DVDS_CLK
dsdhd
dscdsu
dscdhd
DVDS_VLD,DVDS_SOS Hold after DVDS_CLK Table CS98100 Interface Characteristics
1.Values guaranteed design only
dsckper
DVDS_CLK (Input)
tdsckl
dsckh dsdsu dsdhd
DVDS_DATA (Input)
dscdsu
DVDS_VLD, DVDS_SOS (Input)
dscdhd
Figure CS98100 Serial Interface Timing Diagram
CS98100
1.2.4 Digital Video Interface Timing
Figure illustrates signal timing digital video interface pins. clock without polarity show clock inverted register programming. This also illustrates that data clocked both clock edges progressive mode. data order Cr,Y0,Cb,Y1, sync outputs programmed active high active low.
Symbol
Description CLK27_O period VDAT[7:0] delay from CLK27_O Vsync/Hsync delay from CLK27_O
37.037
Unit
vocper
covo12
covo22
Table CS98100 Digital Video Interface Characteristics 1.Values guaranteed design only 2.It recommanded that output data should taken opposite edge CLK27_O.
Tvocper
CLK27_O (Output)
Tcovo1 VDAT[7:0] (Output) Tcovo2
VSYNC/HSYNC (Output)
Figure CS98100 Digital Video Interface Timing Diagram
CS98100
1.2.5 Digital Audio Interface Timing
Figure Figure illustrate signal timing digital audio pins. bi-directional AUD_XCK clocks frequency AUD_BCK pin. AUD_BCK outputs sample frequency, transitions falling edge AUD_XCK pin. AUD_BCK shown without polarity indicate polarity programmable.
Symbol
Description AIN_LRCK setup AUD_BCK active edge AIN_DATA setup AUD_BCK active edge
Unit
slri
thsdi
AIN_DATA hold time after AUD_BCK active edge Table Digital Audio Characteristics
*AUD_BCK (Output) lrts AIN_LRCK (Input) sdsus sdhs AIN_DATA (Input) Active clock edge programmable. Timing referenced from active edge.
Figure Digital Audio Timing Diagram
CS98100
Symbol
Description
Unit
axch
AUD_XCLK High Time (AUD_XCLK Input/Output) AUD_XCLK Time (AUD_XCLK Input/Output) AUD_XCLK period (Input/Output) AUD_BCK delay from AUD_XCLK(output) active edge AUD_BCK delay from AUD_XCLK(input) active edge AUD_BCK period AUD_LRCK delay from AUD_BCK active edge AUD_D[3:0] delay from AUD_BCK active edge
taxcl1
axper odbck odbck aoper odlr2 odsd2
Table Digital Audio Characteristics 1.Values guaranteed design only 2.It recommanded that output data should taken opposite edge AUD_BCK.
AUD_XCLK(Input/Output) AUD_BCK(Output)
axcl
axper
axch
odbck
aoper
AUD_BCK(Output)
AUD_LRCK(Output) odsd AUD_DO[3:0] (Output)
odlr
Active clock edge programmable. Timing referenced from active edge.
Figure Digital Audio Timing Diagram
CS98100
1.2.6
ROM/NVRAM Interface Symbol Read Cycle Time Data Setup Data Setup Address Data Setup Address setup (Write) setup (Write) Pulse Width (Write) Data Output (Write) Data Hold (Write) Description Unit
Table RAM/NVROM Characteristics Note:Read timing based 10.5 memory clock programmed wait states.
Address M_A[11:0], M_D[27:16] NVM_CE_N NVM_OE_N (M_AP) M_D[7:0] NVM_WE_N
Figure ROM/NVRAM Reading Timing
CS98100
Address M_A[11:0], M_D[27:16] NVM_CE_N NVM_WE_N twdo M_D[7:0] NVM_OE_N (M_AP)
Figure ROM/NVRAM Write Timing
CS98100
1.2.7 Miscellaneous Timings
Symbol txclper trstl tgph tgpl
Description XTLCLK period RST_N Pulse Width GPIO High GPIO
1000
37.037
Unit
Table Miscellaneous Timing Characteristics 1.XTLCLK must meet requirement external video encoder correct chroma KHz).
xccper
XTLCLOCK rstl RESET-N tgph tgpl
GPIO
Figure Miscellaneous Timings
CS98100
TYPICAL APPLICATION
Figure shows example complete high-end solution using CS98100.
Front Panel
XTAL (4)Audio DACs
Audio
Audio
AudioUp Channels S/PDIF Composite Video S-Video
CS98100
Loader Channel, ATPAI Serial)
ROM/ FLASH -1MB
SDRAM 4-8MB Power Reg.
Component Video Switch Power
Figure CS98100 Application
CS98100 Device Summary
RISC-32
Powerful 32-bit RISC processor Optimizing compiler source level debugger little endian data formats supported multiply/accumulate cycles with support. Kbyte instruction cache, Kbyte data cache. Single cycle instructions MHz.
DSP-32
Powerful 24/32-bit processor 24-bit fixed point logic, with 54-bit accumulator. Single-cycle throughput, 2-cycle latency multiply accumulate, 32-bit simple integer logic. Kbyte instruction cache, Kbyte program visible local memory Single cycle instructions MHz.
SYSTEM CONTROLS
communication 32-bit timers other uses, with programmable interval rates Both hardware software interrupts data debug Performance monitors which measures DRAM bandwidth, usage, performance Built PLLs generate required clocks from input clock. Memory Controller Supports SDRAM, SGRAM, from MBytes MBytes. Supports multiple banks FLASH MBytes. 32-bit data DRAM, 16-bit data ROM.
DATA FLOW ENGINE
Include several hardware lockable semaphore registers General-purpose registers inter-processor
controllers local memory based direct memory-to-memory 2432 bytes internal memory, to/from main into local SRAM. Supports endian conversion byte, short,
CS98100
long data formats DMA. Supports block transfers graphics blits.
MPEG VIDEO DECODER
Supports VCD1.0, 1.1, 3.0, SVCD, video standards. Supports trick features, including smooth forward play. Special anti-tearing logic controls picture decode presentation. Advanced error concealment hardware.
SYSTEM SYNCHRONIZATION
channel interface supports standard loader protocols Separate serial interface support lowcost (track buffer-less) loaders
VIDEO PROCESSOR
System time clock (STC) audio/video synchronization Flexible interrupt structure controlling decode presentation times Hardware scheduling sub-picture highlight events
AUDIO INTERFACE
screen display module supports 2-bit 4bit, pixel modes. supports separate regions transparency overlay levels High quality scaling using polyphase programmable vertical horizontal filters, support size image 768x576. Multiple video plain overlays (main video subpicture picture-in-picture on-screen display). Gamma Correction. Progressive scan video output
VIDEO ENCODER
Supports channels PCM, bits output rate. Simultaneous IEC-958 output with programmable channel status user data Also supports S/PDIF receiver high performance applications
EXTERNAL INTERFACE
2-wire serial master slave port, second 2wire master port controlling device. 4-wire serial master/slave port. Large number programmable bi-directional pins. pins used other function reassigned general purpose pins pins used edge level detection interrupt pins. Hardware-assisted support infrared remote devices, such remote control, infrared keyboard, mouse, printer, more. Programmable parallel host master interface supports formats including ATAPI, ISA, more.
Three 10-bit video DACs, drive 37.5 load directly without external buffering Supports (B,D,G,H,I,N) NTSC Component (RBG YUV) composite SVideo output Progressive interlaced mode output Macrovision support (interlaced) Macrovision 1.03 support (progressive) Wide-screen signaling support (interlaced progressive) CGMS support Closed captioning support
SUB-PICTURE PROCESSOR
Run-length decode sub-pictures SVCD formats Hardware vertical scaling supports NTSC-PAL format conversion level alpha blending System Functions 208-pin MQFP package. pins with tolerance. Advanced 0.18 micron CMOS technology. Chip runs Supports power modes clock shutoff.
CS98100
FUNCTIONAL DESCRIPTION
RISC Processor CS98100 includes powerful, proprietary 32bit RISC processor with optimizing compiler support. RISC engine which performs multiply/accumulate cycles pipelined fashion with support, effectively achieving single cycle throughout. CS98100 fully supports many Real Time Operating Systems (RTOS). RISC processor co-ordinates on-chip multithreaded tasks, well supervises system activities such remote control front panel control. Processor CS98100 contains proprietary digital signal processor (DSP) which optimized audio applications. performs 32-bit simple integer operations, 24-bit fixed point logic unit, with 54-bit accumulator. There generalpurpose registers, eight independent address generation registers, featuring: post-increment ALU, linear circular buffer operations, reverse operations, dual operand read from memory. multiply-accumulator single-cycle throughput, with cycle latency. optimized packing unpacking operations. interface main memory designed bursting flexible block sizes skip counts. Memory Control DRAM Interface performs SDRAM control arbitration functions other modules CS98100. DRAM interface services arbitrates number clients stores their code and/or data within local memory. This arbitration scheduling guarantees allocation sufficient bandwidth various clients. DRAM Interface supports MByte. typical player application, CS98100 requires MByte SDRAM MByte FLASH. Sharing same interface, CS98100 also supports flash ROM, OTP, masked interface. Code stored ROM. After system booted, code shadowed inside DRAM execution. FLASH interface provided that code upgraded field once communication channel established via, example, CD-R serial port. Utility software will provided debug upgrade code system manufacturer. Dataflow Control (DMA) controller moves data between external memory internal memory. external memory address specified using register, FIFO mode, using start address registers. Separate start/end address registers used read write operations. interface also block transfer function, which allows transfer block data from external memory location another external memory location. effect, combining read write into operation. addition, write operation allows byte, short, word, other types masking. second dedicated controller provides fast memory-to-memory transfers. System Control Functions system control functions used coordinate activities multiple processors, provide supporting system operations. Four 32-bit communication registers available inter-processor communication, eight semaphore registers used resource locking. Timers available general-purpose functions, well more specialized functions such watchdog timers performance monitoring. large number general purpose I/Os offers flexibility system configurations. Three separate serial interfaces, conforming industry-standard protocols, available vari-
CS98100
system interface functions. Interrupts generated specific generic events. Infrared inputs filtered glitches stored unfiltered into memory. Power-down control internal clocks also possible. Internal PLLs used generate internal system memory clocks, audio clocks widely used frequency. DVD/ATAPI Interface CS98100 programmable interface port, which configured connect industry standard CD/DVD loaders without external glue logic. CD/DVD interface fully supports wide range popular CD/DVD loaders. interface consists control data ports, optional control/data port. CS98100 hardware manages interface moving data arbitrary size input FIFO DRAM. same interface pins optionally configured generic 16-bit host master port. this mode, CS98100 control four devices (using chip select outputs), each which different protocol timing. interface ATAPI mode, connect directly ATAPI loader (using chip selects). Simultaneously, other chip selects configured connect other devices, such super chip hard disk. third option configure interface micro-less loader operation, which also configured connect without external glue logic. Serial Interface CS98100 4-pin serial port which interfaces data port popular low-cost loaders. This type loader provides system cost eliminating track buffer, interface FIFO, flow control logic. CS98100 contains large internal SRAM handle high burst data rates, without requiring reverse flow control. track buffer resides CS98100 SDRAM, which reduces system complexity simplifies software architecture. CS98100 performs error detection, sector number tracking, interrupt generation. MPEG Video Decoding Compressed MPEG data read from disk into input FIFO DRAM. data flow (DMA) controller moves Video packets from input FIFO into MPEG decoder's input FIFO (also DRAM). controller also perform advanced functions such start code search, relieving RISC processor. System Sync function used control timing MPEG picture decoding. MPEG Video decoder processes frames, writes video frame buffers DRAM, output display. Special anti-tearing logic ensures currently displayed frame buffers overwritten. Audio Processing Compressed Audio data read from disk into input FIFO DRAM. data decompressed, then written output FIFO, also DRAM. Presentation time stamps (PTS) extracted from stream update STC, order maintain audio/video synchronization. decompression stages audio processing done with combination unit, RISC processors. optimized audio processing, most common formats handled alone, including AC-3, MPEG2 audio, others. enough reserve bandwidth handle Karaoke echo-mix pitch shift, AC-3 down-mix functions. audio output data written into DRAM FIFO 24-bit format. flexible audio output stage simultaneously output channels data audio DACs, plus IEC958 encoded output, kHz. IEC-958 output fully programmable channel status (commercial), provides flexible solution support IEC-958 modes User Data.
CS98100
audio interface also includes flexible input interface, which input wide range protocols from IEC-958 receiver. Another, lowcost approach audio input internal sigmadelta demodulator. This module inputs digital version audio input, which created board using inexpensive ramp generator comparator. sigma-delta demodulator uses programmable filters reconstruct 9bit (mono) audio data sampling frequency. 3.10 Video Processing CS98100 Video processor powerful, fully programmable video post processing engine that displays video interlaced progressive HDTV. 16-tap polyphase vertical filter fully programmable line-by-line basis, provide high quality vertical scaling interlaced field conversion. Horizontal filtering done with programmable 16-tap polyphase filter. This advanced filter processing used de-interlacing, zoom, frame size conversion. Source mode interlaced progressive determined from disk type automatically. progressive source detection, pulldown detected from status flags video stream ensure optimized playback. Interlaced video source filtered progressive size output using bilinear vertical filter. This visibly superior simple line doubling. Each line field being filtered output 480p. Progressive video source output full progressive resolution. Each line frame output 480p. Source mode interlaced progressive determined from disk type. progressive source detection, pulldown simply detected from status flags video stream. Zoom fully programmable, from 500X zoom, with value between. Frame type conversion, from NTSC PAL, NTSC, done with bilinear vertical filter, reducing flicker jaggies. There programmable gamma-correction lookup table final output. Cirrus Logic provides some easy utilities order best advantage powerful video filtering capabilities CS98100. video encoder sends progressive interlaced digital video data internal video encoder, output parallel digital data external video encoder. video processor also allows multiple video plain overlay (main video sub-picture on-screen display). sub-picture unit hardware-only solution which performs high-quality vertical scaling PAL/NTSC conversion, full support (sub-picture) SVCD (OGT) modes. on-screen display unit features 2-bit 4-bit pixels, transparency levels, three independent regions full-screen size. picture-in-picture unit place screen sized window anywhere screen. This feature used special effects, such snapshot freeze zoom assist. 3.11 Video Encoder video encoder uses three 10-bit DACS convert digital data component (RGB YPRPB) composite (composite plus S-Video) analog video. output interlaced (PAL/NTSC) high resolution progressive. progressive mode, video encoder will typically drive YPRPB 525line television 59.94 although other output modes possible, such lines RGB. encoder performs Macrovision copy protection function modes (revision interlaced, revision 1.03 progressive). Other features include built-in voltage reference, color generator, individual power-down control each DAC, programmable baseband filters, color/contrast/tint controls, Closed Captioning (interlaced modes), wide screen signalling (PAL mode), Copy Generation Management System (NTSC progressive modes).
CS98100
MEMORY REGISTERS
Processor Memory CS98100 externally supports Mbytes DRAM Mbytes ROM/NVRAM. Table lists memory viewed RISC processor, identifies whether each segment mapped cacheable.
Processor byte address 0000_0000 07FF_FFFF 8000_0000 81FF_FFFF 9400_0000 9CFF_FFFF 9C00_0000 9CFF_FFFF 9D00_0000 9DFF_FFFF A000_0000 A1FF_FFFF B000_0000 B003_FFFF B400_0000 BCFF_FFFF BC00_0000 BCFF_FFFF BD00_0000 BDFF_FFFF C000_0000 FFFF_FFFF
Description DRAM (mapped) DRAM Mbytes) NVRAM write Mbytes) NVRAM/ROM Mbytes) NVRAM/ROM Mbytes) DRAM Mbytes) Internal (256 Kbytes) NVRAM write Mbytes) NVRAM/ROM Mbytes) NVRAM/ROM Mbytes) DRAM (mapped)
Cacheable
Table Memory RISC Processor
Host Port Memory Table lists memory viewed host slave port.
Host byte address 0000 0000 003F FFFF 1000 0000 13FF FFFF 1400 0000 17FF FFFF
Description Internal Space DRAM space Mbytes) NVRAM space Mbytes) Table Host Port Memory
CS98100
Internal Space Table shows Internal space mapped between general registers, internal SRAM ports, RISC processor debug port.
Byte address offset 0_0000 0_2FFF 0_3000 1_FFFF 2_0000 2_FFFF
Description General registers General Internal SRAM RISC Internal SRAM/Registers
Table Internal Space
CS98100 Register Space Table lists register groups, they split among main CS98100 functional blocks.
CS98100 Register 000xx, 010xx 001xx 002xx 003xx 004xx 005xx 006xx 007xx 008xx 00Axx 00Bxx 00Cxx 00Dxx 00Exx 02xxxx
Block General Host DRAM Controller (DRC) CD/DVD Interface Serial (DVDS) Sync Control MPEG Video Decoder Picture-in-picture Video Processor Subpicture Display On-screen Display In/Out RISC Processor
Table CS98100 Register Blocks
Table lists registers CS98100 their addresses, indicates whether registers read/write (R/W), read only (RO) write only (WO).
CS98100
Address 1040 1044 1048 1064 1068 106C
Type
Function General General General General General General General General General General General General General General (Genio) General (Genio) General (Genio) General (Genio) General (Genio) General (Genio) General (Genio) General (Genio) General (Genio) General (Genio) General (Genio) General (Genio) General (Genio) General (Genio) General (Genio) Table CS98100 Registers
Register Name Command InterProc_Comm_Register_0 InterProc_Comm_Register_1 InterProc_Comm_Register_2 InterProc_Comm_Register_3 Semaphore_Register_0 Semaphore_Register_1 Semaphore_Register_2 Semaphore_Register_3 Semaphore_Register_4 Semaphore_Register_5 Semaphore_Register_6 Semaphore_Register_7 GenIO_Read_Data GenIO_Write_Data GenIO_Three_State_Enable GenIO_Positive_Edge GenIO_Negative_Edge GenIO_Interrupt_Status GenIO_Positive_Edge_Mask GenIO_Negative_Edge_Mask GenIO_Level_Mask GenIO2_Read_Data GenIO2_Write_Data GenIO2_Three_State_Enable GenIO2_Mode GenIODVD_Read_Data GenIODVD_Write_Data
CS98100
Address 1070 1074 Type Function General (Genio) General (Genio) General (Serial IF1) General (Serial IF1) General (Serial IF1) General (Serial IF1) General (Serial IF1) General (Serial IF1) General (Interrupt) General (Interrupt) General (Interrupt) General (Interrupt) General (Interrupt) General (Interrupt) General (Interrupt) General (Interrupt) General (Interrupt) General (Interrupt) General (Interrupt) General (Interrupt) General (Interrupt) General (Interrupt) General (Interrupt) General (Interrupt) General (Timer) General (Timer) General (Timer) General (Timer) General (Timer) General (Timer) Register Name GenIODVD_Three_State_Enable GenIODVD_Mode Ser1_Mstr_Write_1Byte Ser1_Mstr_Write_2Bytes Ser1_Mstr_Control Ser1_Mstr_Status Ser1_Mstr_Read_Data RSK_Interrupt_Mask RSK_Interrupt_Set RSK_Interrupt_Status RSK_Interrupt_Cause DSP_Interrupt_Mask DSP_Interrupt_Set DSP_Interrupt_Status DSP_Interrupt_Cause RSK_Interrupt_Mask2 RSK_Interrupt_Set2 RSK_Interrupt2_Status RSK_Interrupt_Cause2 DSP_Interrupt_Mask2 DSP_Interrupt_Set2 DSP_Interrupt2_Status DSP_Interrupt_Cause2 Timer_0 Timer_1 Timer_2 Timer_3 Timer_Control Performance_Monitor_Count
Table CS98100 Registers (Continued)
CS98100
Address 10F0 10F8 1000 1004 1008 10B0 10B4 10B8 10BC 10C0 10C4 10C8 10CC 10D0 10D4 10E0 10E4 10E8 Type Function General (Timer) General (IR) General (IR) General (IR) General (IR) General (IR) General (PLL) General (PLL) General (PLL) General (PLL) General (PLL) General (PLL) General (DMA) General (DMA) General (DMA) General (Serial IF2) General (Serial IF2) General (Serial IF2) General (Serial IF2) General (Serial IF2) General (Serial IF2) General (Serial IF2) General (Serial IF2) General (Serial IF2) General (Serial IF2) General (Serial IF2) General (Serial IF3) General (Serial IF3) Host Host Register Name Timer_M_Over_N IR_Glitch_Max IR_Control IR_Dram_Start_Address IR_Dram_End_Address IR_Dram_Write_Address PLL_Control_Register1 Low_Power_Clock_Control PLL_Control_Register2 PLL_Turn_Off PLL_Monitor PLL_Clock_Divider DMA2_Source_Addr DMA2_Dest_Addr DMA2_Size Ser2_Mstr_Write_Data_0 Ser2_Mstr_Write_Data_1 Ser2_Mstr_Write_Data_2 Ser2_Mstr_Write_Data_3 Ser2_Mstr_Read_Data_0 Ser2_Mstr_Read_Data_1 Ser2_Mstr_Read_Data_2 Ser2_Mstr_Read_Data_3 Ser2_Mstr_Setup Ser2_Mstr_Command_Status Ser3_Control Ser3_Write_Data Ser3_Read_Data Device_1_Control Device_2_Control
Table CS98100 Registers (Continued)
CS98100
Address 220-224 Type Function Host Host Host Host Host Host Host Host General Host Dram controller Dram controller Dram controller Dram controller Dram controller Dram controller Dram controller Dram controller Dram controller Register Name Device_3_Control Device_4_Control Write_Data_Port Read_Data_Port Host_Start_Address Dram Start Address Stream_Transfer_Size DRAM_Burst_Threshold Ser1_Slave_Address Host_Master_Control DRAM_Controller_Priority0 DRAM_Controller_Priority1 DRAM_Controller_Priority2 DRAM_Controller_Priority3 DRAM_Controller_Priority4 DRAM_Controller_Setup DRAM_Command DRAM_Controller_Mb_Width DRAM_Controller_Debug DMA_Enable DMA_Control DMA_Status Xfer_Byte_Cnt Dram_Byte_Start_Addr Sram_Byte_Start_Addr Fifo_Start_Rd_Addr Fifo_Start_Wr_Addr Search_Control Search_Status Fifo_End_Rd_Addr
Table CS98100 Registers (Continued)
CS98100
Address Type Function CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD DVDS DVDS DVDS DVDS DVDS DVDS DVDS DVDS DVDS DVDS Table CS98100 Registers (Continued) Register Name Fifo_End_Wr_Addr Lines_and_Skip Mask_Pattern_Match DVD_Control DVD_Fifo_Base_Address DVD_Fifo_Size DVD_Sector DVD_Start_of_Sector DVD_Current_Dram_Address CD_Control CD_Error_Status DVD_Status DCI_Control_Reg DCI_Status DCI_Dram_Rd_Start_Addr DCI_Dram_Wr_Start_Addr DCI_Mbytes_Sent DCI_Mbytes_Switch DCI_Diagnostic DCI_Active DVDS_Control DVDS_DataSwap _Mode DVDS_Flow_Control_Ref Track_Buffer_Base Track_Buffer_End Track_Buffer_Current_Address DVDS_Sector_ID DVDS_Bad_Sector_ID Interrupt_Status Interrupt_Enable
CS98100
Address Type Function DVDS DVDS Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Register Name DRAM_Underflow_Status Input_Data_Counter DSP_Boot_Code_Start_Address DSP_Run_Enable DSP_Program_CntRun_Status Audio_Sync_Control Video_Sync_Control Video_Sync_Status Wait_Line Frame_Period STC_Interval System_Time_Clock Top_Bits Video_PTS_FIFO_Start_Address Video_PTS_FIFO_End_Address Video_PTS_FIFO_Write_Address Video_PTS_FIFO_Read_Address Subpicture_PTS_FIFO_End_Address Highlight_Start_PTS Highlight_End_PTS Button_End_PTS Video_PTS Audio_PTS Subpicture_PTS Audio_Time Video_Sync_Debug
Table CS98100 Registers (Continued)
CS98100
Address Type Function Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control MPEG Vid. Decoder MPEG Vid. Decoder MPEG Vid. Decoder MPEG Vid. Decoder MPEG Vid. Decoder MPEG Vid. Decoder MPEG Vid. Decoder MPEG Vid. Decoder MPEG Vid. Decoder MPEG Vid. Decoder MPEG Vid. Decoder MPEG Vid. Decoder MPEG Vid. Decoder MPEG Vid. Decoder MPEG Decoder MPEG Decoder MPEG Decoder MPEG Decoder MPEG Decoder MPEG Decoder MPEG Decoder Register Name SP_DRC_VPTS_Debug Frame_Count_Interrupt Video_DTS Sync_Interrupt_Status Sync_Interrupt_Control Sync_Interrupt_Set Sync_Interrupt_Clear MPEG_Video_Control MPEG_Video_Setup MPEG_Video_FIFO_Start_Address MPEG_Video_FIFO_End_Address MPEG_Video_FIFO_Current_Address MPEG_Video_Horiz_Pan_Vector MPEG_Video_FIFO_Add_Bytes MPEG_Video_FIFO_Curr_Bytes MPEG_Video_FIFO_Interrupt_Bytes MPEG_Video_FIFO_Total_Bytes MPEG_Video_Status Macroblock Width_Height MPEG_Video_Debug MPEG_U_Offset MPEG_I_Base_Register MPEG_P_Base_Register MPEG_Dest_Control MPEG_Software_Flags MPEG_V_Offset MPEG_AntiTearWindow MPEG_Error_Pos PIP_Control PIP_VidBrdStartX
Table CS98100 Registers (Continued)
CS98100
Address Type Function Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Table CS98100 Registers (Continued) Register Name PIP_VidBrdEndX PIP_VidBrdStartY PIP_VidBrdEndY PIP_BorderClr PIP_Vscale PIP_Line_Offnum_Bot PIP_FrBaseY PIP_FrBaseU PIP_FrBaseV PIP_Line_Width PIP_ Line_Offnum_Top PIP_Frame_Size Video_Processor_Control Video_DRAM_Line_Length Display_ActiveX Display_ActiveY Blank_Color Internal_Hsync_Count Internal_Vsync_Count Horizontal_Y_Offset Horizontal_UV_Offset Vertical_Offset Video_Line_Size Frame_Buffer_Base Video_Line_Mode_Buffer Horizontal_Vertical_Filter Source_X_Offset Horizontal_Video_Scaling Mb_Width
CS98100
Address Type Function Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Register Name Anti-Flicker Anti-Flicker Anti-Flicker Anti-Flicker Anti-Flicker Gamma Control Gamma Control Gamma Control Gamma Control Gamma Control Gamma Control Gamma Control Gamma Control ENC_Field_at_EAV Subpicture_Color0 Subpicture_Color1 Subpicture_Color2 Subpicture_Color3 Subpicture_Color4 Subpicture_Color5 Subpicture_Color6 Subpicture_Color7 Subpicture_Color8 Subpicture_Color9 Subpicture_Color10 Subpicture_Color11 Subpicture_Color12 Subpicture_Color13 Subpicture_Color14 Subpicture_Color15
Table CS98100 Registers (Continued)
CS98100
Address Type Function Subpicture Subpicture Subpicture Subpicture Subpicture Screen Display Screen Display Screen Display Screen Display Screen Display Screen Display Screen Display Screen Display Screen Display Screen Display Screen Display Screen Display Screen Display Screen Display Screen Display Screen Display Screen Display Screen Display Screen Display Register Name Subpicture_DCI_Address Subpicture_HLI_Address Subpicture_Control Subpicture_Display_Offset Subpicture_Display_Scale OSD_Status OSD_Control OSD_Color_Number OSD_Color_Data OSD_Region1_Control OSD_Region1_Hlimits OSD_Region1_Vlimits OSD_Region1_DramBase OSD_Region2_Control OSD_Region2_Hlimits OSD_Region2_Vlimits OSD_Region2_DramBase OSD_Region3_Control OSD_Region3_Hlimits OSD_Region3_Vlimits OSD_Region3_DramBase OSD_Blend OSD_Debug1 OSD_Debug2 PCM_Run_Clear PCM_Output_Control PCM_Out_FIFO_Start_Address PCM_Out_FIFO_End_Address PCM_Out_FIFO_Interrupt_Address PCM_Out_FIFO_Current_Address
Table CS98100 Registers (Continued)
CS98100
Address Type Function Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Register Name IEC958_Channel_Status PCM_Input_Control PCM_In_FIFO_Start_Address PCM_In_FIFO_End_Address PCM_In_FIFO_Interrupt_Address PCM_Out_FIFO_Interrupt_Address2 PCM_Out_FIFO_Interrupt_Address3 PCM_In_FIFO_Current_Address IEC958_Output_Control IEC958_Output_FIFO_End_Address IEC958_Output_FIFO_Add_Blocks Reserved Reserved User_Data_Start_Frame User_Data_DRAM_Address User_Data_Interrupt_Frame User_Data_Current_Address VidEnc_PowerDown VidEnc_Status Video_Mode Video_Sync Video_Setup Contrast Brigthness Chroma_Saturation Tint VideoDAC_Select
Table CS98100 Registers (Continued)
CS98100
Address FA0-FFC 2xxxx Type Function Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder RISC Register Name Test Test Test Burst_Gain Component_Mode Sync_Attenuation Sync_Offset Test Closed_Caption_Control Closed_Caption_Data0 Closed_Caption_Data1 Closed_Caption_Data2 Closed_Caption_Data3 WideScreen_Data0 WideScreen_Data1 WideScreen_Data2 Reserved RISC Processor Registers
Table CS98100 Registers (Continued)
CS98100
DESCRIPTIONS
H_D[15:0] H_CS[3:0] H_A[2:0] H_ALE H_RD H_WR H_RDY M_A[11:0] DR_BS_N M_D[31:0] DR_DQM[3:0] DR_RAS_N DR_CAS_N DR_WE_N DR_AP DR_CKE DR_CKO NVM_CE_N NVM_OE_N NVM_WR_N HSYNC VSYNC CLK27_O VDAT[7:0] Y_G_Y U_B_C V_R_YC RSET COMP VREF AUD_XCK AUD_BCK AUD_LRCK AUD_DO[3:0] IEC958_O AIN_DATA AIN_LRCK
ATAPI pins)
Memory pins)
Serial pins)
DVDS_CLK DVDS_DAT DVDS_VLD DVDS_SOS
CS98100
Misc. pins)
XTLCLK_I XTLCLK_O RST_N IR_IN MFG_TST GPIO[7:0] SER_CLK SER_CS SER_DO SER_DI MS_SCL1 MS_SDA1 M_SCL2 M_SDA2
Video pins)
Serial pins)
Audio pins) Audio pins)
Figure CS98100 Layout
Table lists conventions used identify type direction.
Symbol Name Name Description Input Schmitt trigger input pull down resistor pull resistor Output Output drive Output drive Bi-direction Bi-direction drive Bi-direction drive +2.5V +3.3V power supply voltage Power supply ground active active
Table Type Direction Legend
CS98100
ASSIGNMENTS
Table lists number, name type 208-pin CS98100 package. signal pins, direction after reset shown. priPin Name PLL_1V8 M_A11 M_A10 M_A9 M_D8 M_D7 M_D6 IO_GND M_D5 IO_3V3 M_D4 M_D3 M_D2 M_D1 DIG_1V8 M_D0 DR_CKE DIG_GND IO_GND DR_CKO IO_3V3 GPIO1 GPIO2 GPIO3 Type Reset Function Power DR_Addr[11] DR_Addr[10] DR_Addr[9] DR_Data[8] DR_Data[7] DR_Data[6] Ground DR_Data[5] Power DR_Data[4] DR_Data[3] DR_Data[2] DR_Data[1] Core Power DR_Data[0] DR_CKE Core Ground Ground DR_CKO Power GPIO[1] GPIO[2] GPIO[3] NVM_Data[0] NVM_Data[4] NVM_Data[3] NVM_Data[2] NVM_Data[1] NVM_Data[5] NVM_Addr[11] NVM_Addr[10] NVM_Addr[9] NVM_Data[8] NVM_Data[7] NVM_Data[6]
mary function direction shown signal pins. some signal pins, second third function direction also shown.
Function Function Note
Table Assignments
CS98100
Name GPIO4 GPIO5 used used used used used used used used M_BS_N DIG_1V8 DR_AP DIG_GND IO_GND DR_RAS_N IO_3V3 DR_CAS_N M_D31 M_D30 M_D29 M_D28 M_D27 IO_GND M_D26 IO_3V3 M_D25 DR_BS_N Core Power DR_AP Core Ground Ground DR_RAS_N Power DR_CAS_N DR_Data[31] DR_Data[30] DR_Data[29] DR_Data[28] DR_Data[27] Ground DR_Data[26] Power DR_Data[23] NVM_Addr[21] NVM_Addr[22] NVM_Addr[23] Type Reset Function GPIO[4] GPIO[5] Function Function Note
Table Assignments (Continued)
CS98100
Name M_D24 M_D23 M_D22 M_D21 GPIO6 GPIO7 IO_GND NVM_CE_N NVM_OE_N NVM_WE_N IO_3V3 M_D20 M_D19 M_D18 H_A2 H_A1 H_A0 H_ALE M_D17 IO_GND M_D16 M_D15 M_D14 IO_3V3 M_D13 M_D12 M_D11 Type Reset Function DR_Data[24] DR_Data[23] DR_Data[22] DR_Data[21] GPIO[6] GPIO[7] Ground NVM_CE_N NVM_OE_N NVM_WE_N Power DR_Data[20] DR_Data[19] DR_Data[18] Hst_Addr[2] Hst_Addr[1] Hst_Addr[0] Hst_ALE DR_Data[17] Ground DR_Data[16] DR_Data[15] DR_Data[14] Power DR_Data[13] DR_Data[12] DR_Data[11] NVM_Data[13] NVM_Data[12] NVM_Data[11] NVM_Addr[12] NVM_Data[15] NVM_Data[14] NVM_Addr[16] NVM_Addr[15] NVM_Addr[14] GPIO_D[25] GPIO_D{[24] GPIO_D[23] GPIO_D[26] NVM_Addr[13] Function NVM_Addr[20] NVM_Addr[19] NVM_Addr[18] NVM_Addr[17] Function Note
Table Assignments (Continued)
CS98100
Name DIG_1V8 M_D10 DIG_GND IO_GND M_D9 M_A8 M_A7 IO_3V3 H_D3 H_D2 H_D1 H_D0 H_CS3 H_CS2 H_CS1 H_CS0 IO_GND M_A6 M_A5 M_A4 IO_3V3 M_A3 M_A2 M_A1 M_A0 IO_GND VDAT0 Type Reset Function Core Power DR_Data[10] Core Ground Ground DR_Data[9] DR_Addr[8] DR_Addr[7] Power Hst_Data[3] Hst_Data[2] Hst_Data[1] Hst_Data[0] Hst_CS[3] Hst_CS[2] Hst_CS[1] Hst_CS[0] Ground DR_Addr[6] DR_Addr[5] DR_Addr[4] Power DR_Addr[3] DR_Addr[2] DR_Addr[1] DR_Addr[0] Ground Vid_Data[0] GPIO_2[0] NVM_Addr[3] NVM_Addr[2] NVM_Addr[1] NVM_Addr[0] NVM_Addr[6] NVM_Addr[5] NVM_Addr[4] GPIO_D[3] GPIO_D[2] GPIO_D[1] GPIO_D[0] GPIO_D[21] GPIO_D[20] GPIO_D[19] GPIO_D[18] DVD_Error DVD_SOS DVD_Data[3] DVD_Data[2] DVD_Data[1] DVD_Data[0] NVM_Data[9] NVM_Addr[8] NVM_Addr[7] NVM_Data[10] Function Function Note
Table Assignments (Continued)
CS98100
Name VDAT1 VDAT2 VDAT3 VDAT4 VDAT5 VDAT6 VDAT7 HSYNC VSYNC SER_RDY IO_3V3 SER_DO SER_DI SER_CLK AUD_XCK AUD_BCK AUD_LRCK H_WR H_RD MFG_TEST IO_GND DIG_GND AUD_DO0 DIG_1V8 AUD_DO1 AUD_DO2 AUD_DO3 Type Reset Function Vid_Data[1] Vid_Data[2] Vid_Data[3] Vid_Data[4] Vid_Data[5] Vid_Data[6] Vid_Data[7] Vid_Hsync Vid_Vsync SER_CS Power SER_Dout SER_Din SER_Clock AUD_XCK AUD_BCK AUD_LRCK Hst_Write Hst_Read (Tie ground) Ground Core Ground AUD_Dout[0] Core Power AUD_Dout[1] AUD_Dout[2] AUD_Dout[3] GPIO_2[13] GPIO_2[14] GPIO_2[15] GPIO_D[17] GPIO_D[16] DVD_ENA DVD_RDY GPIO_2[12] GPIO_2[9] GPIO_2[10] GPIO_2[11] GPIO_2[8] Function GPIO_2[1] GPIO_2[2] GPIO_2[3] GPIO_2[4] GPIO_2[5] GPIO_2[6] GPIO_2[7] Function Note
Table Assignments (Continued)
CS98100
Name used AIN_DATA used AIN_LRCK IEC958_O GPIO0 MS_SCL1 MS_SDA1 IO_3V3 M_SCL2 M_SDA2 DVDS_CLK DVDS_DAT DVDS_VLD DVDS_SOS CLK27_O used used used IR_IN IO_GND RST_N used PLL_1V8 PLL_GND H_RDY DIG_GND Power Ground Hst_Ready Core Ground GPIO_D[22] DVD_STB Infrared Ground Reset_L B4SU B4SU B4SU B4SU AIN_LRCK AUD_IEC958 GPIO[0] M_SCL2 M_SDA2 Power M_CLK2 M_DAT2 DVDS_CLK DVDS_DAT DVDS_VLD DVDS_SOS Vid_Clock GPIO_2[23] GPIO_2[25] GPIO_2[24] GPIO_2[22] GPIO_2[20] GPIO_2[21] GPIO_2[18] GPIO_2[19] GPIO_2[17] AIN_DATA GPIO_2[16] Type Reset Function Function Function Note
Table Assignments (Continued)
CS98100
Name H_D15 DIG_1V8 H_D14 H_D13 H_D12 H_D11 H_D10 H_D9 H_D8 IO_3V3 H_D7 H_D6 H_D5 H_D4 used used used used DAC_GND DAC_1V8 DAC_DGND U_B_C DAC_3V3 DAC_GND Y_G_Y DAC_3V3 DAC_GND Analog Analog Analog Ground Digital Power Digital Ground Video Analog Power Analog Ground Video Analog Power Analog Ground Type Reset Function Hst_Data[15] Core Power Hst_Data[14] Hst_Data[13] Hst_Data[12] Hst_Data[11] Hst_Data[10] Hst_Data[9] Hst_Data[8] Power Hst_Data[7] Hst_Data[6] Hst_Data[5] Hst_Data[4] GPIO_D[8] GPIO_D[8] GPIO_D[8] GPIO_D[8] DVD_Data[7] DVD_Data[6] DVD_Data[5] DVD_Data[4] GPIO_D[14] GPIO_D[13] GPIO_D[12] GPIO_D[11] GPIO_D[10] GPIO_D[9] GPIO_D[8] CD_LRCK CD_BCLK CD_C2P0 DVDL_DI DVDL_DO DVDL_RDY DVDL_CK Function GPIO_D[15] Function CD_DATA Note
Table Assignments (Continued)
CS98100
Name V_R_YC DAC_3V3 DAC_GND COMP RSET VREF DAC_3V3 DAC_GND DAC_GND DAC_3V3 DAC_3V3 IO_GND DR_WE_N DR_DQM0 DR_DQM1 DR_DQM2 DR_DQM3 IO_3V3 XTLCLK_I XTLCLK_O IO_GND PLL_GND Type Analog Analog Analog Analog Pwr. Reset Function Video Analog Power Analog Ground Compensation Current Voltage Analog Power Analog Ground Analog Ground Analog Power Analog Power Ground DR_WE_N DR_DQM[0] DR_DQM[1] DR_DQM[2] DR_DQM[3] Power Osc. Osc. Ground Ground Function Function Note
Table Assignments (Continued) Note used micro-less loader interface Note should left unconnected Note M_D[31:16] driving when CS98100 reading ROM/NVRAM M_D[15:0], which occurs immediately after reset.
CS98100
Miscellaneous Pins These pins used used basic functions, such clocking, reset, infrared receiver interface.
Signal Name IR_IN XTLCLK_I XTLCLK_O RST_N MFG_TEST Type Description De-modulated infrared Input, from receiver. crystal input, oscillator input crystal output Reset Input, active low. Manufacturing test pin, should always connect ground.
Table Miscellaneous Interface Pins
CS98100
Serial Interface There 2-wire serial controllers, which support industry standard protocols. controller combination master/slave, typically used debug (slave), control small non-volatile memory (master). slave chip select address programmable defaults 7-bit value 0x1A. second 2-wire controller dedicated master used controlling certain
Signal Name MS_SCL1 MS_SDA1 M_SCL2 M_SDA2 SER_CLK SER_DO SER_DI SER_CS Type
devices. third serial controller device supports industry standard 3-wire 4-wire protocols. master mode, this interface control front panel small non-volatile memory. slave mode, operate under control external processor, example, combination unit.
Description Clock 2-wire serial port (master/slave port) Data 2-wire serial port (master/slave port) Clock 2-wire serial port (master) Data 2-wire serial port (master) Clock 4-wire serial port (output master mode, input slave mode) Output data 4-wire serial port function bidirectional data 3-wire mode. Input data 4-wire serial port Chip select 4-wire serial port (output master mode, input slave mode). also used bi-directional ready line.
Table Serial Interface Assignments
CS98100
SDRAM Interface These pins used interface CS98100 with external SDRAM various sizes. Typical configurations Mbyte x16-bit, Mbyte
100,101,102, 203,202,201,200 Signal Name M_D[31:0] Type
x32-bit. Table gives instructions interface particular configuration SDRAM.
Description Memory Data Bus. CS98100 bits only M_D[15:0], which case M_D[31:16] left unconnected.note: bits wide recommended
M_A[11.0]
Memory Address Bus. Connect order starting with M_A[0] address pins already connected DR_BS_N DR_AP. Memory Clock Memory Clock Enable Bank Selection. Always connect pin. Memory Auto Pre-charge. Always connect pin. Memory Address Strobe Memory Column Address Strobe Memory Write Enable Mask Data DR_DQM[3] DR_Data[31:24]
DR_CKO DR_CKE DR_BS_N DR_AP DR_RAS_N DR_CAS_N DR_WE_N DR_DQM[3.0]
Table SDRAM Interface Assignments
CS98100
ROM/NVRAM Interface This interface connects non-volatile memory that contains firmware. memory could ROM, NVRAM (FLASH), EEPROM, combination these. This interface also connect SRAM that emulate development system. width bits. Most these
Signal Name M_D[15:0] Type
pins shared with DRAM interface, which operates simultaneously with ROM/NVRAM interface.
Description NVM_Data[15:0], Memory Data (shared with bits [15:0] DRAM data bus). M_D[7:0] 8-bit interface. NVM_Addr[11:0], Memory Address Bus[11:0] (shared with DRAM address bus) NVM_Addr[23:12], Memory Address Bus[23:12] (shared with bits [27:16] DRAM data bus) ROM/NVRAM Chip Enable. ROM/NVRAM Output Enable. Copy ROM/NVRAM Output Enable. NVRAM Write Enable.
M_A[11:0] M_D[27:16]
NVM_CE_N NVM_OE_N M_D[31] NVM_WE_N
Table ROM/NVRAM Interface Assignments
CS98100
Digital Video Output Interface This interface used drive CCIR601/CCIR-656 digital data external video encoder (such CS4955), example fourth required. CS98100 sync master
this interface. progressive mode, data pins output both edges clock. Optionally, this interface used only generate separate combined horizontal/ vertical sync, example drive syncs monitor.
Description
112, 111, 110, 109, 108, 107, 106,
Signal Name HSYNC VSYNC CLK27_O VDAT[7:0]
Type Horizontal Sync output
Vertical combined vertical/horizontal Sync output Clock Output. Video Data Output[7:0] YCrCb format.
Table Video Output Interface Assignments
CS98100
Audio Output/Input Interface This audio interface that connects audio CODEC. sample rate size
samples programmable both input output direction.
Signal Name AUD_XCK AUD_BCK AUD_LRCK AUD_DO0 AUD_DO1 AUD_DO2 AUD_DO3 IEC958_O AIN_DATA AIN_LRCK
Type
Description Audio 256x/384x Clock input output Serial DAC. When output, it's generated from CS98100 internal PLL. Audio Clock output serial DAC. Polarity programmable. Audio Left/Right Clock serial DAC. Audio Serial Data Out[0] (Front) Audio Serial Data Out[1] (Surround) Audio Serial Data Out[2] (Center LFE) Audio Serial Data Out[3] (2-channel downmix) IEC-958 Output This input come from from external comparator. Left/Right Clock. Input from external audio ADC. CS98100 programmed Audio Output function's internally generated clock, which case this required.
Table Audio Output Interface Assignments
CS98100
Host Master/ATAPI Interface This 16-bit parallel host interface allows CS98100 host master, controlling other devices that would used same system. interface supports programmable protocols speeds, including multiplexed non-multiplexed addressing. Slaves with different protocols connected same time, controlled different
160, 162, 163, 164, 165, 166, 167, 168, 170, 171, 172, 173, Signal Name H_CS[3:0] H_ALE H_RD H_WR H_RDY H_A[2:0] H_D[15:0] Type
chip selects. example, chip selects used control ATAPI device, while other chip selects control another ATAPI non-ATAPI slave device.
Description Host Chip Select[3:0]. host master programmed different protocol each chip selects Host address latch enable. Used modes which multiplex upper address information onto data lines Host Read Request. Host Write Request. Host Ready. Connect pull-up pull-down host used. Host Address[2:0]. Host Data Bus[15:0]. These pins also output Host Address during address phase multiplexed address/data mode. together pull-up pull-down host used.
Table Host Master Interface Assignments
CS98100
Channel Interface This interface connects standard loaders, consists three parts: Control, Data Data. This interface shares CS98100 pins with Host Master/ATAPI interface. definiPin 170, 171, 172, 173, Signal Name DVD_SOS DVD_Error H_RD H_WR H_RDY H_D[7:0] CD_C2P0 CD_BCLK CD_LRCK CD_DATA DVDL_CK DVDL_RD DVDL_DO DVDL_DI Type
tion register programming, modes mutually exclusive.
Description data start sector signal from loader data error signal from loader DVD_RDY, data ready signal loader DVD_ENA, data enable signal from loader DVD_STB, data clock from loader DVD_Data[7:0], data port parallel data input from loader error signal from loader clock from loader left/right clock from loader serial data from loader Control port clock loader Control port ready signal from loader Control port serial command loader Control port serial status from loader
Table Channel Interface Assignments
CS98100
Serial Data Interface This interface connects data port cost loaders using 4-wire serial interface. this case, control loader will typically done using 2-wire serial interface master. ATAPI/IO channel pins then free used
Signal Name DVDS_CLK DVDS_DAT DVDS_VLD DVDS_SOS Type
second loader, general purpose ATAPI, GPIOs.
Description clock input rising edge active edge serial data input (data input first) valid data clocked when this high start sector input active high
Table Serial Data Interface Assignments
CS98100
6.10 Video Encoder Interface video encoder interface three outputs, operates three modes: component YUV, component RGB, S-Video plus composite. component modes operate eiPin Signal Name U_B_C Y_G_Y V_R_YC COMP RSET VREF Type
ther normal interlaced resolution, progressive (high resolution).
Description Analog video output U(YUV), B(RGB), C(Y/C/YC) Analog video output Y(YUV), G(RGB), Y(Y/C/YC) Analog video output V(YUV), R(RGB), YC(Y/C/YC) Compensation pin, should connect through 0.1µF capacitor analog 3.3V supply Current adjust pin, connect through 174,1% resistor analog ground Voltage reference pin, connect through 0.1µF capacitor analog ground
Table Video Encoder Interface Assignments
CS98100
6.11 General Purpose Input/Output (GPIO) CS98100 provides number GPIO pins, each with individual output three-state controls. There eight dedicated GPIO pins, which also used generate internal interrupts based edge level events pins. groups adPin 146, 147, 148, 143, 142, 139, 136, 134, 131, 130, 121, 118, 117, 115, 111, 110, 109, 107, 106, 145, 140, 132, 119, 112, 108, Signal Name GPIO[7:0] Type GPIO_2[2 5:24] GPIO_2[2 3:20] GPIO_2[1 9:16] GPIO_2[1 5:12] GPIO_2[1 1:8] GPIO_2[7: GPIO_2[3: 160, 165, 170, GPIO_D[2 6:24] GPIO_D[2 3:20] GPIO_D[1 9:16] GPIO_D[1 5:12] GPIO_D[1 1:8] GPIO_D[7: GPIO_D[3:
ditional pins also re-defined GPIOs required other functions. Each these additional pins control register select either GPIO normal function pin.
Description General purpose dedicated pins General purpose I/Os, redefined from following pins: DVDS_VLD, DVDS_SOS, DVDS_DAT, CLK27_O, SDA2, SCL2, SDA1, SCL1, AIN_LRCK, AIN_DATA, AUD_DO_3, AUD_DO_2, AUD_DO_1, AUD_BCK, SER_CLK, SER_DI, SER_DO, SER_RDY, VDAT_7, VDAT_6, VDAT_5, VDAT_4, VDAT_3, VDAT_2, VDAT_1, VDAT_0
158, 123, 124, 162, 163, 164, 166, 167, 168, 171, 172, 173,
General purpose I/Os, redefined from following pins: H_ALE, H_A_2, H_A_1, H_A_0, H_RDY, H_CS_3, H_CS_2, H_CS_1, H_CS_0, H_WR, H_RD, H_D_15, H_D_14, H_D_13, H_D_12, H_D_11, H_D_10, H_D_9, H_D_8, H_D_7, H_D_6, H_D_5, H_D_4, H_D_3, H_D_2, H_D_1, H_D_0
Table General Purpose Interface Assignments
CS98100
6.12 Power Ground CS98100 requires five different types power supplies Plus, internal logic, pins, video DAC-digital video analog. PLLs, internal logic video digital supply voltage. pins video analog supply voltage. recommended good
157, 129, 127, 116, 141, 169, 104, 126, 153, 198, 182, 185, 188, 193, 196, 178, 183, 186, 189, 194, Signal Name PLL_1V8 PLL_GND DIG_1V8 DIG_GND IO_3V3 Type 1.8V internal PLLs Ground internal PLLs 1.8V internal core logic Ground internal core logic 3.3V Digital I/Os
layout techniques provide isolation between supply types board. Contact Cirrus Logic applications engineering layout guidelines.
Description
IO_GND
Ground Digital I/Os
DAC_1V8 DAC_DGND DAC_3V3 DAC_GND
Digital 1.8V video Digital ground video Analog 3.3V video Analog ground video Table Power Ground
CS98100
MQFP PACKAGE SPECIFICATIONS
30.60±0.30 28.00±0.13
3.68(MAX) 3.23 ±0.08 0.10(MIN)
28.00±0.13
30.60±0.30
0.50±0.10
Detail
+0.10 0.15 -0.05 WITH PLATING 0.20 ±0.05 BASE METAL 1.30±0.20
0~10°
0.50±0.20
DETAIL
Notes: Measurement Unit Figure CS98100 208-Pin MQFP Package Drawing

32-Bit RISC Processor, supported RTOS, C/C++ compilers 32-bit cap

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