CS5540 low-power low-voltage analog-to-digital converter (ADC), which

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CS5540 low-power low-voltage analog-to-digital converter (ADC), which

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CS5540 Low-Power, Low-Voltage,
CS5540 low-power low-voltage analog-to-digital converter (ADC), which achieves highly accurate conversions using simple non-programmable interface that easy understand design-in. optimized convert analog signals measurement applications, such temperature pressure measurement, various portable devices where low-power consumption required. accommodate these applications, integrates analog input reference buffers increased input impedance two-channel multiplexer. CS5540 includes digital filter, which achieves simultaneous rejection 50/60 signals provides single conversion settling throughput. Absolute accuracy achieved continuous internal self-calibration. device draws nominal Low-power, low-voltage operation, simple serial interface make CS5540 ideal device low-cost, power-conscious measurement applications. ORDERING INFORMATION CS5540-AS 16-Pin SSOP
Analog-to-Digital Converter
Linearity Error: 0.0015% Noise:
Channel Differential Buffered, Fully Differential Analog Voltage Reference Inputs Scalable VREF Input: Analog Supply High Absolute Accuracy Self-Calibration Fixed Digital Filter
Single Conversion Settling Simultaneous 50/60 Rejection
Simple
Serial Interface
MicrowireCompatible Schmitt Trigger Serial Clock (SCLK)
SPI
Power
Single +3.0 Supply Supply Current Sleep Mode
VREF+
VREF-
OSC1 OSC2
Clock Generator
Serial Interface
AIN1+ AIN1AIN2+ AIN2Input
Differential Order
Modulator
Digital Filter
Calibration Register
SCLK
Output Register
DGND
Preliminary Product Information
P.O. 17847, Austin, Texas 78760 (512) 7222 FAX: (512) 7581 http://www.cirrus.com
This document contains information product. Cirrus Logic reserves right modify this product without notice.
Copyright Cirrus Logic, Inc. 2000 (All Rights Reserved)
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TABLE CONTENTS
CHARACTERISTICS SPECIFICATIONS GENERAL DESCRIPTION Analog Input 2.1.1 Analog Input Model Voltage Reference Input 2.2.1 Voltage Reference Input Model Power Supply Arrangements Clock Generator Serial Port Interface Input Channel Selector 2.6.1 Switching Channels Serial Port Data Conversions 2.7.1 Reading Conversions 2.7.2 Output Coding 2.7.3 Digital Filter Sleep Mode Power-Up Initialization 2.10 Layout DESCRIPTIONS SPECIFICATION DEFINITIONS PACKAGE DIMENSIONS
Contacting Cirrus Logic Support
complete listing Direct Sales, Distributor, Sales Representative contacts, visit Cirrus Logic site
trademark Motorola Inc. Microwire trademark National Semiconductor Corp. Preliminary product information describes products which production, which full characterization data available. Advance product information describes products which development subject development changes. Cirrus Logic, Inc. made best efforts ensure that information contained this document accurate reliable. However, information subject change without notice provided without warranty kind (express implied). responsibility assumed Cirrus Logic, Inc. this information, infringements patents other rights third parties. This document property Cirrus Logic, Inc. implies license under patents, copyrights, trademarks, trade secrets. part this publication copied, reproduced, stored retrieval system, transmitted, form means (electronic, mechanical, photographic, otherwise) without prior written consent Cirrus Logic, Inc. Items from Cirrus Logic website disk printed user. However, part printout electronic files copied, reproduced, stored retrieval system, transmitted, form means (electronic, mechanical, photographic, otherwise) without prior written consent Cirrus Logic, Inc.Furthermore, part this publication used basis manufacture sale items without prior written consent Cirrus Logic, Inc. names products Cirrus Logic, Inc. other vendors suppliers appearing this document trademarks service marks their respective owners which registered some jurisdictions. list Cirrus Logic, Inc. trademarks service marks found http://www.cirrus.com.
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LIST FIGURES
Figure Continuous Running SCLK Timing (Not Scale) Figure Read Timing (Not Scale). Figure Multiplexer Configuration. Figure Input model AIN+ AIN- pins. Figure Resolution Voltage Reference. Figure Input model VREF+ VREF- pins. Figure CS5540 Configured with single +3.0 Supply. Figure Command Data Word Timing. Figure Self Calibration Offset. Figure Self Calibration Gain. Figure Digital Filter Response.
LIST TABLES
Table Output Conversion Data Register Description bits flags) Table CS5540 24-Bit Bipolar Output Coding
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CHARACTERISTICS SPECIFICATIONS
ANALOG CHARACTERISTICS +3.0 ±5%, ±5%, DGND VREF+ VREF- MCLK 32.768 kHz, (Output Word Rate) SPS, Input Range ±2.5 Differential, Vcm=1.25 (See Note
Parameter Accuracy Linearity Error Missing Codes Offset Error Offset Drift Full Scale Error Full Scale Drift Noise Bandwidth (Note (Notes (Note (Notes ±0.0015 11.96 ±0.003 Bits LSB24 nV/°C ppm/°C Units
Notes: Specifications guaranteed design, characterization, and/or test. Specification applies device only does include effects caused external parasitic thermocouples. Drift over specified temperature range after power-up Wideband noise aliased into baseband. Referred input. Typical values shown peak-to-peak noise multiply value 6.6.
Specifications subject change without notice.
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ANALOG CHARACTERISTICS (Continued)
Parameter Analog Input Common Mode Signal AIN+ AINSingle Supply Dual Supplies Current AIN+, AINInput Leakage when Common Mode Rejection Input Capacitance Voltage Reference Input Range (VREF+) (VREF-) (Note (Note (Note 1/OWR MCLK/2 (VA+) (VA-) 60Hz (Note VA12 Units
Current VREF+ VREFCommon Mode Rejection Input Capacitance Dynamic Characteristics Modulator Sampling Frequency Filter Settling (Full Scale Step) Power Supplies Power Supply Currents (Normal Mode) Normal Mode Sleep Mode Positive Supplies Negative Supplies
(Note
1000
Power Consumption Power Supply Rejection
Notes: Section 2.1, "Analog Input". Section 2.2, "Voltage Reference Input". Absolute voltages VREF+ VREF- must less than equal supply voltages. CS5540 includes digital filter. filter which achieves simultaneous rejection 50/60 provides single conversion settling throughput. outputs unloaded. inputs CMOS levels.
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±5%, DGND (See Notes 11.) voltage levels measured relative DGND. Parameter High-Level Input Voltage: Pins Except OSC1, SCLK OSC1 SCLK OSC1, SCLK OSC1 SCLK SDO, Iout -1.0 SDO, Iout 1.6mA Symbol Cout 0.6VD+ (VD+)-0.45 (VD+)-.25 0.16VD+ Units
DIGITAL CHARACTERISTICS
Low-Level Input Voltage:
Pins Except
High-Level Output Voltage: Low-Level Output Voltage: Input Leakage Current 3-State Leakage Current Digital Output Capacitance
Notes: measurements performed under static conditions.
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ABSOLUTE MAXIMUM RATINGS (DGND Note 12.)
Parameter Power Supplies (Notes Positive Digital Positive Analog Negative Analog (Notes (Note VREF pins Symbol VAIIN IOUT VINA VIND Tstg -0.3 -0.3 -0.3 (VA-) (-0.3) -0.3 +4.0 +4.0 +0.3 (VA+)+0.3 (VD+)+0.3 +150 Units
Input Current, Except Supplies Output Current Power Dissipation Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature
Notes: voltages measured with respect digital ground (DGND). must satisfy {(VA+) (VA-)} +4.0 must satisfy {(VD+) (VA-)} +4.0 Applies pins including continuous overvoltage conditions analog input (AIN) pins. Transient current 100mA will cause latch-up. Maximum input current power supply Total power dissipation, including input currents output currents. WARNING: Operation beyond these limits result permanent damage device. Normal operation guaranteed these extremes.
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SWITCHING CHARACTERISTICS +3.0 ±5%,
DGND Input Levels: Logic Logic VD+; 50pF) Parameter Master Clock Frequency: Master Clock Duty Cycle Rise Times (Note Digital Input Except SCLK SCLK Output (Note Digital Input Except SCLK SCLK Output XTAL 32.768 (Note trise trise tost tpor MCLK cycles Symbol External Clock MCLK Internal Oscillator (Note 32.768 Units
Fall Times
Start-up Oscillator Start-up Time Power-on Reset Period Serial Port Timing Serial Clock Frequency Serial Clock Enabled SCLK Rising SCLK falling prior Chip Select Disabled Read Timing Data Valid SCLK Falling Data Rising Hi-Z Pulse Width High Pulse Width SCLK
Notes: Device parameters specified with 32.768 clock; however, clocks used increased throughput. Specified using points waveform interest. Output loaded with Oscillator start-up time varies with crystal parameters. This specification does apply when using external clock source.
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SCLK
Figure Continuous Running SCLK Timing (Not Scale)
MSB-1
SCLK
Figure Read Timing (Not Scale)
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GENERAL DESCRIPTION
CS5540 low-power low-voltage 24-bit analog-to-digital converter (ADC). optimized convert analog signals measurement applications such temperature pressure measurement, various portable devices where power consumption required. accommodate these applications, integrates analog input reference buffers increased input impedance includes two-channel multiplexer. Absolute accuracy accomplished self-calibration. device also operates with variety supply configurations while drawing nominal CS5540 includes digital filter which achieves simultaneous rejection 50/60 provides single conversion settling throughput. filter's output word rate increased approximately 1.22X using master clock, although 50/60 rejection will sacrificed. ease communications between microcontroller, converter includes simple three-wire serial interface which Microwire compatible. Schmitt Trigger input provided serial clock (SCLK) input.
Analog Input
Figure illustrates block diagram CS5540. device consists multiplexer, unity gain coarse/fine charge input buffer, fourth order modulator, digital filter.
2.1.1 Analog Input Model
Figure illustrates input models pins. model includes coarse/fine charge buffer which reduces dynamic current demands from analog input signal. buffer designed accommodate rail rail (common-mode plus signal) input voltages. Typical (sampling) current about (MCLK 32.768 kHz). Application Note "Switched-Capacitor Input Structures", details various input architectures.
Fine 25mV Coarse 2*MCLK 65.536
Figure Input model AIN+ AIN- pins
VREF+ VREFX1
AIN1+ AIN1AIN2+ AIN2CHS Differential Order
Modulator
Sinc Digital Filter
Serial Port
SCLK
Figure Multiplexer Configuration DS503PP1
CS5540
Voltage Reference Input
differential voltage between VREF+ VREF- sets nominal full scale input span converter. single-ended reference voltage, reference output connected VREF+ CS5540 ground reference connected VREF- pin. Note that differential reference voltage from ((VA+)- (VA-)). noise-free resolution single sample from directly proportional voltage reference depicted Figure
Note: When lower reference voltage used, resulting code widths smaller. Since output codes exhibit more changing codes fixed amount noise, converter appears noisier.
2.2.1 Voltage Reference Input Model
Figure illustrates input models VREF pins. includes coarse/fine charge buffer which reduces dynamic current demand external reference. reference's buffer designed accommodate rail-to-rail (common-mode plus signal) input voltages. Typical (sampling) current about (MCLK 32.768 kHz).
Fine CVosf VREF Coarse 2*MCLK 65.536
Figure Input model VREF+ VREF- pins
Noise-Free Resolution (Bits) VREF
25mV
Figure Typical Noise-Free Resolution Voltage Reference Noise-Free Res. log2 (Bipolar Span/6.6*RMS Noise)
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Power Supply Arrangements
CS5540 designed operate with total supply voltage maximum flexibility, separate pins provided VA+, VA-, VD+, DGND, which especially useful with ground-referenced input signals. Figure illustrates CS5540 connected with single +3.0 supply both analog digital sections.
Serial Port Interface
CS5540's serial interface consists three control lines: SDO, SCLK. Chip Select, control line which enables access serial port. tied logic port function three wire interface. SDO, Serial Data Out, data signal used transfer output data from converters. output will held high impedance time logic SCLK, Serial Clock, serial bit-clock which controls shifting data from ADC's serial port. must held logic before SCLK transitions recognized port logic. accommodate opto-isolators, SCLK designed with Schmitt-trigger input.
Clock Generator
CS5540 includes oscillator circuit which connected with external crystal provide master clock chip. chip designed operate using low-cost 32.768 "tuning fork" type crystal. lead crystal should connected OSC1 other OSC2. megohm resistor required parallel with crystal. Lead lengths should minimized reduce stray capacitance. Note that converter will operate with external (CMOS compatible) clock with frequencies 40kHz, applied OSC1 pin.
Input Channel Selector
CHS, Channel Select input, permits user select between AIN1 AIN2 data conversions. When AIN1 converted. When AIN2 converted. Note that since converter continuously converts input selected
+3.0 Analog
Supply
VREF+ VREF13
OSC2
Voltage Reference
OSC1 Optional Clock Source Serial Data Interface
CS5540
AIN1+ AIN1CS SCLK
Analog Signal Sources
AIN2+ AIN2VA3 DGND
Channel Selection
Figure CS5540 Configured with single +3.0 Supply
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CHS, channel being converted switched time. conversion in-process when switched will aborted conversion will begin selected channel. indicator bits output will indicate which channel converted. decode conversion word into respective flag data bits.
Note: CS5540 offers self calibration, which calibrates offset gain errors itself. Calibration CS5540 used zero gain slope ADC's transfer function. self-calibration offset, converter internally ties inputs modulator together routes them VREF- shown Figure VREF- must tied fixed voltage between VA-. self-calibration gain, differential inputs modulator connected VREF+ VREF- shown Figure10. Further note that each calibration step (offset gain) transparent user included specified output rate.
2.6.1 Switching Channels
7358 clock cycles after toggled, will fall (indicating data present). subsequent data will presented serial port every 4884 clock cycles, portrayed Figure
Serial Port Data Conversions
When power applied CS5540, reset power-on reset circuit. Then converter enters data mode where continuously converts analog input channel selected channel select (CHS). After conversion complete, falls logic indicate conversion next serial clock pulses shift data serial port. Figure illustrates sequence necessary read output data from data conversion register. CS5540 operates self-calibration mode which allows converter calibrate continuously between each conversion user requires system calibration, this accommodated system microcontroller). sections that follow detail conversion mode also explain
SCLK
AIN+
AINVREF-
Figure Self Calibration Offset
7358 clock cycles 4884 clock cycles
while reading status data
SCLKs read status Data Time SCLKs
Figure Command Data Word Timing
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channel switched when low, will remain low, previous conversion result will remain serial port. will rise MCLK cycle before channel's data ready, then fall indicate that conversion data available.
AIN+
AINVREF+ Reference VREF-
2.7.2 Output Coding
CS5540 outputs 24-bit two's-complement data conversion word. read conversion word user must read conversion data register, which bits long outputs conversions first. Once conversion complete, falls SCLK's required read conversion. first SCLKs used clear internal flag clock status flags. (CHannel indicator) keeps track which input channel converted (0=AIN1; 1=AIN2). (Oscillation Detect) logic time that oscillatory condition detected modulator. This does occur under normal operating conditions, occur whenever input converter extremely overranged. set, conversion data bits completely erroneous. flag will cleared logic when modulator becomes stable. (Overrange Flag) logic time input signal more positive than positive full scale, more negative than negative full scale. cleared back logic whenever conversion word occurs which overranged. last SCLKs used clock actual data conversion data register. Table Table illustrate output coding CS5540. Conversion data output two's complement format.
Figure Self Calibration Gain
2.7.1 Reading Conversions
completion conversion, will fall logic indicate that conversion complete. Calibration will transparent user. Nevertheless, read conversion word, user must issue SCLK's. first SCLKs clear flag read status flags. Upon falling edge SCLK, will present first (MSB) conversion word. SCLKs (high, then low) then required read conversion word from port. Upon falling edge 32nd SCLK, will return high, waiting till next conversion complete before falls again. user required read every conversion. user chooses read conversion after falls, will rise MCLK clock cycle before next conversion completed then fall signal that another conversion word available (assuming kept low).
Note: user begins clear flag read conversion data, this action must finished before conversion cycle which occurring background complete user wants able read conversion data. multiplexer input converter switched while performing conversion, filter will abort current conversion start conversion channel.
2.7.3 Digital Filter
CS5540 filter achieves simultaneous rejection 50/60 provides single conversion settling throughput, including auto-calibration.
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filter optimized yield better than rejection between (i.e. minimum rejection both when master clock 32.768 kHz. filter's output word rate increased approximately 1.22X using master clock, although 50/60 rejection will sacrificed. filter response shown Figure
Note: converter's digital filter linearly scales with MCLK.
Magnitude (dB)
-100
-120 -140
Frequency (Hz)
Figure Filter Response (MCLK 32.768 kHz)
Table Output Conversion Data Register Description bits flags)
Bipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5 Two's Complement 7FFFFF 7FFFFF -7FFFFE 000000 -FFFFFF 800001 -800000 800000
-0.5
-VFS+0.5 <(-VFS+0.5 LSB)
Table CS5540 24-Bit Bipolar Output Coding Note: Plus minus defined differential input signal equal magnitude voltage between VREF+ VREF- pins. text about error flags overrange underrange conditions.
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Sleep Mode
CS5540 features power consumption modes: normal sleep. normal mode, default mode, entered after power-on-reset. normal mode, CS5540 performs conversions typically consumes enter sleep, transmit SCLK's (low-high transitions) after falls, indicating that conversion complete SCLK's would needed read conversion). conversion cycle later, when falls again, part enters sleep, reducing consumed power around During sleep, most analog portion chip powered down filter convolutions halted. While part sleep mode, will remain logic high state, long Chip Select enabled. exit sleep mode, transmit more SCLK's. Since sleep mode disables oscillator, approximately crystal oscillator start-up delay period required before returns normal mode. external clock used, will return normal power mode within milliseconds. either case, will indicate when data available read. delay being used drive ADC, then conversions will begin immediately.
Note: CS5540 includes on-chip power reset circuit automatically reset shortly after power-up. When power CS5540 applied, held reset condition until master clock started counter-timer elapses (i.e. counter-timer counts clock cycles make sure oscillator fully stable).
After valid reset, initialized into data state where begins continuously calibrate convert analog input. Once valid conversion complete, monitor falling edge indicate that data ready read.
2.10 Layout
CS5540 should placed entirely over analog ground plane with DGND device connected analog ground plane. Place analog-digital plane split immediately adjacent digital portion chip CDB5540/41 data sheet suggested layout details refer Applications Note more detailed layout guidelines. Applications engineering provides Free Confidential Schematic Review Service.
Power-Up Initialization
Care must exercised insure that pins ever taken below negative analog supply (VA-) potential. analog digital supplies should applied simultaneously assure that power-on reset circuit will automatically reset when both supplies acceptable levels. Conversions will begin once stable clock available ADC. 32.768 crystal being used, will take approximately oscillator stabilize begin conversions after power been applied converter. CMOS compatible clock source with start-up
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DESCRIPTIONS
AIN1+ AIN1VAVA+ SCLK OSC1
AIN2+ AIN2VREF+ VREFDGND OSC2
Clock Generator OSC1; OSC2 Master Clock. inverting amplifier inside chip connected between these pins used with crystal resonator provide master clock device. Alternatively, external (CMOS compatible) clock (powered relative VD+) supplied into OSC1 provide master clock device OSC2 left unconnected. Control Pins Serial Data Chip Select. When active low, port will recognize SCLK. When high will output high impedance state. should only changed when SCLK Serial Data Output. serial data output. will output high impedance state SCLK Serial Clock Input. clock signal this determines output rate data pins respectively. This input Schmitt trigger allow slow rise-time signals. SCLK will recognize clocks only when low. Channel Select Input. permits user select between AIN1 AIN2 data conversions. When AIN1 converted. When AIN2 converted. Note that since converter continuously converts input selected CHS, channel being converted switched time. current conversion will aborted started newly selected channel. serial data status flags will indicate which channel converted.
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CS5540
Measurement Reference Inputs AIN1+, AIN1-, AIN2+, AIN2- Differential Analog Inputs. Differential input pins into device. VREF+, VREF- Voltage Reference Inputs. Fully differential inputs which establish voltage reference on-chip modulator. Power Supply Connections Positive Analog Power. Positive analog supply voltage. Negative Analog Power. Negative analog supply voltage. Positive Digital Power. Positive digital supply voltage. DGND Digital Ground. Ground return digital supply.
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SPECIFICATION DEFINITIONS
Linearity Error deviation code from straight line which connects points Converter transfer function. point located below first code transition other point located beyond code transition ones. Units percent full-scale. Differential Nonlinearity deviation code's width from ideal width. Units LSBs. Full Scale Error deviation last code transition from ideal [{(VREF+) (VREF-)} LSB]. Units LSBs. Offset Error deviation mid-scale transition (111.111 000.000) from ideal (1/2 below zero volts differential between AIN+ AIN- pins). Units LSBs.
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PACKAGE DIMENSIONS
SSOP PACKAGE DRAWING
SIDE VIEW
VIEW
SEATING PLANE
VIEW
INCHES -0.002 0.064 0.009 0.232 0.291 0.197 0.022 0.025 -0.005 0.069 0.012 0.244 0.307 0.209 0.026 0.0295 0.084 0.010 0.074 0.015 0.256 0.323 0.220 0.030 0.041 -0.05 1.68 0.22 5.90 7.40 5.00 0.55 0.63
MILLIMETERS -0.13 1.75 -6.20 7.80 5.30 0.65 0.75 2.13 0.25 1.88 0.38 6.50 8.20 5.60 0.75 1.03
NOTE
JEDEC MO-150 Notes: "E1" reference datums included mold flash protrusions, include mold mismatch measured parting line, mold flash protrusions shall exceed 0.20 side. Dimension does include dambar protrusion/intrusion. Allowable dambar protrusion shall 0.13 total excess dimension maximum material condition. Dambar intrusion shall reduce dimension more than 0.07 least material condition. These dimensions apply flat section lead between 0.10 0.25 from lead tips.
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Notes

CS5540 low-power low-voltage analog-to-digital converter (ADC), which

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