Compliant with Serial Gen1 Revision 1.0a Specification Power Oper

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Compliant with Serial Gen1 Revision 1.0a Specification Power Oper

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Gbps Bi-directional Transceiver
Compliant with Serial Gen1 Revision 1.0a Specification
Power Operation
Channel Nominal
Blocks Include
Integrated Processor K28.5 COMMA Detection Digital Clock Data Recovery (CDR) with Digital Equalization Spread Spectrum Clocking Optional 8B/10B Encoder Decoder Parallel Synchronous 8-bit/10-bit Parallel Interface Serial Programmable Pre-emphasis Programmable Swing Control Passive Equalization Receive Input Buffer Support Spread Spectrum Clocking Integrated Matched Differential Termination Coupling Support Test Features Far-end Near-end Loopback Support Speed BIST Scan Test Physical Coding Sub-layer (PCS)
2-channel Serial AT78C5090 Summary
Overview
AT78C5090 2-channel SATA supporting speeds Gbps. been designed based requirements stated Serial Standard, 1.0a, 2003. transmit path, parallel data registered, passed through transmit FIFO compensate phase differences between link clocks, 8B/10B encoded then passed high speed serializer using spread spectrum clock. Builtin flexibility permits bypassing encoding block addition optionally disabling spread spectrum clocking. user control transmit buffer output swing pre-emphasis levels direct input signals. receive path, AT78C5090 performs serial-to-parallel conversion, using high bandwidth clock data recovery (CDR) block. recovered data then passed through comma alignment block optional 8B/10B decode block before being passed phyCtrl layer parallel interface. This interface synchronous recovered clock. core band (OOB) processor. specified Serial standard, three band (OOB) signals used/detected PHY, namely COMRESET, COMINIT, COMWAKE. Each these signals indicated number bursts four ALIGN primitives followed defined idle periods during which differential voltage serial line null. signals observed detecting temporal spacing between adjacent bursts activity. Test functions including BIST, scan, parallel serial loopback modes configured controlled direct input signals. Similarly, error/status bits indicated through direct output signals such bistErr.
3526AS-NETST-10/04
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Block Diagram(1)
t[7:0] tBIMSB syncMode txClk bist bistErr enDec lBEn[2:0] pOR, phyReset rxRefMode frcPhyRdy cfgHostMode gotCIOrR gotComWake phyRdy scanClk,scanEn scanResetL scanMode scanIn1,2 scanOut1,2 vizGroup[15:0] rDat2Link[10:0] phyRClk phyIntErr enCommaDet txPreEmCtrl[2:0]
Serializer FIFO 8B/10B Encode
txSSCMode[2:0] rxSCCMode refClk dual, rate
BIST Test Pattern Generator Control Block Processor
High Speed PLLs
pllFilt pllBGap
iDDQEn debugEnL debugSel[3:0] debugClk
Analog Bias 8B/10B Decode Digital
anaViz txAmpCtrl[3:0] resRef VSSRESREF
Note:
block diagram only shows channel.
AT78C5090
3526AS-NETST-10/04
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3526AS-NETST-10/04

Compliant with Serial Gen1 Revision 1.0a Specification Power Oper

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