HSTL LVTTL Fanout Buffer Preliminary Information Table Clock Enab

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HSTL LVTTL Fanout Buffer Preliminary Information Table Clock Enab

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FS6070-01
HSTL LVTTL Fanout Buffer
Preliminary Information Table Clock Enable Configuration
CONTROL OE_0 OE_1 DIVSEL CLOCK OUTPUTS Q0_1:2 Tristate Tristate Tristate HREF HREF HREF HREF Q1_3:4 Tristate HREF HREF Tristate Tristate HREF HREF
October 2000
Features
Distributes differential HSTL HCSL reference clock banks single-ended LVTTL outputs DIVSEL selects output divide-by-three divideby-four input frequency LVTTL output-enable control each bank Input-to-output propagation delay: 66.7MHz 16-pin (0.150 SOIC (4.4mm) TSSOP available
Figure Configuration
DIVSEL HREF_P HREF_N OE_0
Q0_1 Q0_2 Q1_3 Q1_4 OE_1
Table Descriptions
Key: Digital Input; Input with Internal Pull-Up; Input with Internal Pull-Down; Digital Input/Output; Digital Output; Power/Ground; Active-low
Figure Block Diagram
OE_0
FS6070
15,16
TYPE
NAME HREF_P HREF_N Q0_1 Q0_2 Q1_3 Q1_4 DIVSEL OE_0 OE_1
DESCRIPTION HSTL input (true) HSTL input (complement) LVTTL clock output LVTTL clock output LVTTL clock output LVTTL clock output Divider selection control input Bank output enable control; also used with DIVSEL, OE_1 select dividers Bank output enable control; also used with DIVSEL, OE_0 select dividers 3.3V power supply Ground Differential Input Output Bank Output Bank
Q0_1 Q0_2 HREF_P HREF_N Q1_3 Q1_4 OE_1
Figure Divide-by-3, Divide-by-4 Timing
HREF_N HREF_P Q0_1:2, Q1_3:4 (divide Q0_1:2, Q1_3:4 (divide tpHL tpLH tpHL tpLH
FS6070
This document contains information preproduction product. Specifications information herein subject change without notice.
ISO9001 QS9000
10.31.00
FS6070-01
HSTL LVTTL Fanout Buffer
Preliminary Information
October 2000
Electrical Specifications
Table Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. These conditions represent stress rating only, functional operation device these other conditions above operational limits noted this specification implied. Exposure maximum rating conditions extended conditions affect device performance, functionality, reliability.
PARAMETER Supply Voltage (VSS ground) Input Voltage, Output Voltage, Input Clamp Current, VDD) Output Clamp Current, VDD) Storage Temperature Range (non-condensing) Ambient Temperature Range, Under Bias Junction Temperature Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7)
SYMBOL
MIN. VSS-0.5 VSS-0.5 VSS-0.5
MAX. VDD+0.5 VDD+0.5
UNITS
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting loss functionality performance occur this device subjected high-energy electrostatic discharge.
Table Operating Conditions
PARAMETER Supply Voltage Operating Temperature Range Load Capacitance Reference Frequency Range Input Signal Edge Rate Input Duty Cycle Input High-Level Voltage Input Low-Level Voltage Input Differential Cross Point Voltage Required HSTL signalling parameters 0.68 SYMBOL fHREF Q0_1:2, Q1_3:4 30pF 0.90 CONDITIONS/DESCRIPTION MIN. 3.135 TYP. MAX. 3.465 UNITS V/ns
ISO9001 QS9000
FS6070-01
HSTL LVTTL Fanout Buffer
Preliminary Information
October 2000
Table Electrical Specifications
Unless otherwise stated, power supplies 3.465V, load output, ambient temperature range 70°C. Parameters denoted with asterisk represent nominal characterization data currently production tested specific limits. characterization data typical. Negative currents indicate current flows device.
PARAMETER Overall Supply Current, Dynamic, with Loaded Outputs Supply Current, Static HSTL Reference Input (HREF_P, HREF_N) High-Level Input Voltage Low-Level Input Voltage Differential Cross Point Voltage Input Leakage Current
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
fHREF 200.0MHz, fOUT 66.67MHz (divide-by-3) supplies 3.465V fHREF 200.0MHz, fOUT 50.00MHz (divide-by-4); supplies 3.465V
IDDs
HREF stopped either high
Table proper HSTL signal input levels
VSS-0.3
VDD+0.3
LVTTL Digital Inputs (OE_0, OE_1, DIVSEL) High-Level Input Voltage Low-Level Input Voltage Input Leakage Current LVTTL Clock Outputs (Q0_1:2, Q1_3:4) High Level Output Source Current Level Output Sink Current Output Impedance Tristate Output Current Short Circuit Output Source Current Short Circuit Output Sink Current IOSH IOSL shorted 30s, max. 3.3V; shorted 30s, max. 3.135V, 1.0V 3.465V, 3.135V 3.135V, 1.95V 3.465V, 0.4V Measured 1.65V, output driving Measured 1.65V, output driving high VSS-0.3 VDD+0.3
ISO9001 QS9000
FS6070-01
HSTL LVTTL Fanout Buffer
Preliminary Information Table Timing Specifications
Unless otherwise stated, power supplies 3.465V, load output, ambient temperature range 25°C. Parameters denoted with asterisk represent nominal characterization data currently production tested specific limits. characterization data typical.
October 2000
PARAMETER Overall Propagation Delay Output Tristate Enable Delay Output Tristate Disable Delay
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
tpLH, tpHL tDZL, tDZH tDLZ, tDHZ
LVTTL Clock Outputs (Q0_1:2, Q1_3:4) Duty Cycle Output Skew Rise Time Fall Time tsk(o) Ratio high pulse width clock period, measured divide divide 50.7 49.5
clock output relative another 1.5V, with both outputs same frequency, 30pF Measured 0.4V 2.4V; 10pF Measured 0.4V 2.4V; 30pF Measured 2.4V 0.4V; 10pF Measured 2.4V 0.4V; 30pF
Table Clock Outputs
Voltage
0.000 0.165 0.330 0.495 0.660 0.825 0.990 1.155 1.320 1.485 1.650 1.815 1.980 2.145 2.310 2.475 2.640 2.805 2.970 3.135 3.300 3.465
Drive Current (mA) MIN.
10.0 19.1 27.1 34.2 40.4 45.6 50.0 53.5 56.2 58.0 59.2 59.9 60.5 60.9 61.2 61.4 61.7 61.8 62.0
MAX.
24.2 45.9 65.2 82.3 97.2 110.1 121.1 130.2 137.1 141.7 144.2 145.6 146.5 147.2 147.7 148.2 148.5 148.8 149.1 149.4 149.6
Voltage
0.000 0.165 0.330 0.495 0.660 0.825 0.990 1.155 1.320 1.485 1.650 1.815 1.980 2.145 2.310 2.475 2.640 2.805 2.970 3.135 3.300 3.465
High Drive Current (mA) MIN.
-45.5 -45.2 -44.9 -44.5 -44.2 -43.8 -43.3 -42.8 -42.1 -41.0 -39.5 -37.4 -34.7 -31.5 -27.7 -23.4 -18.4 -12.9 -6.7
MAX.
-132.2 -131.4 -130.5 -129.5 -128.4 -127.2 -125.8 -124.1 -122.1 -119.5 -116.1 -111.7 -106.1 -99.3 -91.4 -82.2 -71.8 -60.1 -47.1 -32.8 -17.1
Output Current (mA)
-100 -125 -150
Output Voltage
Data this table represents nominal characterization data only
ISO9001 QS9000
FS6070-01
HSTL LVTTL Fanout Buffer
Preliminary Information
October 2000
Package Information
Table 16-pin SOIC (0.150") Package Dimensions
DIMENSIONS INCHES MIN. 0.061 0.004 0.055 0.013 0.0075 0.386 0.150 0.230 0.010 0.016 MAX. 0.068 0.0098 0.061 0.019 0.0098 0.393 0.157 0.244 0.016 0.035 MILLIMETERS MIN. 1.55 0.102 1.40 0.33 0.191 9.80 3.81 5.84 0.25 0.41 MAX. 1.73
0.249 1.55 0.49 0.249 9.98 3.99 6.20 0.41 0.89
RADII: 0.005" 0.01"
typ.
SEATING PLANE
0.050
1.27
BASE PLANE
Table 16-pin SOIC (0.150") Package Characteristics
PARAMETER Thermal Impedance, Junction Free-Air Lead Inductance, Self Lead Inductance, Mutual Lead Capacitance, Bulk SYMBOL CONDITIONS/DESCRIPTION flow Corner lead Center lead lead adjacent lead lead TYP. UNITS °C/W
ISO9001 QS9000
FS6070-01
HSTL LVTTL Fanout Buffer
Preliminary Information
October 2000
Package Information
Table 16-pin TSSOP (4.4mm) Package Dimensions
DIMENSIONS INCHES MIN. 0.002 0.0315 0.0075 0.0035 0.193 0.169 0.0079 0.0177 MAX. 0.0472 0.006 0.041 0.0118 0.0079 0.201 0.177 0.0295 MILLIMETERS MIN. 0.05 0.80 0.19 0.09 4.90 4.30 0.20 0.45 MAX. 1.20 0.15 1.05 0.30 0.20 5.10 4.50 0.75
BASE PLANE AMERICAN MICROSYSTEMS, INC.
0.252 0.0256
6.40
0.65
SEATING PLANE
Table 16-pin TSSOP (4.4mm) Package Characteristics
PARAMETER Thermal Impedance, Junction Free-Air Lead Inductance, Self SYMBOL Lead Inductance, Mutual Lead Capacitance, Bulk Lead Capacitance, Mutual CONDITIONS/DESCRIPTION flow Corner lead plus wire Center lead plus wire Corner lead plus wire, first adjacent lead Center lead plus wire, first adjacent lead Corner lead plus wire, next adjacent lead Center lead plus wire, next adjacent lead corner lead plus wire center lead plus wire corner lead plus wire first adjacent lead center lead plus wire first adjacent lead corner lead plus wire next adjacent lead center lead plus wire next adjacent lead TYP. 2.361 1.443 0.754 0.367 0.293 0.249 0.375 0.254 0.137 0.053 0.008 0.006 UNITS °C/W
ISO9001 QS9000
FS6070-01
HSTL LVTTL Fanout Buffer
Preliminary Information
October 2000
Ordering Information
Table Device Ordering Codes
DEVICE NUMBER ORDERING CODE 13710-801 13710-201 PACKAGE TYPE 16-pin (0.150") SOIC 16-pin (4.4mm) TSSOP OPERATING TEMPERATURE RANGE (Commercial) SHIPPING CONFIGURATION Tape Reel
FS6070-01
Revision Information
DATE 7/31/00 8/1/00 PAGE DESCRIPTION This document contains information product. Specifications information herein subject change without notice. Flipped HREF_P, HREF_N signals timing diagram, revised electrical specs. Added 16-pin TSSOP This document contains information preproduction product. Specifications information herein subject change without notice.
10/18/00
Copyright 2000 American Microsystems, Inc.
Devices sold covered warranty patent indemnification provisions appearing Terms Sale only. makes warranty, express, statutory implied description, regarding information forth herein regarding freedom described devices from patent infringement. makes warranty merchantability fitness purposes. reserves right discontinue production change specifications prices time without notice. AMI's products intended commercial applications. Applications requiring extended temperature range, unusual environmental requirements, high reliability applications, such military, medical life-support life-sustaining equipment, specifically recommended without additional processing such applications.
American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, 83201, (208) 233-4690, (208) 234-6796, Address: http://www.amis.com E-mail: tgp@amis.com
ISO9001 QS9000

HSTL LVTTL Fanout Buffer Preliminary Information Table Clock Enab

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