LVPECL HCSL/LVTTL Motherboard Clock Driver Preliminary Informatio
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FS6058-01
LVPECL HCSL/LVTTL Motherboard Clock Driver
Preliminary Information Figure Configuration
VDD_R PECL_P PECL_N VSS_R VDD_M MREF_P MREF_N VSS_M VDD_L VSS_H VDD_H HOST_P1 HOST_N1 VSS_H
November 2000
Features
Distributes differential LVPECL reference clock differential HCSL clock pairs singleended LVTTL MREF clocks HCSL current levels controlled IREF current reference MULT_0:1 current multiplier pins Host clock frequency division selected SEL_A, SEL_B, SEL_U input signals Active-low PWR_DWN# signal disables outputs Tristate output control SEL_T facilitates board testing Available 48-pin SSOP TSSOP
Pair Pair Pair
HOST_P2 HOST_N2 VDD_H HOST_P3 HOST_N3 VSS_H
FS6058-01
Pair
HOST_P4 HOST_N4 VDD_H HOST_P5 HOST_N5 VSS_H
Figure Block Diagram
MULT_0:1 IREF PWR_DWN# SEL_T PECL_P PECL_N SEL_A SEL_B SEL_U
Divider Control Current Adjust VDD_H
VSS_L SEL_T MULT_0 MULT_1 VDD_L VSS_L SEL_A SEL_B SEL_U PWR_DWN#
Pair
HOST_P1,6 HOST_N1,6
VSS_H VDD_H
Pair
HOST_P6 HOST_N6 VDD_H IREF VSS_I VDD_I
HOST_P2:5 HOST_N2:5
VSS_H VDD_M
MREF_P MREF_N
VSS_M
FS6058
Table Divider Power-Down Control
CONTROL INPUTS PWR_ DWN# SEL_ SEL_ SEL_ SEL_ HOST_P1 HOST_N1 PECL tristate PECL PECL PECL tristate PECL PECL tristate HOST_P1 IREF HOST_N1 tristate HOST_P2 HOST_N2 PECL PECL PECL PECL PECL PECL PECL PECL tristate HOST_P2 IREF HOST_N2 tristate CLOCK OUTPUTS (MHz) HOST_P3 HOST_N3 PECL PECL PECL PECL PECL PECL PECL PECL tristate HOST_P3 IREF HOST_N3 tristate HOST_P4 HOST_N4 PECL PECL PECL PECL PECL PECL PECL PECL tristate HOST_P4 IREF HOST_N4 tristate HOST_P5 HOST_N5 PECL PECL PECL PECL PECL PECL PECL PECL tristate HOST_P5 IREF HOST_N5 tristate HOST_P6 HOST_N6 PECL tristate PECL PECL PECL tristate PECL PECL tristate HOST_P6 IREF HOST_N6 tristate MREF_P MREF_N PECL PECL PECL PECL PECL PECL PECL PECL tristate MREF_P high MREF_N
11.10.00
This document contains information product. Specifications information herein subject change without notice.
ISO9001 QS9000
FS6058-01
LVPECL HCSL/LVTTL Motherboard Clock Driver
Preliminary Information Table Descriptions
Analog Input; Analog Output; Digital Input; Input with Internal Pull-Up; Input with Internal Pull-Down; Digital Input/Output; Digital Output; Power/Ground; Active-low
November 2000
TYPE
NAME HOST_N1 HOST_P1 HOST_N2 HOST_P2 HOST_N3 HOST_P3 HOST_N4 HOST_P4 HOST_N5 HOST_P5 HOST_N6 HOST_P6 IREF MREF_N MREF_P MULT_0 MULT_1 PECL_N PECL_P PWR_DWN# SEL_A SEL_B SEL_T SEL_U VDD_H VDD_I VDD_L VDD_M VDD_R VSS_H VSS_I VDD_L VSS_M VSS_R Differential output pair Differential output pair Differential output pair Differential output pair Differential output pair Differential output pair Outside Pair Outside Pair
DESCRIPTION
SUPPLY
Inside Pairs
Current-steering differential current-mode (HCSL) outputs provided clocking CPU. output drive current established reference current IREF multiplying factor MULT_0:1
VDD_H
fixed precision resistor from this ground provides reference current used differential current-mode HOST clock outputs Single-ended clock (180° phase with MREF_P) provided reference clock memory clock driver Single-ended clock pair outputs reference clock memory clock driver logic setting these pins selects multiplying factor IREF reference current HOST pair outputs Differential Input LVPECL input (complementary) LVPECL input (true)
VDD_I
VDD_M
VDD_L VDD_R VDD_I
Asynchronous active-low LVTTL power-down signal forces MREF outputs low, tristates HOST_N outputs, drives HOST_P output currents 2xIREF Used conjunction with SEL_B SEL_U select desired output frequencies Used conjunction with SEL_A SEL_U select desired output frequencies Active high input tristates outputs Used conjunction with SEL_A SEL_B select desired output frequencies 3.3V core power supply 3.3V power supply differential HOST clock outputs 3.3V power supply IREF current reference input 3.3V power supply logic input pins 3.3V power supply MREF clock outputs 3.3V power supply PECL reference clock inputs Core ground Ground differential HOST clock outputs Ground IREF current reference input Ground logic input pins Ground MREF clock outputs Ground PECL inputs
VDD_L
ISO9001 QS9000
FS6058-01
LVPECL HCSL/LVTTL Motherboard Clock Driver
Preliminary Information Table HOST Buffer Clock Outputs
Output Voltage 3.30 3.14 2.97 2.81 2.64 2.48 2.31 2.14 1.98 1.81 1.65 1.48 1.32 1.15 0.99 0.82 0.66 MULTPLIER IREF IREF IREF IREF
November 2000
HOST Buffer Current Control
current supplied HOST outputs controlled parameters: value programming resistor from IREF ground (VSS), multiplier factor determined logic setting MULT_0 MULT_1 pins. HOST output current mirrored scaled copy reference current flowing through programming resistor IREF pin. voltage that appears IREF one-third voltage VDD_I pin. Therefore, reference current
VDD_I IREF
HIGH DRIVE CURRENT (mA) PRIMARY SYSTEM CONFIGURATION MIN. 0.00 -3.03 -5.66 -7.87 -9.67 -11.05 -11.98 -12.52 -12.77 -12.91 -12.99 -13.04 -13.07 -13.08 -13.09 -13.11 -13.12 -13.13 -13.13 -13.14 -13.15 TYP. 0.00 -4.22 -7.68 -10.30 -11.91 -12.56 -12.85 -13.07 -13.26 -13.42 -13.54 -13.64 -13.70 -13.73 -13.75 -13.76 -13.78 -13.79 -13.80 -13.81 -13.82 MAX. 0.00 -5.76 -9.86 -11.85 -12.45 -12.84 -13.16 -13.45 -13.72 -13.96 -14.17 -14.36 -14.52 -14.64 -14.71 -14.74 -14.76 -14.78 -14.80 -14.82 -14.83
mirrored reference current increased adding more copies mirror current together. additional current controlled logic settings MULT_0 MULT_1 pins.
Table Current Multiplier
MULT_0 MULT_1
0.49 0.33 0.16 0.00
Output Voltage
Table HOST Current Selection
PROGRAM RESISTOR
(1%) (1%) (1%) (1%) (1%) (1%) (1%) (1%)
REFERENCE CURRENT CURRENT MULTIPLIER
2.32mA 2.32mA 2.32mA 2.32mA IREF IREF IREF IREF IREF IREF IREF IREF
TRACE IMPEDANCE
OUTPUT VOLTAGE
0.71V 0.59V 0.85V 0.71V 0.56V 0.47V 0.99V 0.82V 0.75V 0.62V 0.90V 0.75V 0.60V 0.50V 1.05V 0.84V
Output Current (mA)
Data this table represents nominal characterization data only
NOTE: Shaded indicates Primary System Configuration
ISO9001 QS9000
FS6058-01
LVPECL HCSL/LVTTL Motherboard Clock Driver
Preliminary Information
November 2000
Electrical Specifications
Table Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. These conditions represent stress rating only, functional operation device these other conditions above operational limits noted this specification implied. Exposure maximum rating conditions extended conditions affect device performance, functionality, reliability.
PARAMETER Supply Voltage (VSS ground) Input Voltage, Output Voltage, Input Clamp Current, VDD) Output Clamp Current, VDD) Storage Temperature Range (non-condensing) Ambient Temperature Range, Under Bias Junction Temperature Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7)
SYMBOL
MIN. VSS-0.5 VSS-0.5 VSS-0.5
MAX. VDD+0.5 VDD+0.5
UNITS
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting loss functionality performance occur this device subjected high-energy electrostatic discharge.
Table Operating Conditions
PARAMETER SYMBOL CONDITIONS/DESCRIPTION Core (VDD) Supply Voltage Operating Temperature Range Reference Frequency Range Input Rise/Fall Time Input Duty Cycle Input High-Level Voltage Input Low-Level Voltage Load Capacitance Load Resistance Required LVPECL signalling parameters MREF_P, MREF_N HOST_P1 HOST_P6, HOST_N1 HOST_N6 2.135 1.490 2.420 1.825 Clock Buffers (VDD_H, VDD_I, VDD_M, VDD_R, VDD_L) MIN. 3.135 3.135 TYP. MAX. 3.465 3.465 UNITS
ISO9001 QS9000
FS6058-01
LVPECL HCSL/LVTTL Motherboard Clock Driver
Preliminary Information
November 2000
Table Electrical Specifications
Unless otherwise stated, power supplies 3.3V load output, ambient temperature range 70°C. Parameters denoted with asterisk represent nominal characterization data currently production tested specific limits. characterization data typical. Negative currents indicate current flows device.
PARAMETER Overall Supply Current, Dynamic, with Loaded Outputs Supply Current, Static
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
IDDs
fHOST 133MHz; supplies 3.465V, RIREF= 475, IREF PWR_DWN# low, supplies 3.465V, RIREF= 475, IREF
LVTTL Digital Inputs (PWR_DWN#, MULT_0, MULT_1, SEL_U, SEL_A, SEL_B, SEL_T) High-Level Input Voltage Low-Level Input Voltage Input Leakage Current PECL Reference Inputs (PECL_P, PECL_N) High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Current Reference (IREF) Bias Voltage Short Circuit Output Source Current load VSS-0.3 VDD+0.3
MREF_P, MREF_N Clock Outputs (Type Clock Driver) High Level Output Source Current Level Output Sink Current Output Impedance Tristate Output Current Short Circuit Output Source Current Short Circuit Output Sink Current IOSH IOSL shorted 30s, max. 3.3V; shorted 30s, max. VDD_M, VDD_R, VDD_66 3.135V, 1.0V VDD_M, VDD_R, VDD_66 3.465V, 3.135V VDD_M, VDD_R, VDD_66 3.135V, 1.95V VDD_M, VDD_R, VDD_66 3.465V, 0.4V Measured 1.65V, output driving Measured 1.65V, output driving high
HOST_P1:4, HOST_N1:4 Clock Outputs (Type Clock Buffer) Crossover Voltage High-Level Output Source Current Output Source Current Tolerance Output Impedance Tristate Output Current 33.2, 49.9, RIREF 475, IREF 0.65V, RIREF 475, IREF 0.74V, RIREF 475, IREF 3.30V, over settings Table VDD_I=3.3V±5%, over settings Table VO/IO, where 1.0V, VSS, RIREF 475, IREF 3000 12.9 14.9 %VOH %IOH
ISO9001 QS9000
FS6058-01
LVPECL HCSL/LVTTL Motherboard Clock Driver
Preliminary Information Table MCLK_P, MCLK_N Clock Outputs
Voltage High Drive Current (mA) MIN. TYP. MAX. Voltage Drive Current (mA) MIN. TYP. MAX. -132 -131 -130 -129 -127 -126 -124 -121 -117 -112 -105
November 2000
Output Current (mA)
-100 -125 -150
Output Voltage
Data this table represents nominal characterization data only
ISO9001 QS9000
FS6058-01
LVPECL HCSL/LVTTL Motherboard Clock Driver
Preliminary Information
November 2000
Table Timing Specifications
Unless otherwise stated, power supplies 3.3V, load output, ambient temperature 25°C. Parameters denoted with asterisk represent nominal characterization data currently production tested specific limits. characterization data typical. Spread spectrum modulation disabled except Rise/Fall time measurements.
PARAMETER Overall Tristate Enable Delay Tristate Disable Delay Clock Stabilization power-up)
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
tDZL, tDZH tDLZ, tDHZ tSTB
SEL_A:B=00, SEL133/100#=0 SEL_A:B=11, SEL133/100#=0 PWR_DWN#
HOST_P1:6, HOST_N1:6 Clock Outputs Duty Cycle Clock Skew Jitter, Additive Period (peak-peak) Rise Time Rise/Fall Time Matching* MREF_P, MREF_N Clock Outputs Duty Cycle Jitter, Additive Period (peak-peak) Rise Time Fall Time tj(P) Ratio high pulse width clock period, measured 1.5V From rising edge rising edge 1.5V, CL=30pF Measured 0.4V 2.4V; CL=10pF Measured 0.4V 2.4V; CL=30pF Measured 2.4V 0.4V; CL=10pF Measured 2.4V 0.4V; CL=30pF tJ(IN)+ tsk(o) tj(P) Ratio high pulse width clock period RIREF 475, IREF, RS=33.2, RP=49.9 HOST pair HOST pair RIREF 475, IREF, 33.2, 49.9 Rising edge rising edge VX,, RIREF 475, IREF, 33.2, 49.9 Rising edge rising edge VX,, RIREF 475, IREF, 33.2, 49.9 Rising edge rising edge VX,, RIREF 475, IREF, 33.2, 49.9 tJ(IN)+
ISO9001 QS9000
FS6058-01
LVPECL HCSL/LVTTL Motherboard Clock Driver
Preliminary Information
November 2000
Package Information
Table 48-pin SSOP (0.300") Package Dimensions
DIMENSIONS INCHES MIN. 0.095 0.008 0.008 0.005 0.620 0.395 0.291 0.015 0.020 MAX. 0.110 0.016 0.0135 0.010 0.630 0.420 0.299 0.025 0.040 MILLIMETERS MIN. 2.41 0.20 0.20 0.13 15.75 10.03 7.39 0.38 0.51 MAX. 2.79 0.41 0.34 0.25 16.00 10.67 7.59 0.64 1.01
0.025
0.64
SEATING PLANE
Table 48-pin SSOP (0.300") Package Characteristics
PARAMETER Thermal Impedance, Junction Free-Air Lead Inductance, Self Lead Inductance, Mutual Lead Capacitance, Bulk Lead Capacitance, Mutual SYMBOL CONDITIONS/DESCRIPTION flow Longest lead Longest lead adjacent lead Longest lead adjacent lead Longest lead Longest lead adjacent lead Longest lead adjacent lead TYP. 0.94 0.46 0.05 UNITS °C/W
ISO9001 QS9000
FS6058-01
LVPECL HCSL/LVTTL Motherboard Clock Driver
Preliminary Information
November 2000
Table 48-pin TSSOP (6.1mm) Package Dimensions
DIMENSIONS INCHES MIN. 0.002 0.0067 0.0035 0.488 0.236 0.018 0.008 MAX. 0.047 0.006 0.011 0.008 0.496 0.244 0.030 MILLIMETERS MIN. 0.05 0.17 0.09 12.40 6.00 0.45 0.20 MAX. 1.20 0.15 0.27 0.20 12.60 6.20 0.75
0.318 0.019
8.10
0.50
SEATING PLANE
Table 48-pin TSSOP (6.1mm) Package Characteristics
PARAMETER Thermal Impedance, Junction Free-Air Lead Inductance, Self Lead Inductance, Mutual Lead Capacitance, Bulk Lead Capacitance, Mutual SYMBOL CONDITIONS/DESCRIPTION flow Longest lead Longest lead adjacent lead Longest lead adjacent lead Longest lead Longest lead adjacent lead Longest lead adjacent lead TYP. 3.50 1.82 1.17 0.63 0.30 0.03 UNITS °C/W
ISO9001 QS9000
FS6058-01
LVPECL HCSL/LVTTL Motherboard Clock Driver
Preliminary Information
November 2000
Ordering Information
Table Device Ordering Codes
DEVICE NUMBER ORDERING CODE 11915-802 FS6058-01 11915-202 48-pin (6.1mm) TSSOP (Commercial) Tape Reel PACKAGE TYPE 48-pin (0.300") SSOP OPERATING TEMPERATURE RANGE (Commercial) SHIPPING CONFIGURATION Tape Reel
Revision Information
DATE 8/4/00 PAGE DESCRIPTION This document contains information product. Specifications information herein subject change without notice.
Copyright 2000 American Microsystems, Inc. Devices sold covered warranty patent indemnification provisions appearing Terms Sale only. makes warranty, express, statutory implied description, regarding information forth herein regarding freedom described devices from patent infringement. makes warranty merchantability fitness purposes. reserves right discontinue production change specifications prices time without notice. AMI's products intended commercial applications. Applications requiring extended temperature range, unusual environmental requirements, high reliability applications, such military, medical life-support life-sustaining equipment, specifically recommended without additional processing such applications. American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, 83201, (208) 233-4690, (208) 234-6796, Address: http://www.amis.com E-mail: tgp@amis.com
ISO9001 QS9000
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