1:10 HSTL SMBus Zero-Delay Clock Buffer Advance Information Figur
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FS61850-01
1:10 HSTL SMBus Zero-Delay Clock Buffer
Advance Information Figure Block Diagram
November 2000
Features
Generates bank differential 2.5V HSTL clock outputs (YP0/YN0 YP9/YN9) from differential HSTL reference clock input Meets JEDEC Standard Clock Driver Applications External feedback input (FBINP/FBINN) synchronize clock outputs reference input Operating frequency 60MHz 170MHz Tight tracking skew (spread-spectrum tolerant) Integrated series damping resistors driving point-to-point loads Serial programming interface provides tristate control over more output driver pairs Packaged 48-pin TSSOP
AVDD
SMBus Logic
FBINP FBINN
AGND
Description
FS61850 skew, jitter CMOS zero-delay phase-lock loop (PLL) clock buffer differential buffered clock outputs derived from onboard openloop PLL. aligns frequency phase output clock pairs differential reference input clock CLKP/CLKN, including feedback output clock pair that feeds back FBINP/FBINN close loop. bypassed test purposes pulling AVDD ground.
FS61850
Figure Configuration
FBOUTP FBOUTN
Table Function Table
INPUT AVDD
ZeroDelay
OUTPUT YP0YP9 YN0YN9 FBOUT FBOUT
FS61850
VDD_I AVDD AGND
FBINP FBINN FBOUTN FBOUTP
2.5V 2.5V 2.5V 2.5V
Bypass
<20MHz
ISO9001 QS9000
This document contains information preproduction product. Specifications information herein subject change without notice.
11.14.00
FS61850-01
1:10 HSTL SMBus Zero-Delay Clock Buffer
Advance Information Table Descriptions
Key: Analog Input; Analog Output; Digital Input; Input with Internal Pull-Up; Input with Internal Pull-Down; Digital Input/Output; DI-3 Three-Level Digital Input, Digital Output; Power/Ground; Active
November 2000
TYPE
NAME AVDD AGND FBINP FBINN FBOUTP FBOUTN
DESCRIPTION 2.5V power supply Test mode enable. This provides power supply internal PLL. When pulled low, bypassed output clocks directly follow input clock ground Reference clock input (true complementary) Feedback input (true complementary) Feedback output (true complementary) Serial interface clock Serial interface data input/output
Clock outputs (true complementary)
VDD_I
Ground clock outputs 2.5V power supply SMBus logic 2.5V power supply clock outputs
Device Operation
FS61850 precisely aligns frequency phase differential HSTL output clocks differential reference input CKP/CKN on-chip phaselock loop (PLL). generates low-skew, lowjitter copies reference, with outputs adjusted duty cycle. differential FBOUT clock must hardwired FBINP/FBINN pins complete loop. actively adjusts output clocks that there phase error between reference clock feedback input.
Since device uses lock output clocks input clock, there power-up stabilization time that required achieve phase lock. Note that inputs outputs 2.5V HSTL signal levels.
Bypass
When AVDD pulled low, reference clock signal bypasses muxed directly through outputs. powered down, device acts fanout buffer. Note that AVDD re-established, requires power-up stabilization time lock input clock.
ISO9001 QS9000
FS61850-01
1:10 HSTL SMBus Zero-Delay Clock Buffer
Advance Information
After last byte written, additional byte information sent device wraps around starts rewriting information contained Byte
November 2000
Programming Interface
This device supports both Block Write Block Read commands. device address
Block Read
Table Device Address
Block Write
Block Write command allows Host write several bytes data sequential registers, starting with Byte Register. shown Figure Block Write starts with seven-bit device address followed logic-low bit. According SMBus protocol, command code containing zeroes (0000 0000) byte count describing number data bytes written should issued Host after acknowledge handshake. This device, however, ignores both byte count command code. After device acknowledge byte count, data bytes written sequentially, starting with Byte Register incrementing order. acknowledge between each byte data must occur before next data byte sent.
Block Read command, shown Figure permits Host read several bytes data from sequential registers, starting default Byte Register. begin Block Read, seven-bit device address sent from Host, followed logic-high bit. Note that repeated START command required initiate Block Read. After acknowledgement byte count this device takes command transmits data beginning Byte Register. After last byte data, Host should generate "not-acknowledge," followed STOP command. Without STOP command, additional read requests after reading last byte wrap around begin rereading information contained Byte host does want receive data contained device, host should not-acknowledge last desired data byte issue STOP command next clock.
Figure Block Write
DEVICE ADDRESS BYTE COUNT DATA BYTE DATA BYTE
From Host device From device Host
7-bit Receive Device Address START Command
Command Code Acknowledge WRITE Command
Byte Count Acknowledge
Write Data Acknowledge Acknowledge
Write Data Acknowledge STOP Command
Figure Block Read
DEVICE ADDRESS BYTE COUNT DATA BYTE DATA BYTE
From Host device From device Host
7-bit Receive Device Address START Command
Byte Count Acknowledge READ Command
Read Data Acknowledge Acknowledge
Read Data Acknowledge STOP Command
ISO9001 QS9000
FS61850-01
1:10 HSTL SMBus Zero-Delay Clock Buffer
Advance Information Register Programming Table Byte Register
DESCRIPTION Control Outputs Tristated Control Outputs Tristated Default Reserved: Always write this Default Reserved: Always write this Default Reserved: Always write this Default Reserved: Always write this Default Reserved: Always write this Default Outputs Enabled Reserved: Always write this Outputs Enabled
November 2000
logic-one written valid location enables (turns assigned output clock. Likewise, logic-zero written valid location disables (turns off) assigned output clock. unused reserved register bits should cleared zero. Serial bits written this device starting with Byte proceeding higher. each byte written first, bits written descending order down
Table Byte Register
DESCRIPTION Control Outputs Tristated Control Outputs Tristated Control Outputs Tristated Control Outputs Tristated Control Outputs Tristated Control Outputs Tristated Control Outputs Tristated Control Outputs Tristated Outputs Enabled Outputs Enabled Outputs Enabled Outputs Enabled Outputs Enabled Outputs Enabled Outputs Enabled Outputs Enabled
Shaded areas indicate default settings
Shaded areas indicate default settings
ISO9001 QS9000
FS61850-01
1:10 HSTL SMBus Zero-Delay Clock Buffer
Advance Information
November 2000
Electrical Specifications
Table Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. These conditions represent stress rating only, functional operation device these other conditions above operational limits noted this specification implied. Exposure maximum rating conditions extended conditions affect device performance, functionality, reliability.
PARAMETER Supply Voltage, Clock Buffers (GND ground) Supply Voltage, Core Input Voltage, Output Voltage, Input Clamp Current, VDD) Output Clamp Current, VDD) Storage Temperature Range (non-condensing) Ambient Temperature Range, Under Bias Junction Temperature Lead Temperature (soldering, 10s) Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7)
SYMBOL AVDD
MIN. GND-0.5 GND-0.5 GND-0.5 GND-0.5
MAX. VDD+0.5 VDD+0.5
UNITS
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting loss functionality performance occur this device subjected high-energy electrostatic discharge.
Table Operating Conditions
PARAMETER Supply Voltage Ambient Operating Temperature Range SYMBOL AVDD fCLK Frequency range over which acquires lock Frequency range where timing parameter specification (over 80%) Core Outputs CONDITIONS/DESCRIPTION MIN. 0.375 TYP. MAX. -0.5 kb/s UNITS
Input Frequency (CKP CKN)
Input Duty Cycle Input Rise/Fall Time Spread-Spectrum Modulation Frequency Spread-Spectrum Modulation Index Output Load Capacitance Serial Data Transfer Rate
ISO9001 QS9000
FS61850-01
1:10 HSTL SMBus Zero-Delay Clock Buffer
Advance Information Table Electrical Specifications
Unless otherwise stated, power supplies 2.5V, load output, ambient temperature range 70°C. Parameters denoted with asterisk represent nominal characterization data currently production tested specific limits. characterization data typical. Negative currents indicate current flows device.
November 2000
PARAMETER Overall Supply Current, Dynamic, with Loaded Outputs Supply Current, Static SCL, Serial Interface High-Level Input Voltage Hysteresis Voltage Input Leakage Current Low-Level Output Sink Current (SDA) Input Low-Level Input Voltage
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
IDDL
2.7V, fCLK 170MHz 2.7V, PWRDWN# fCLK 20MHz
Vhys CL(in) Magnitude difference between input level input level 2.7V seen external clock driver 2.3V, 1.7V 2.3V, 2.2V 2.3V, 0.6V 2.3V, 0.1V 0.4V, 2.7V
1.67 GND-0.3 0.833
VDD+0.3 0.833
Differential Clock Inputs (CKP, CKN, FBINP, FBINN) Input Voltage Level Crossover Voltage Differential Voltage Input Leakage Current Input Loading Capacitance GND-0.3 VDD/2 -0.2 0.36 VDD+0.3 VDD/2 +0.2 VDD+0.6 -100 VDD/2 -0.2 Magnitude difference between output levels YP0:9, FBOUTP output levels YN0:9, FBOUTN Measured 1.25V, output driving Measured 1.25V, output driving high shorted 30s, max. 2.5V; shorted 30s, max. 0.70 VDD/2 +0.2 VDD+0.6
Differential Clock Outputs (YP0:9, YN0:9, FBOUTP, FBOUTN) High-Level Output Source Current Low-Level Output Sink Current Crossover Voltage Differential Voltage IOSH IOSL
Output Impedance Tristate Output Current Short Circuit Source Current Short Circuit Sink Current
ISO9001 QS9000
FS61850-01
1:10 HSTL SMBus Zero-Delay Clock Buffer
Advance Information
November 2000
Table Timing Specifications
Unless otherwise stated, power supplies 2.5V, load output, ambient temperature 25°C. Parameters denoted with asterisk represent nominal characterization data currently production tested specific limits. characterization data typical.
PARAMETER Overall Clock Skew, Output Output Dynamic Phase Offset Static Phase Offset Clock Stabilization Time Phase-Lock Loop Loop Bandwidth Phase Angle Phase Error Clock Outputs (1Y0:9, FBOUT) Duty Cycle Jitter, Cycle-cycle (peak-peak) Jitter, Period (peak-peak) Jitter, Half-Period (peak-peak) Rise Time Fall Time Enable Delay Disable Delay
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
tsk(o)
Measured between output pairs 15pF Spread modulation Spread modulation Does include jitter Time required achieve phase lock calculation Tracking Skew calculation Tracking Skew From rising edge rising edge FBIN -0.031 -120
-100
tj(CC) tj(P) tDLH tDHL 0.5V 2.0V; 15pF 2.0V 0.5V; 15pF PWRDWN# PWRDWN#
0.75 0.75
ISO9001 QS9000
FS61850-01
1:10 HSTL SMBus Zero-Delay Clock Buffer
Advance Information Table Serial Interface Timing Specifications
Unless otherwise stated, power supplies 2.5V, load output, ambient temperature 25°C. Parameters denoted with asterisk represent nominal characterization data currently production tested specific limits. characterization data typical.
November 2000
STANDARD MODE PARAMETER Clock frequency free time between STOP START time, START (repeated) Hold time, START time, data input Hold time, data input Output data valid from clock Rise time, data clock Fall time, data clock High time, clock time, clock time, STOP SYMBOL fSCL tBUF tsu:STA thd:STA tsu:DAT thd:DAT tsu:STO Minimum delay bridge undefined region fall-ing edge avoid unintended START STOP SDA, SDA, CONDITIONS/DESCRIPTION MIN. 1000 MAX. UNITS
Figure Timing Data
tsu:STA thd:STA tsu:STO
START
ADDRESS DATA VALID
DATA CHANGE
STOP
Figure Data Transfer Sequence
tsu:STA thd:STA thd:DAT
tsu:DAT
tsu:STO
tBUF
ISO9001 QS9000
FS61850-01
1:10 HSTL SMBus Zero-Delay Clock Buffer
Advance Information
November 2000
Package Information
Table 48-pin TSSOP (6.1mm) Package Dimensions
DIMENSIONS INCHES MIN. 0.002 0.0067 0.0035 0.488 0.236 0.018 0.008 MAX. 0.047 0.006 0.011 0.008 0.496 0.244 0.030 MILLIMETERS MIN. 0.05 0.17 0.09 12.40 6.00 0.45 0.20 MAX. 1.20 0.15 0.27 0.20 12.60 6.20 0.75
0.318 0.019
8.10 0.50
SEATING PLANE
Table 48-pin TSSOP (6.1mm) Package Characteristics
PARAMETER Thermal Impedance, Junction Free-Air Lead Inductance, Self Lead Inductance, Mutual Lead Capacitance, Bulk Lead Capacitance, Mutual SYMBOL CONDITIONS/DESCRIPTION flow Longest lead Longest lead adjacent lead Longest lead adjacent lead Longest lead Longest lead adjacent lead Longest lead adjacent lead TYP. 3.50 1.82 1.17 0.63 0.30 0.03 UNITS °C/W
ISO9001 QS9000
FS61850-01
1:10 HSTL SMBus Zero-Delay Clock Buffer
Advance Information
November 2000
Ordering Information
Table Device Ordering Codes
DEVICE NUMBER FS61850-01 ORDERING CODE PACKAGE TYPE 48-pin TSSOP (Thin Shrink Small Outline Package) OPERATING TEMPERATURE RANGE (Commercial) SHIPPING CONFIGURATION Tape Reel
13810-802
Purchase components American Microsystems, Inc., sublicensed Associated Compa2 nies conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips. Copyright 2001 American Microsystems, Inc. Devices sold covered warranty patent indemnification provisions appearing Terms Sale only. makes warranty, express, statutory implied description, regarding information forth herein regarding freedom described devices from patent infringement. makes warranty merchantability fitness purposes. reserves right discontinue production change specifications prices time without notice. AMI's products intended commercial applications. Applications requiring extended temperature range, unusual environmental requirements, high reliability applications, such military, medical life-support life-sustaining equipment, specifically recommended without additional processing such applications. American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, 83201, (208) 233-4690, (208) 234-6796, Address: http://www.amis.com E-mail: tgp@amis.com
ISO9001 QS9000
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