Motherboard Clock Generator Features Figure Block Diagram

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Motherboard Clock Generator Features Figure Block Diagram

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FS6233-01
Motherboard Clock Generator
Features
Figure Block Diagram
XOUT ISEL_0:1 IREF PWR_DWN# SS_EN# SEL133/100# SEL_A:B SSCG Control
delay
Generates clocks required single-processor platforms, including: differential current-mode Host clock pairs Three 66.67MHz 3.3V CK66 clock outputs 33.3MHz 3.3V clock outputs 3.3V Memory Reference clock outputs 48MHz 3.3V CK48 clock outputs buffered copies crystal reference Control current-mode Host clocks IREF current programming ISEL_0:1 current multiplier pins Host clock frequency selection SEL_A, SEL_B, SEL133/100# pins Active-low PWR_DWN# signal allows complete clock cycle each clock outputs then shuts down crystal oscillator, PLLs, outputs Spread-spectrum modulation (-0.5% 31.5kHz) SSCG clocks, enabled SS_EN# input Supports test mode tristate output control facilitate board testing Available 48-pin SSOP TSSOP
Crystal Oscillator
adjust
VDD_R
REF_0:1
VSS_R
VDD_H
HOST_P1:2 HOST_N1:2
VSS_H VDD_66
CK66_0:2
VSS_66 VDD_P
PCI_0:7
VSS_P VDD_M
MREF_P MREF_N
VSS_M VDD_48
CK48_0:1
VSS_48
FS6233
Figure Configuration
REF_1 ISEL_1 VDD_R REF_0 ISEL_0 VSS_R VDD_M MREF_P MREF_N VSS_M SS_EN# HOST_P1 HOST_N1 VDD_H HOST_P2 HOST_N2 VSS_H IREF PWR_DWN# VDD_66 CK66_0 CK66_1 VSS_66 CK66_2 VDD_66 VDD_48
Table Clock Parameters
CLOCK GROUP HOST_P HOST_N MREF_P MREF_N CK66 CK48 PINS 3.3V VDD_H SUPPLY VOLTAGE SUPPLY GROUP FREQ. (MHz) 133.33 100.00 66.67 50.00 66.67 33.33 48.008 14.318 PHASE SKEW 180° 180° 150ps Pair Pair 250ps 300ps
XOUT VSS_P PCI_0 PCI_1 VDD_P PCI_2 PCI_3 VSS_P PCI_4 PCI_5 VDD_P PCI_6 PCI_7 VSS_P
Pair
3.3V 3.3V 3.3V 3.3V 3.3V
VDD_M VDD_66 VDD_P VDD_48 VDD_R
FS6233-01
Pair
Table Clock Offsets
RELATION CK66 leads PHASE 1.5ns 3.5ns
PCI_8 PCI_9 VDD_P SEL133/100# VSS_48 CK48_0 SEL_A CK48_1 SEL_B
Intel Pentium registered trademarks Intel Corporation. Lexmark trademark Lexmark International, Inc. Non-linear spread spectrum modulation profile licensed under Patent 5488627, Lexmark International, Inc. American Microsystems, Inc. reserves right change detail specifications required permit improvements design products.
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FS6233-01
Motherboard Clock Generator
Table Descriptions
Key: Analog Input; Analog Output; Digital Input; Input with Internal Pull-Up; Input with Internal Pull-Down; Digital Input/Output; DI-3 Three-Level Digital Input, Digital Output; Power/Ground; Active-low
TYPE
NAME CK48_0 SEL_A CK48_1 SEL_B CK66_0:3 HOST_P1 HOST_N1 HOST_P2 HOST_N2 IREF MREF_N MREF_P PCI_0:9 PWR_DWN# REF_0
DESCRIPTION 3.3V 48MHz clock outputs, generated from non-spread latched inputs that select HOST MREF output frequency 3.3V 48MHz clock outputs, generated from non-spread latched inputs that select HOST MREF output frequency Three 3.3V 66.67MHz clock outputs, generated from spread spectrum Host clock pair pairs current-steering differential current-mode outputs. current established reference current IREF multiplying factor ISEL_0:1 Host clock pair pairs current-steering differential current-mode outputs fixed precision resistor from this ground provides reference current used differential current-mode HOST clock outputs clock (180° phase with MREF_P) pair outputs provided reference clock memory clock driver clock pair outputs provided reference clock memory clock driver 3.3V 33.3MHz clocks, lagging CK66 clock 3.5ns Asynchronous active-low LVTTL power-down signal shuts down oscillator PLL, puts clocks state. Complete clock cycles outputs will occur before shut down begins. 3.3V buffered copies crystal reference frequency clock latched inputs that select multiplying factor IREF reference current HOST pair outputs 3.3V buffered copies crystal reference frequency clock latched inputs that select multiplying factor IREF reference current HOST pair outputs Selects 133MHz (logic high) 100MHz (logic low) Host clock frequency Active spread-spectrum enable turns spread spectrum modulation 3.3V core power supply 3.3V power supply CK48 clock outputs 3.3V power supply CK66 clock outputs 3.3V power supply differential HOST clock outputs 3.3V power supply MREF clock outputs 3.3V power supply clock outputs 3.3V power supply clock output crystal oscillator Core ground Ground CK48 clock outputs Ground CK66 clock outputs Ground differential HOST clock outputs Ground MREF clock outputs Ground clock outputs Ground clock outputs crystal oscillator 14.318MHz crystal oscillator input 14.318MHz crystal oscillator output
SUPPLY VDD_48 VDD_48 VDD_66 VDD_H VDD_H VDD_M VDD_M VDD_P VDD_48
ISEL_0 REF_1
VDD_R
ISEL_1 SEL133/100# SS_EN# VDD_48 VDD_66 VDD_H VDD_M VDD_P VDD_R VSS_48 VSS_66 VSS_H VSS_M VSS_P VSS_R XOUT
VDD_R VDD_48 VDD_M VDD_R VDD_R
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Motherboard Clock Generator
Programming Information
Table Function/Clock Enable Configuration
CONTROL INPUTS PWR_ DWN#
CLOCK OUTPUTS (MHz) SEL_B HOST_P 100.00 reserved reserved tristate 133.33 reserved reserved IREF HOST_N 100.00 reserved reserved tristate 133.33 reserved reserved tristate MREF_P, MREF_N 50.00 reserved reserved tristate 66.67 reserved reserved CK66_ 66.67 reserved reserved tristate 66.67 reserved reserved PCI_ 33.33 reserved reserved tristate 33.33 reserved reserved CK48_ 48.008 reserved reserved tristate 48.008 reserved reserved 14.318 reserved reserved tristate 14.318 reserved reserved
133/100#
SEL_A
expected that Control Inputs will defined power-up will change during normal operation.
Table Synthesis Error
CLOCK HOST_P1:2, HOST_N1:2 MREF_P, MREF_N CK66 CK48
ACTUAL (MHz) 99.9963 133.3072 49.9982 66.6536 66.6642 33.3321 48.008 DEVIATION (ppm) -36.657 -195.924 -36.657 -195.924 -36.657 -36.657 +167
HOST Buffer Current Control
TARGET (MHz) 100.0000 133.3333 50.0000 66.6667 66.6667 33.3333 48.000
current supplied HOST outputs controlled parameters: value programming resistor from IREF ground (VSS), multiplier factor determined logic setting ISEL_0 ISEL_1 pins.
Current Reference
48MHz clock required +167ppm from 48.000MHz conform standards. Spread spectrum disabled
HOST output current mirrored scaled copy reference current flowing through programming resistor IREF pin. Conceptually, circuit given Figure shows mirror current generated. voltage that appears IREF one-third voltage VDD_I pin. reference current
VDD_I RIREF
Current Scaling
mirrored reference current increased adding more copies mirror current together. additional current controlled logic settings ISEL_0 ISEL_1 pins.
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Motherboard Clock Generator
Table Current Multiplier
ISEL_0 ISEL_1 MULTPLIER IREF IREF IREF IREF
Table HOST Buffer Clock Outputs
Output Voltage 3.30 3.14 2.97 2.81 2.64 2.48 HIGH DRIVE CURRENT (mA) PRIMARY SYSTEM CONFIGURATION MIN. 0.00 -3.03 -5.66 -7.87 -9.67 -11.05 -11.98 -12.52 -12.77 -12.91 -12.99 -13.04 -13.07 -13.08 -13.09 -13.11 -13.12 -13.13 -13.13 -13.14 -13.15 TYP. 0.00 -4.22 -7.68 -10.30 -11.91 -12.56 -12.85 -13.07 -13.26 -13.42 -13.54 -13.64 -13.70 -13.73 -13.75 -13.76 -13.78 -13.79 -13.80 -13.81 -13.82 MAX. 0.00 -5.76 -9.86 -11.85 -12.45 -12.84 -13.16 -13.45 -13.72 -13.96 -14.17 -14.36 -14.52 -14.64 -14.71 -14.74 -14.76 -14.78 -14.80 -14.82 -14.83
Figure Current Reference Circuit
VDD_I (3.3V)
1.1V
Additional Mirror Current Mirror Current ISEL_0:1
2.31 2.14 1.98 1.81 1.65 1.48
IREF Reference Current IREF RIREF
HOST_N
HOST_P
1.32 1.15 0.99 0.82 0.66 0.49
Table HOST Current Selection
PROGRAM RESISTOR RIREF (1%) (1%) (1%) (1%) (1%) (1%) (1%) (1%) REFERENCE CURRENT CURRENT MULTIPLIER IREF 2.32mA 2.32mA 2.32mA 2.32mA IREF IREF IREF IREF IREF IREF IREF IREF TRACE IMPEDANCE OUTPUT VOLTAGE 0.71V 0.59V 0.85V 0.71V 0.56V 0.47V 0.99V 0.82V 0.75V 0.62V 0.90V 0.75V 0.60V 0.50V 1.05V 0.84V
0.33 0.16 0.00
Output Voltage
Output Current (mA)
NOTE: Shaded indicates Primary System Configuration
Data this table represents nominal characterization data only
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Power Management
Table Latency Table
SIGNAL SIGNAL STATE Power Power Output: Device: LATENCY MIN. clocks clocks MAX. clocks clocks
PWR_DWN# signal asynchronous, active-low LVTTL input that places device power inactive state without removing power from device. internal clocks turned off, clock outputs held low. Since PWR_DWN# asynchronous, signal synchronized internally each individual clock. shown Figure falling-rising-falling edge sequence individual clock output required before that clock output disabled low. This edge sequence ensures that complete clock cycle will occur before clock stops.
PWR_ DWN#
Upon release PWR_DWN# (power-up), external circuitry should allow minimum lock before enabling clocks.
Figure PWR_DWN# Timing
Clock (internal) PWR_DWN# Clock (output) After output shuts off. Crystal Oscillator
Shaded regions Crystal Oscillator waveforms indicate that clock valid Crystal Oscillator active.
until clock valid
Dual Function Pins
Figure Programming
Termination Resistor Device Solder Pads
Several pins this device serve dual function input/output pins. During initial application device, this type functions input pin. Upon completion power-up, logic state present latched internally, converted output driver. external pull-down resistor ground required logic pull-up resistor clock output required logic high. resistor presents insignificant load output driver that should affect output clock. Note that latching logic state occurs only application chip supply voltage (VDD). logic state latched PWR_DWN# signal used power-down device with still applied.
Clock Trace
Programming Resistor
Ground Power
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Motherboard Clock Generator
Electrical Specifications
Table Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. These conditions represent stress rating only, functional operation device these other conditions above operational limits noted this specification implied. Exposure maximum rating conditions extended conditions affect device performance, functionality, reliability.
PARAMETER Supply Voltage (VSS ground) Input Voltage, Output Voltage, Input Clamp Current, VDD) Output Clamp Current, VDD) Storage Temperature Range (non-condensing) Ambient Temperature Range, Under Bias Junction Temperature Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7)
SYMBOL
MIN. VSS-0.5 VSS-0.5 VSS-0.5
MAX. VDD+0.5 VDD+0.5
UNITS
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting loss functionality performance occur this device subjected high-energy electrostatic discharge.
Table Operating Conditions
PARAMETER Supply Voltage Operating Temperature Range Crystal Resonator Frequency Crystal Resonator Load Capacitance SYMBOL fXTAL XIN, XOUT pins MREF_P, MREF_N PCI_0:9 Load Capacitance CK66_0:2 CK48_0:1 REF_0:1 Load Resistance Maximum High-Level Output Voltage HOST_P1 HOST_P2, HOST_N1 HOST_N2 HOST_P1 HOST_P2, HOST_N1 HOST_N2 CONDITIONS/DESCRIPTION Core (VDD) Clock Buffers (VDD_48, VDD_66, VDD_H, VDD_M, VDD_P, VDD_R) MIN. 3.135 3.135 14.316 13.5 14.318 TYP. MAX. 3.465 3.465 14.32 22.5 1.20 UNITS
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Motherboard Clock Generator
Table Electrical Specifications
Unless otherwise stated, power supplies 3.3V load output, ambient temperature range 70°C. Parameters denoted with asterisk represent nominal characterization data currently production tested specific limits. characterization data typical. Negative currents indicate current flows device.
PARAMETER Overall Supply Current, Dynamic, with Loaded Outputs Supply Current, Static
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
IDDs
fHOST 133MHz; supplies 3.465V, RIREF= 475, IREF PWR_DWN# low, supplies 3.465V, RIREF= 475, IREF VSS-0.3 VDD+0.3
Digital Inputs (PWR_DWN#, SEL133/100#, SS_EN#) High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Crystal Oscillator Feedback (XIN) Threshold Bias Voltage High-Level Input Current Low-Level Input Current Crystal Loading Capacitance Input Loading Capacitance Crystal Oscillator Drive (XOUT) High Level Output Source Current Level Output Sink Current Current Reference (IREF) Bias Voltage Short Circuit Output Source Current load VDD_M, VDD_66, VDD_P 3.135V, 1.0V VDD_M, VDD_66, VDD_P 3.465V, 3.135V VDD_M, VDD_66, VDD_P 3.135V, 1.95V VDD_M, VDD_66, VDD_P 3.465V, 0.4V Measured 1.65V, output driving Measured 1.65V, output driving high shorted 30s, max. 3.3V; shorted 30s, max. (XIN) 3.3V, (XIN) 3.3V -8.0 CL(xtal) CL(XIN) 3.3V seen external crystal connected XOUT seen external clock driver XOUT; unconnected 13.5 22.5
MREF_P, MREF_N, CK66_0:2, PCI_0:9 Clock Outputs (Type High Level Output Source Current Level Output Sink Current Output Impedance Tristate Output Current Short Circuit Output Source Current Short Circuit Output Sink Current IOSH IOSL
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Table Electrical Specifications, continued
Unless otherwise stated, power supplies 3.3V load output, ambient temperature range 70°C. Parameters denoted with asterisk represent nominal characterization data currently production tested specific limits. characterization data typical. Negative currents indicate current flows device.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
HOST_P1:2, HOST_N1:2 Clock Outputs (Type Crossover Voltage High-Level Output Source Current Output Source Current Tolerance Output Impedance Tristate Output Current 33.2, 49.9, RIREF 475, IREF 0.65V, RIREF 475, IREF 0.74V, RIREF 475, IREF 3.3V, over settings Table VDD_I 3.3V±5%, over settings Table VO/IO, where 1.0V, VSS, RIREF 475, IREF 3000 12.9 14.9 %VOH %IOH
REF_0 ISEL_0, REF_1 ISEL_1 Clock Driver I/O, (Type CK48_0 SEL_A, CK48_1 SEL_B Clock Driver (Type High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current (pull-up) High Level Output Source Current Level Output Sink Current Output Impedance Tristate Output Current Short Circuit Output Source Current Short Circuit Output Sink Current Output
3.3V 2.4V 0.4V 2.0V 0.8V
HOST_P HOST_N
IOSH IOSL shorted 30s, max. 3.3V; shorted 30s, max. 0.4V VDD_R, VDD_48 3.465V, 2.4V VDD_R, VDD_48 3.465V, 0.4V Measured 1.65V, output driving Measured 1.65V, output driving high Input
VSS-0.3
VDD+0.3
Figure Measurement Points
Figure Timing Diagram
3.3V 2.4V 1.5V 0.4V
Figure HOST Clock Measurement Point
Figure HOST Clock Test Point
From output under test Test node
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Motherboard Clock Generator
Table Timing Specifications
Unless otherwise stated, power supplies 3.3V, load output, ambient temperature 25°C. Parameters denoted with asterisk represent nominal characterization data currently production tested specific limits. characterization data typical. Spread spectrum modulation disabled except Rise/Fall time measurements.
PARAMETER Overall Spread Spectrum Modulation Frequency Spread Spectrum Modulation Index Clock Offset Output Tristate Enable Delay Output Tristate Disable Delay Power-up Lock Time
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
tDZL, tDZH tDLZ, tDHZ
SS_EN# SS_EN# CK66 leads 1.5V, CL=30pF 1.5V, 30pF (measured rising edges) SEL_A:B SEL133/100# SEL_A:B SEL133/100# PWR_DWN# HOST pair HOST pair RIREF 475, IREF, 33.2, 49.9 Ratio high pulse width clock period RIREF 475, IREF, RS=33.2, RP=49.9 Rising edge rising edge RIREF 475, IREF 33.2, 49.9 Measured VOH; RIREF 475, IREF 33.2, 49.9 Measured VOH; RIREF 475, IREF 33.2, 49.9 Ratio high pulse width clock period, measured 1.5V From rising edge rising edge 1.5V, CL=30pF Measured 0.4V 2.4V; CL=10pF Measured 0.4V 2.4V; CL=30pF Measured 2.4V 0.4V; CL=10pF Measured 2.4V 0.4V; CL=30pF
31.5 -0.5
HOST_P1:2, HOST_N1:2 Clock Outputs Clock Skew Duty Cycle Jitter, Period (peak-peak) Rise Time Rise/Fall Time Matching* MREF_P, MREF_N Clock Outputs Duty Cycle Jitter, Period (peak-peak) Rise Time Fall Time tj(P) tsk(o) tj(P)
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Motherboard Clock Generator
Table Timing Specifications, continued
Unless otherwise stated, power supplies 3.3V, load output, ambient temperature 25°C. Parameters denoted with asterisk represent nominal characterization data currently production tested specific limits. characterization data typical. Spread spectrum modulation disabled except Rise/Fall time measurements.
PARAMETER PCI_0:9 Clock Outputs Duty Cycle Clock Skew Jitter, Period (peak-peak) Rise Time Fall Time CK66_0:2 Clock Outputs Duty Cycle Clock Skew Jitter, Period (peak-peak) Rise Time Fall Time REF_0:1 Clock Outputs Duty Cycle Jitter, Period (peak-peak) Rise Time Fall Time CK48_0:1 Clock Outputs Duty Cycle Jitter, Period (peak-peak) Rise Time Fall Time
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
tsk(o) tj(P)
Ratio high pulse width clock period, measured 1.5V clock output relative another 1.5V From rising edge rising edge 1.5V, 30pF Measured 0.4V 2.4V; 10pF Measured 0.4V 2.4V; 30pF Measured 2.4V 0.4V; 10pF Measured 2.4V 0.4V; 30pF Ratio high pulse width clock period, measured 1.5V clock output relative another 1.5V From rising edge rising edge 1.5V, 30pF Measured 0.4V 2.4V; 10pF Measured 0.4V 2.4V; 30pF Measured 2.4V 0.4V; 10pF Measured 2.4V 0.4V; 30pF Ratio high pulse width clock period, measured 1.5V From rising edge rising edge 1.5V, 20pF Measured 0.4V 2.4V; 10pF Measured 0.4V 2.4V; 20pF Measured 2.4V 0.4V; 10pF Measured 2.4V 0.4V; 20pF Ratio high pulse width clock period, measured 1.5V From rising edge rising edge 1.5V, 20pF Measured 0.4V 2.4V; 10pF Measured 0.4V 2.4V; 20pF Measured 2.4V 0.4V; 10pF Measured 2.4V 0.4V; 20pF
tsk(o) tj(P)
tj(P)
1000
tj(P)
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Motherboard Clock Generator
Table MCLK_P, MCLK_N, PCI_0:9, CK66_0:2 Clock Outputs
Voltage High Drive Current (mA) MIN. TYP. MAX. Voltage Drive Current (mA) MIN. TYP. MAX. -132 -131 -130 Output Current (mA) -129 -127 -126 -124 -121 -117 -112 -105
-100 -125 -150
Output Voltage
Data this table represents nominal characterization data only
Table REF_0:1, CK48_0:1 Clock Outputs
Voltage High Drive Current (mA) MIN. TYP. MAX. Voltage Drive Current (mA) MIN. TYP. MAX. -102 -101 -100
Output Current (mA)
-100 -120
Output Voltage
Data this table represents nominal characterization data only
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Motherboard Clock Generator
Package Information
Table 48-pin SSOP (0.300") Package Dimensions
DIMENSIONS INCHES MIN.
0.095 0.008 0.008 0.005 0.620 0.395 0.291 0.015 0.020
MILLIMETERS MIN.
2.41 0.20 0.20 0.13 15.75 10.03 7.39 0.38 0.51
MAX.
0.110 0.016 0.0135 0.010 0.630 0.420 0.299 0.025 0.040
MAX.
2.79 0.41 0.34 0.25 16.00 10.67 7.59 0.64 1.01
0.025
0.64
SEATING PLANE
Table 48-pin SSOP (0.300") Package Characteristics
PARAMETER
Thermal Impedance, Junction Free-Air Lead Inductance, Self Lead Inductance, Mutual Lead Capacitance, Bulk Lead Capacitance, Mutual
SYMBOL
CONDITIONS/DESCRIPTION
flow Longest lead Longest lead adjacent lead Longest lead adjacent lead Longest lead Longest lead adjacent lead Longest lead adjacent lead
TYP.
0.94 0.46 0.05
UNITS
°C/W
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Motherboard Clock Generator
Table 48-pin TSSOP (6.1mm) Package Dimensions
DIMENSIONS INCHES MIN.
0.002 0.0067 0.0035 0.488 0.236 0.018 0.008
MILLIMETERS MIN.
0.05 0.17 0.09 12.40 6.00 0.45 0.20
MAX.
0.047 0.006 0.011 0.008 0.496 0.244 0.030
MAX.
1.20 0.15 0.27 0.20 12.60 6.20 0.75
0.318 0.019
8.10 0.50
SEATING PLANE
Table 48-pin TSSOP (6.1mm) Package Characteristics
PARAMETER
Thermal Impedance, Junction Free-Air Lead Inductance, Self Lead Inductance, Mutual Lead Capacitance, Bulk Lead Capacitance, Mutual
SYMBOL
CONDITIONS/DESCRIPTION
flow Longest lead Longest lead adjacent lead Longest lead adjacent lead Longest lead Longest lead adjacent lead Longest lead adjacent lead
TYP.
3.50 1.82 1.17 0.63 0.30 0.03
UNITS
°C/W
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Motherboard Clock Generator
Ordering Information
Table Device Ordering Codes
DEVICE NUMBER ORDERING CODE 11995-202
FS6233-01
PACKAGE TYPE
48-pin (0.300") SSOP
OPERATING TEMPERATURE RANGE
SHIPPING CONFIGURATION
Tape Reel
11995-212 11995-203 11995-213
48-pin (6.1mm) TSSOP
(Commercial)
Tubes Tape Reel Tubes
Copyright 2000 American Microsystems, Inc.
Devices sold covered warranty patent indemnification provisions appearing Terms Sale only. makes warranty, express, statutory implied description, regarding information forth herein regarding freedom described devices from patent infringement. makes warranty merchantability fitness purposes. reserves right discontinue production change specifications prices time without notice. AMI's products intended commercial applications. Applications requiring extended temperature range, unusual environmental requirements, high reliability applications, such military, medical life-support life-sustaining equipment, specifically recommended without additional processing such applications.
American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, 83201, (208) 233-4690, (208) 234-6796, Address: http://www.amis.com E-mail: tgp@amis.com
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Motherboard Clock Generator Features Figure Block Diagram

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