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3URJUDPPDEOH / LQH / RFN &ORFN HQHUDWRU , &

Frequency Synthesis Line-Locked and Genlock Applications Clock Multiplication Telecom Jitter Attenuation

3URJUDPPDEOH / LQH / RFN &ORFN HQHUDWRU , &
April 1999
Features
Applications
Complete programmable control via I C -bus Selectable CMOS or PECL compatible outputs External feedback loop capability allows genlocking Tunable VCXO loop for jitter attenuation Commercial (FS6131-01) and industrial (FS6131-01i) temperature versions available
Frequency Synthesis Line-Locked and Genlock Applications Clock Multiplication Telecom Jitter Attenuation
Figure 1: Pin Configuration
SCL SDA ADDR VSS XIN XOUT XTUNE VDD
Description
CLKN CLKP VDD FBK REF VSS EXTLF LOCK / IPRG
The FS6131-01 is a monolithic CMOS clock generator / regenerator IC designed to minimize cost and compo2 nent count in a variety of electronic systems. Via the I Cbus interface, the FS6131-01 can be adapted to many clock generation requirements. The ability to tune the on-board voltage-controlled crystal oscillator (VCXO), the length of the Reference and Feedback Dividers, their granularity, and the flexibility of the Post Divider make the FS6131-01 the most flexible stand-alone phase-locked loop (PLL) clock generator available.
FS6131
16-pin 0.150" SOIC
Figure 2: Block Diagram
LFTC CLF CLP XLROM2:0 XLPDEN, XLSWAP
XTUNE
(optional)
XCT3:0, XLVTEN
Control ROM VCXO Divider
CRYSTAL LOOP
XLCP1:0
XIN VCXO XOUT
(optional)
Internal Loop Filter
0 EXTLF STAT1:0 1
PhaseFrequency Detector
EXTLF
(optional)
Charge Pump
Lock Detect
REFDIV11:0
CMOS 1
0 POST31:0 POST21:0 POST11:0
LOCK / IPRG
(optional)
0 1 REFDSRC
(fREF)
Reference Divider
MLCP1:0 0 PDREF UP
VCOSPD, OSCTYPE
1 0 PDFBK
PhaseFrequency Detector
Charge Pump
Voltage Controlled Oscillator
Clock Gobbler
OUTMUX1:0
Post Divider (NPx) CMOS / PECL Output
(fCLK)
ADDR Feedback Divider (NF) SCL SDA I2C Interface Registers
FBKDIV13:0
11 01 10 00 FBKDSRC1:0
(fVCO)
MAIN LOOP
FS6131
I2C is a licensed trademark of Philips Electronics, N.V. Windows and Windows NT are registered trademarks of Microsoft Corporation. American Microsystems, Inc. reserves the right to change detail specifications as may be required to permit improvements in the design of its products.
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April 1999
Table 1: Pin Descriptions
NAME SCL SDA ADDR VSS XIN XOUT XTUNE VDD LOCK / IPRG EXTLF VSS REF FBK VDD CLKP CLKN
DESCRIPTION Serial Interface Clock (requires an external pull-up) Serial Interface Data Input / Output (requires an external pull-up) Address Select Bit (see Section 5.2.1) Ground VCXO Feedback VCXO Drive VCXO Tune Power Supply (+5V) Lock Indicator / PECL Current Drive Programming External Loop Filter Ground Reference Frequency Input Feedback Input Power Supply (+5V) Differential Clock Output (+) Differential Clock Output (-)
Functional Block Description
Main Loop PLL
The PFD will drive the VCO up or down in frequency until the divided reference frequency and the divided VCO frequency appearing at the inputs of the PFD are equal. The input / output relationship between the reference frequency and the VCO frequency is
The Main Loop Phase Locked Loop (ML-PLL) is a standard phase- and frequency- locked loop architecture. As shown in Figure 2, the ML-PLL consists of a Reference Divider, a Phase-Frequency Detector (PFD), a charge pump, an internal loop filter, a Voltage-Controlled Oscillator (VCO), a Feedback Divider, and a Post Divider. During operation, the reference frequency (fREF), generated by either the on-board crystal oscillator or an external frequency source, is first reduced by the Reference Divider. The integer value that the frequency is divided by is called the modulus, and is denoted as NR for the Reference Divider. The divided reference is then fed into the PFD. The PFD controls the frequency of the VCO (fVCO) through the charge pump and loop filter. The VCO provides a high-speed, low noise, continuously variable frequency clock source for the ML-PLL. The output of the VCO is fed back to the PFD through the Feedback Divider (the modulus is denoted by NF) to close the loop.
If the VCO frequency is used as the PLL output frequency (fCLK) then the basic PLL equation can be rewritten as
4.1.1 Reference Divider The Reference Divider is designed for low phase jitter. The divider accepts either the output of either the Crystal Loop (the VCXO output) or an external reference frequency, and provides a divided-down frequency to the PFD. The Reference Divider is a 12-bit divider, and can be programmed for any modulus from 1 to 4095. See both Table 3 and Table 8 for additional programming information.
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April 1999
4.1.2 Feedback Divider The Feedback Divider is based on a dual-modulus prescaler technique. The technique allows the same granularity as a fully programmable feedback divider, while still allowing the programmable portion to operate at low speed. A high-speed pre-divider (also called a prescaler) is placed between the VCO and the programmable Feedback Divider because of the high speeds at which the VCO can operate. The dual-modulus technique insures reliable operation at any speed that the VCO can achieve and reduces the overall power consumption of the divider. For example, a fixed divide-by-eight could be used in the Feedback Divider. Unfortunately, a divide-by-eight would limit the effective modulus of the feedback divider path to multiples of eight. The limitation would restrict the ability of the PLL to achieve a desired input-frequency-tooutput-frequency ratio without making both the Reference and Feedback Divider values comparatively large. Large divider moduli are generally undesirable due to increased phase jitter.
4.1.3 Feedback Divider Programming The requirement that MA means that the Feedback Divider can only be programmed for certain values below a divider modulus of 56. The selection of divider values is listed in Table 2. If the desired Feedback Divider is less than 56, find the divider value in the table. Follow the column up to find the A-counter program value. Follow the row to the left to find the M-counter value. Above a modulus of 56, the Feedback Divider can be programmed to any value up to 16383. See both Table 3 and Table 8 for additional programming information.
Table 2: Feedback Modulus Below 56
M-COUNTER: FBKDIV13:3 00000000001 00000000010 00000000011 A-COUNTER: FBKDIV2:0 000 8 16 24 32 40 48 56 001 9 17 25 33 41 49 57 010 18 26 34 42 50 58 011 27 35 43 51 59 100 36 44 52 60 101 45 53 61 110 54 62 111 63
Figure 3: Feedback Divider
DualModulus Prescaler M Counter
FEEDBACK DIVIDER MODULUS
A Counter
4.1.4 Post Divider The Post Divider consists of three individually programmable dividers, as shown in Figure 4.
Figure 4: Post Divider
POST11:0 POST21:0 POST31:0
Post Divider 1 (NP1)
Post Divider 2 (NP2)
POST DIVIDER (NPx)
Post Divider 3 (NP3)
The moduli of the individual dividers are denoted as NP1, NP2, and NP3, and together they make up the array modulus NPx.
3URJUDPPDEOH / LQH / RFN &ORFN HQHUDWRU , &
April 1999 The Post Divider performs several useful functions. First, it allows the VCO to be operated in a narrower range of speeds compared to the variety of output clock speeds that the device is required to generate. Second, it changes the basic PLL equation to
The extra integer in the denominator permits more flexibility in the programming of the loop for many applications where frequencies must be achieved exactly. Note that a nominal 50 / 50 duty factor is preserved for selections which have an odd modulus.
4.2.1 Clock Gobbler (Phase Adjust) The Clock Gobbler circuit takes advantage of the unknown relationship between input and output clocks to permit the adjustment of the CLKP / CLKN output clock phase relative to the REF input. The Clock Gobbler circuit removes a VCO clock pulse before the pulse clocks the Post Divider. In this way, the phase of the output clock can be slipped until the output phase is aligned with the input clock phase. To adjust the phase relationship, switch the Feedback Divider source to the Post Divider input via the FBKDSRC bit, and toggle the GBL register bit. The Clock Gobbler output clock is delayed by one VCO clock period for each transition of the GBL bit from zero to one. 4.2.2 Phase Alignment To maintain a fixed phase relation between input and output clocks, the Post Divider must be placed inside the feedback loop. The source for the Feedback Divider is obtained from the output of the Post Divider via the FBKDSRC switch. In addition, the Feedback Divider must be dividing at a multiple of the Post Divider.
Phase Adjust and Sampling
In line-locked or genlocked applications, it is necessary to know the exact phase relation of the output clock relative to the input clock. Since the VCO is included within the feedback loop in a simple PLL structure, the VCO output is exactly phase aligned with the input clock. Every cycle of the input clock equals NR / NF cycles of the VCO clock.
Figure 5: Simple PLL
Reference Divider (NR)
Figure 7: Aligned I / O Phase
Phase Frequency Detect VCO
Reference Divider (NR)
fIN fOUT
Phase Frequency Detect
Post Divider (NF)
Feedback Divider (NF)
fIN fOUT
Feedback Divider (NF)
The addition of a Post Divider, while adding flexibility, makes the phase relation between the input and output clock unknown because the Post Divider is outside the feedback loop.
Figure 6: PLL with Post Divider
Reference Divider (NR) Phase Frequency Detect VCO Post Divider (NF)
fIN fVCO fOUT
Feedback Divider (NF)
4.2.3 Phase Sampling and Initial Alignment However, the ability to adjust the phase is useless without knowing the initial relation between output and input phase. To aid in the initial synchronization of the output phase to input phase, a Phase Align "flag" makes a transition (zero to one or one to zero) when the output clock phase becomes aligned with the feedback source phase. The feedback source clock is, by definition, locked to the input clock phase. First, the FS6131 is used to sample the output clock with the feedback source clock and set / clear the Phase Align flag when the two clocks match to within a feedback source clock period. Then, the Clock Gobbler is used to delay the output phase relative to the input phase one VCO clock at a time until a transition on the flag occurs. When a transition occurs, the output and input clocks are phase aligned.
3URJUDPPDEOH / LQH / RFN &ORFN HQHUDWRU , &
April 1999 To enter this mode, set STAT1 to one and clear STAT0 to zero. If the CMOS bit is set to one, the LOCK / IPRG pin can display the flag. The flag is always available under software control by reading back the STAT1 bit, which will be overwritten by the flag in this mode. The VCO transfer function (in rad / s, and accounting for the phase integration that occurs in the VCO) is:
The transfer function of the Feedback Divider is:
4.2.4 Feedback Divider Monitoring The Feedback Divider clock can be brought out the LOCK / IPRG pin independent of the output clock to allow monitoring of the Feedback Divider clock. To enter this mode, set both the STAT1 and STAT0 bits to one. The CMOS bit must also be set to one to enable the LOCK / IPRG pin as an output.
Finally, the sampling effect that occurs in the Phase Detector is accounted for by:
Loop Gain Analysis
For applications where an external loop filter is required, the following analysis example can be used to determine loop gain and stability. The loop gain of a PLL is the product of all of the gains within the loop. Establish the basic operating parameters: Set the charge pump current:
The loop gain of the PLL is:
Set the loop filter values:
Set the VCO gain (VCOSPD): Set the Feedback Divider:
Amplitude
I chgpump 2
0.01 0.1kHz
10kHz
100kHz
The transfer function of the loop filter is (in V / A):
Frequency (fi)
The loop phase angle is:
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April 1999
Voltage-Controlled Crystal Oscillator
Figure 9: Loop Phase vs. Frequency
0.1kHz
10kHz
100kHz
Frequency (fi)
A Nyquist plot of gain vs. amplitude is shown below.
Figure 10: Loop Nyquist Plot
Amplitude
The VCXO provides a tunable, low-jitter frequency reference for the rest of the FS6131 system components. Loading capacitance for the crystal is internal to the device. No external components (other than the resonator itself) are required for operation of the VCXO. The resonator loading capacitance is adjustable under register control. This feature permits factory coarse tuning of inexpensive resonators to the necessary precision for digital video applications. Continuous fine-tuning of the VCXO frequency is accomplished by varying the voltage on the XTUNE pin. The total change (from one extreme to the other) in effective loading capacitance is 1.5pF nominal, and the effect is shown in Figure 11. The oscillator operates the crystal resonator in the parallelresonant mode. Crystal warping, or the "pulling" of the crystal oscillation frequency, is accomplished by altering the effective load capacitance presented to the crystal by the oscillator circuit. The actual amount that changing the load capacitance alters the oscillator frequency will be dependent on the characteristics of the crystal as well as the oscillator circuit itself. The motional capacitance of the crystal (usually referred to by crystal manufacturers as C1), the static capacitance of the crystal (C0), and the load capacitance (CL) of the oscillator determine the warping capability of the crystal in the oscillator circuit. A simple formula to determine the total warping capability of a crystal is
Phase
Gain Margin
Phase Margin
Phase
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April 1999
4.4.1 VCXO Tuning The VCXO may be coarse tuned by a programmable adjustment of the crystal load capacitance via the XCT3:0 control bits. See Table 11 for the control code and the associated loading capacitance. The actual amount of frequency warping caused by the tuning capacitance will depend on the crystal used. The VCXO tuning capacitance includes an external 6pF load capacitance (12pF from the XIN pin to ground and 12pF from the XOUT pin to ground). The fine tuning capability of the VCXO can be enabled by setting the XLVTEN bit to a one, or disabled by setting it to a zero. Figure 11 shows the typical effect of the coarse and fine tuning mechanisms. The total coarse tune range is about 350ppm. The difference in VCXO frequency in parts per million (ppm) is shown as the fine tuning voltage on the XTUNE pin varies from 0V to 5V. Note that as the crystal load capacitance is increased the VCXO frequency is pulled somewhat less with each coarse step, and the fine tuning range decreases. The fine tuning range always overlaps a few coarse tuning ranges, eliminating the possibility of holes in the VCXO response. The different crystal warping characteristics may change the scaling on the Y-axis, but not the overall characteristic of the curves.
Crystal Loop
The Crystal Loop is designed to attenuate the jitter on a highly jittered, low-Q, low frequency reference. The Crystal Loop can also maintain a constant frequency output into the Main Loop if the low frequency reference is intermittent. The Crystal Loop consists of a Voltage-Controllable Crystal Oscillator (VCXO), a divider, a PFD, and a charge pump that tunes the VCXO to a frequency reference. The frequency reference is phase-locked to the divided frequency of an external, high-Q, jitter-free crystal, thereby locking the VCXO to the reference frequency. The VCXO can continue to run off the crystal even if the frequency reference becomes intermittent.
Figure 11: VCXO Coarse and Fine Tuning
VCXO Range (ppm) vs. XTUNE Voltage (V)
4.5.1 Locking to an External Frequency Source When the Crystal Loop is synchronized to an external frequency source, the FS6131 can monitor the Crystal Loop and detect if the loop unlocks from the external source. The Crystal Loop tries to drive to zero frequency if the external source is dropped, and sets a Lock Status error flag. The Crystal Loop can also detect if the VCXO has dropped out of the Fine Tune range, requiring a change to the Coarse Tune. The Lock Status also latches the direction the loop went out of range (high or low) when the loop became unlocked.
VCXO Range (ppm)
Coarse Tune Setting XCT3:0
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Differential Output Stage
Figure 12: IPRG to CLKP / CLKN Current
IPRG Input Current (mA)
Connecting the FS6131 to an External Reference Frequency
CLKP / CLKN PECL Output Current (mA)
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April 1999
I C-bus Control Interface
This device is a read / write slave device 2 meeting all Philips I C-bus specifications except a "general call." The bus has to be controlled by a master device that generates the serial clock SCL, controls bus access, and generates the START and STOP conditions while the device works as a slave. Both master and slave can operate as a transmitter or receiver, but the master device determines which mode is activated. A device that sends data onto the bus is defined as the transmitter, and a device receiving data as the receiver. 2 I C-bus logic levels noted herein are based on a percentage of the power supply (VDD). A logic-one corresponds to a nominal voltage of VDD, while a logic-zero corresponds to ground (VSS).
Each data transfer is initiated by a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is determined by the master device, and can continue indefinitely. However, data that is overwritten to the device after the first eight bytes will overflow into the first register, then the second, and so on, in a first-in, firstoverwritten fashion.
Bus Conditions
Data transfer on the bus can only be initiated when the bus is not busy. During the data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is high. Changes in the data line while the clock line is high will be interpreted by the device as a START or STOP condition. The following bus conditions are defined 2 by the I C-bus protocol.
5.1.5 Acknowledge When addressed, the receiving device is required to generate an Acknowledge after each byte is received. The master device must generate an extra clock pulse to coincide with the Acknowledge bit. The acknowledging device must pull the SDA line low during the high period of the master acknowledge clock pulse. Setup and hold times must be taken into account. The master must signal an end of data to the slave by not generating and acknowledge bit on the last byte that has been read (clocked) out of the slave. In this case, the slave must leave the SDA line high to enable the master to generate a STOP condition.
I2C-bus Operation
5.1.1 Not Busy Both the data (SDA) and clock (SCL) lines remain high to indicate the bus is not busy. 5.1.2 START Data Transfer A high to low transition of the SDA line while the SCL input is high indicates a START condition. All commands to the device must be preceded by a START condition. 5.1.3 STOP Data Transfer A low to high transition of the SDA line while SCL is held high indicates a STOP condition. All commands to the device must be followed by a STOP condition. 5.1.4 Data Valid The state of the SDA line represents valid data if the SDA line is stable for the duration of the high period of the SCL line after a START condition occurs. The data on the SDA line must be changed only during the low period of the SCL signal. There is one clock pulse per data bit.
All programmable registers can be accessed randomly or sequentially via this bi-directional two wire digital interface. The crystal oscillator does not have to run for communication to occur. 2 The device accepts the following I C-bus commands:
5.2.1 Slave Address After generating a START condition, the bus master broadcasts a seven-bit slave address followed by a R / W bit. The address of the device is:
where X is controlled by the logic level at the ADDR pin. The variable ADDR bit allows two different FS6131 devices to exist on the same bus. Note that every device on 2 an I C-bus must have a unique address to avoid bus conflicts. The default address sets A2 to 0 via the pulldown on the ADDR pin.
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April 1999
3URJUDPPDEOH / LQH / RFN &ORFN HQHUDWRU , &
April 1999
Figure 13: Random Register Write Procedure
S DEVICE ADDRESS W A REGISTER ADDRESS A DATA A P
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From bus host to device
Data Acknowledge STOP Condition Acknowledge From device to bus host
Figure 14: Random Register Read Procedure
S DEVICE ADDRESS W A REGISTER ADDRESS A S DEVICE ADDRESS R A DATA A P
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From bus host to device
7-bit Receive Device Address Repeat START Acknowledge From device to bus host
Data Acknowledge READ Command STOP Condition NO Acknowledge
Figure 15: Sequential Register Write Procedure
S DEVICE ADDRESS W A REGISTER ADDRESS A DATA A DATA A DATA A P
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From bus host to device
Data Acknowledge
Data Acknowledge Acknowledge
Data Acknowledge STOP Command
From device to bus host
Figure 16: Sequential Register Read Procedure
S DEVICE ADDRESS W A REGISTER ADDRESS A S DEVICE ADDRESS R A DATA A DATA A P
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From bus host to device
7-bit Receive Device Address Repeat START Acknowledge From device to bus host
Data Acknowledge READ Command Acknowledge
Data NO Acknowledge STOP Command
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April 1999
Programming Information
All register bits are cleared to zero on power-up. All register bits may be read back as written except STAT1 (Bit 63).
Table 3: Register Map
ADDRESS BIT 7 STAT1
(Bit 63)
BIT 6 STAT0
(Bit 62)
BIT 5 XLVTEN
(Bit 61)
BIT 4 CMOS
(Bit 60)
BIT 3 XCT3
(Bit 59)
BIT 2 XCT2
(Bit 58)
BIT 1 XCT1
(Bit 57)
BIT 0 XCT0
(Bit 56)
BYTE 7
XLPDEN
(Bit 55)
XLSWAP
(Bit 54)
XLCP1
(Bit 53)
XLCP0
(Bit 52)
XLROM2
(Bit 51)
XLROM1
(Bit 50)
XLROM0
(Bit 49)
(Bit 48)
BYTE 6
OUTMUX1
(Bit 47)
OUTMUX0
(Bit 46)
OSCTYPE
(Bit 45)
VCOSPD
(Bit 44)
(Bit 43)
EXTLF
(Bit 42)
MLCP1
(Bit 41)
MLCP0
(Bit 40)
BYTE 5
FBKDSRC1
(Bit 39)
FBKDSRC0
(Bit 38)
FBKDIV13
(Bit 37)
FBKDIV12
(Bit 36)
FBKDIV11
(Bit 35)
FBKDIV10
(Bit 34)
FBKDIV9
(Bit 33)
FBKDIV8
(Bit 32)
BYTE 4
FBKDIV7
(Bit 31)
FBKDIV6
(Bit 30)
FBKDIV5
(Bit 29)
FBKDIV4
(Bit 28)
FBKDIV3
(Bit 27)
FBKDIV2
(Bit 26)
FBKDIV1
(Bit 25)
FBKDIV0
(Bit 24)
BYTE 3
32 M Counter
2 A Counter - See Table 2
POST31
(Bit 21)
POST31
(Bit 20)
POST21
(Bit 19)
POST20
(Bit 18)
POST11
(Bit 17)
POST10
(Bit 16)
BYTE 2
Reserved (0)
PDFBK
(Bit 15)
PDREF
(Bit 14)
(Bit 13)
REFDSRC
(Bit 12)
REFDIV11
(Bit 11)
REFDIV10
(Bit 10)
REFDIV9
(Bit 9)
REFDIV8
(Bit 8)
BYTE 1
REFDIV7 BYTE 0
(Bit 7)
REFDIV6
(Bit 6)
REFDIV5
(Bit 5)
REFDIV4
(Bit 4)
REFDIV3
(Bit 3)
REFDIV2
(Bit 2)
REFDIV1
(Bit 1)
REFDIV0
(Bit 0)
3URJUDPPDEOH / LQH / RFN &ORFN HQHUDWRU , &
April 1999
Table 4: Device Configuration Bits
Table 5: LOCK / IPRG Pin Configuration Bits
main loop SHUT down select
Phase Detector REFerence source
Phase Detector FeedBacK source
Table 6: Lock Status
CMOS STAT 1 0 STAT 0 0 LOCK / IPRG PIN 1 0 0 1 0 1 1 1 STAT1 READ 1 0 0 STATUS Locked Unlocked Out-ofRange: Low Out-ofRange: High
FeedBacK Divider SouRCe Post Divider Output FBK pin VCO Output (Post Divider Input) FBK pin
EXTernal Loop Filter select Internal Loop Filter EXTLF pin Low Phase Jitter Oscillator FS6031 Compatible Oscillator VCOSPD (Bit 44)
OSCillator TYPe
Table 7: Main Loop Tuning Bits
OUTput MUltipleXer select Main Loop PLL (VCO Output) Reference Divider Output Phase Detector Input VCXO Output
clock GobBLer control No Clock Phase Adjust Clock Phase Delay PECL Output (positive-ECL output drive) CMOS Output / Lock Status Indicator
Loop Filter Time Constant (internal) Short Time Constant: 13.5µs Long Time Constant: 135µs
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April 1999
Table 8: Divider Control Bits
Table 9: Crystal Loop Tuning Bits
POST Divider #1 (NP1) Divide by 1 Divide by 2 Divide by 4 Divide by 8
POST Divider #2 (NP2) Divide by 1
Divide by 3 Divide by 5 Divide by 4
Disabled (crystal loop operates) Enabled (crystal loop is powered down)
Crystal Coarse Tune (see Table 11)
Set these reserved bits to 0
Table 10: Crystal Loop Control ROM
XLROM 2 0 0 0 0 1 1 1 1 XLROM 1 0 0 1 1 0 0 1 1 XLROM 0 0 1 0 1 0 1 0 1 VCXO DIVIDER 1 3072 3156 2430 2500 4000 3375 CRYSTAL FREQUENCY (MHz) 24.576 25.248 19.44 20.00 32.00 27.00
Crystal Oscillator Power-Down
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April 1999
VCXO Coarse Tune
Table 11: VCXO Coarse Tuning Capacitance
XCT3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 XCT2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 XCT1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 XCT0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCXO TUNING CAPACITANCE (pF) 10.00 10.84 11.69 12.53 13.38 14.22 15.06 15.91 16.75 17.59 18.43 19.28 20.13 20.97 21.81 22.66
The VCXO may be coarse tuned by a programmable adjustment of the crystal load capacitance via XCT3:0. The actual amount of frequency warping caused by the tuning capacitance will depend on the crystal used. The VCXO tuning capacitance includes an external 6pF load capacitance (12pF from the XIN pin to ground and 12pF from the XOUT pin to ground). The fine tuning capability of the VCXO can be enabled by setting the XLVTEN bit to a logic-one, or disabled by setting the bit to a logiczero.
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April 1999
Electrical Specifications
Table 12: Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality, and reliability.
SYMBOL VDD VI VO IIK IOK TS TA TJ
MIN. VSS-0.5 VSS-0.5 VSS-0.5 -50 -50 -65 -55
MAX. 7 VDD+0.5 VDD+0.5 50 50 150 125 150 260 2
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge.
Table 13: Operating Conditions
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April 1999
Table 14: DC Electrical Specifications
PARAMETER Overall Supply Current, Dynamic, (with Loaded Outputs) Supply Current, Static Serial Communication I / O (SDA, SCL) High-Level Input Voltage Low-Level Input Voltage Hysteresis Voltage Input Leakage Current Low-Level Output Sink Current (SDA) Tristate Output Current Address Select Input (ADDR) High-Level Input Voltage Low-Level Input Voltage High-Level Input Current (pull-down) Low-Level Input Current Reference Frequency Input (REF, FBK) High-Level Input Voltage Low-Level Input Voltage Hysteresis Voltage Input Leakage Current Loop Filter Input (EXTLF) Input Leakage Current
SYMBOL
CONDITIONS / DESCRIPTION
UNITS
IDD IDDL
VIH VIL Vhys II IOL IZ
Outputs off Outputs off Outputs off
3.5 VSS-0.3 2 -1
VDD+0.3 1.5 1 32 10
2.4 VSS-0.3 5 -2 16
VDD+0.3 0.8 30 2
VIH VIL Vhys II
3.5 VSS-0.3 500 -1
VDD+0.3 1.5 1
High-Level Output Source Current
Low-Level Output Sink Current
3URJUDPPDEOH / LQH / RFN &ORFN HQHUDWRU , &
April 1999 Table
15: DC Electrical Specifications, continued
PARAMETER Crystal Oscillator Output (XOUT) High-Level Output Source Current Low-Level Output Sink Current VCXO Tuning I / O (XTUNE) High-Level Input Voltage Low-Level Input Voltage Hysteresis Voltage Input Leakage Current
SYMBOL
CONDITIONS / DESCRIPTION
UNITS
IOH IOL VIH VIL Vhys II
-20 -20 3.2 VSS-0.3 1.0 -1
-50 -50 VDD+0.3 0.3 1
-1.5 -5 -8 -24 1.5 5 8 25 -1 -25 5 -38 9 66 76 -47 47 -45 15 -68 20 28 33 -100 100 1:4 1 µA mA mA mA mA mA mA mA mA µA µA
High-Level Output Source Current
Low-Level Output Sink Current
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April 1999
Table 16: AC Timing Specifications
PARAMETER Overall Output Frequency
SYMBOL
CONDITIONS / DESCRIPTION
CLOCK (MHz)
UNITS
fO(max)
VCO Frequency
VCO Gain
Loop Filter Time Constant Rise Time Fall Time Lock Time (Main Loop) Disable Time Divider Modulus Feedback Divider Reference Divider Post Divider NF NR NP1 NP2 NP3 tr tf
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April 1999
Table 17: AC Timing Specifications, continued
PARAMETER Clock Output (CLKP, CLKN) Duty Cycle
SYMBOL
CONDITIONS / DESCRIPTION
CLOCK (MHz)
UNITS
Jitter, Long Term (y())
tj(LT)
Jitter, Period (peak-peak)
tj(P)
ps 105 340 270
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April 1999
Table 18: Serial Interface Timing Specifications
PARAMETER Clock frequency Bus free time between STOP and START Set up time, START (repeated) Hold time, START Set up time, data input Hold time, data input Output data valid from clock Rise time, data and clock Fall time, data and clock High time, clock Low time, clock Set up time, STOP
SYMBOL fSCL tBUF tsu:STA thd:STA tsu:DAT thd:DAT tAA tR tF tHI tLO tsu:STO SDA SDA SCL
CONDITIONS / DESCRIPTION
STANDARD MODE MIN. 0 4.7 4.7 4.0 250 0 3.5 1000 300 4.0 4.7 4.0 MAX. 400
UNITS kHz µs µs µs ns µs µs ns ns µs µs µs
Minimum delay to bridge undefined region of the falling edge of SCL to avoid unintended START or STOP
SDA, SCL SDA, SCL SCL SCL
Figure 17: Bus Timing Data
tsu:STA thd:STA tsu:STO
START
ADDRESS OR DATA VALID
DATA CAN CHANGE
Figure 18: Data Transfer Sequence
tF tHI tR
tLO tsu:STA thd:STA thd:DAT tsu:DAT tsu:STO
SDA IN
tAA tAA
SDA OUT
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April 1999
Table 19: CLKP, CLKN Clock Outputs (CMOS Mode)
Voltage (V) 0 0.2 0.5 0.7 1 1.2 1.5 1.7 2 2.2 2.5 2.7 3 3.5 4 4.5 5 5.5 Low Drive Current (mA) MIN. 0 7 18 24 32 37 43 46 51 53 55 56 57 58 59 59 TYP. 0 11 27 36 49 56 66 72 79 83 88 91 93 95 97 99 100 MAX. 0 15 37 50 69 80 95 103 115 122 130 135 140 146 149 152 155 158 Voltage (V) 0 0.5 1 1.5 2 2.5 2.7 3 3.2 3.5 3.7 4 4.2 4.5 4.7 5 5.2 5.5 High Drive Current (mA)
MIN. -58 -56 -55 -53 -49 -43 -40 -35 -31 -25 -21 -14 -8 0
TYP. -98 -96 -94 -91 -85 -77 -73 -67 -62 -54 -48 -39 -32 -21 -13 0
MAX. -153 -150 -148 -142
Output Current (mA) 100 150
-200 Output Voltage (V)
TYP MAX
The data in this table represents nominal characterization data only.
Table 20: LOCK / IPRG Clock Output (CMOS Mode)
Voltage (V) 0 0.2 0.5 0.7 1 1.2 1.5 1.7 2 2.2 2.5 2.7 3 3.5 4 4.5 5 5.5 Low Drive Current (mA) MIN. 0 4 9 12 16 19 23 25 28 29 32 33 34 35 35 36 TYP. 0 4 10 13 18 21 26 29 32 35 38 39 42 45 46 46 47 MAX. 0 4 11 15 21 25 30 33 38 41 45 48 51 56 60 62 63 63 Voltage (V) 0 0.5 1 1.5 2 2.5 2.7 3 3.2 3.5 3.7 4 4.2 4.5 4.7 5 5.2 5.5 High Drive Current (mA)
MIN. -35 -34 -33 -31 -28 -24 -23 -20 -17 -14 -11 -7 -4 0
TYP. -46 -45 -43 -41 -37 -33 -31 -28 -26 -22 -19 -15 -12 -8 -5 0
MAX. -61 -60 -57 -54
Output Current (mA) 40 60
-80 Output Voltage (V)
TYP MAX
The data in this table represents nominal characterization data only.
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April 1999
Package Information
Table 21: 16-pin SOIC (0.150") Package Dimensions
DIMENSIONS INCHES MIN. A A1 A2 B C D E e H h L 0.061 0.004 0.055 0.013 0.0075 0.386 0.150 0.230 0.010 0.016 0° MAX. 0.068 0.0098 0.061 0.019 0.0098 0.393 0.157 0.244 0.016 0.035 8° MILLIMETERS MIN. 1.55 0.102 1.40 0.33 0.191 9.80 3.81 5.84 0.25 0.41 0° MAX. 1.73
ALL RADII: 0.005" TO 0.01"
7° typ.
SEATING PLANE
0.050 BSC
1.27 BSC
BASE PLANE
Table 22: 16-pin SOIC (0.150") Package Characteristics
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April 1999
Ordering Information
Device Ordering Codes
DEVICE NUMBER FS6131 FS6131 FS6131 FS6131 FONT PACKAGE TYPE 16-pin (0.150") SOIC (Small Outline Package) 16-pin (0.150") SOIC (Small Outline Package) 16-pin (0.150") SOIC (Small Outline Package) 16-pin (0.150") SOIC (Small Outline Package) OPERATING TEMPERATURE RANGE 0°C to 70°C (Commercial) 0°C to 70°C (Commercial) -40°C to 85°C (Industrial) -40°C to 85°C (Industrial) SHIPPING CONFIGURATION Tape-and-Reel Tubes Tape-and-Reel Tubes
ORDERING CODE
-01 -01 -01i -01i
Demo Kit Ordering Codes
KIT FOR DEVICE NUMBER: DESCRIPTION Kit includes: · Populated board with example device · Interface Cable · Programming Assistance PC Software
ORDERING CODE
FS6131-01
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April 1999
Demonstration Board and Software
A simple demonstration board and Windows 3.1x / 95 / 98-based software is available from American Microsystems that illustrates the capabilities of the FS6131. The software can operate under Windows NT but cannot communicate with the board. The board schematic is shown below. Components listed with an asterisk () are not required in an actual application, and are used here to preserve signal integrity with the cabling associated with the board. A cabled interface between a computer parallel port (DB25 connector) and the board (J1) is provided. Components shown in dashed lines are optional, depending on the application. Contact your local sales representative for more information.
Figure 19: Board Schematic
J1 1 SCL 2 SDA 3 ADDR 4 +5V 5 6 +5V +5V GND 2 3 4 5 +5V RP1 1k R16 C10 C11 C1 2.2µF C3 0.1µF Y1 27MHz 6 7 8 1 16 15 R7 47 14 R13 C8 12pF C9 12pF 13 12 11 10 9 R9 R18 R19 CLKP C2 2.2µF C4 0.1µF R12 R14 R6 47 CLKN +5V R3 100 R2 100 R5 10 R1 100 +5V
SCL SDA ADDR VSS
CLKN CLKP VDD FBK
FS6131
XIN XOUT XTUNE VDD REF VSS EXTLF LOCK / IPRG
FBK REF
C7 R8 R4 10 LOCK R17 C6
AMERICAN MICROSYSTEMS, INC. FS6131 DEMO BOARD
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Demo Kit Contents
Demonstration board Interface cable (DB25 to 6-pin connector) Data sheet Programming software
Requirements
PC running MS Windows® 3.1x or 95 / 98 with an accessible parallel (LPT1) port. Software also runs on Windows NT® in a calculation mode only. 2.0MB available space on hard drive C:
Demo Program Operation
Board Setup and Software Installation Instructions
1. Run the self-expanding exe file to unzip the compressed demo files to a directory of your choice. 2. Run the setup.exe file to install the programming software.
Figure 20: Opening Screen
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April 1999
10.4.1 Device Mode The Device Mode block presets the demo program to program the FS6131 either as a frequency synthesizer (a stand alone clock generator) or as a line-locked or genlock clock generator. Frequency Synthesis: For use as a stand alone clock generator. Note that the Reference Source is the on-chip crystal oscillator, the expected crystal frequency is 27MHz, and the Voltage Tune in the Crystal Oscillator (i.e. the VCXO) is disabled. The default output frequency (CLK freq.) requested is 100MHz, with a maximum error of 10ppm, or about 100Hz. The Output Stage defaults to CMOS mode. Line-Locked / Genlock: For use in a line lock or genlock application. Note that the Reference Source is the REF Pin, and that the expected reference frequency is 8kHz. The default output frequency requested is a 100x multiple of the reference frequency. 10.4.2 Example: Frequency Synthesizer Mode By default the demo program assumes the FS6131 is configured as a stand alone clock generator. Note that the Reference Source defaults to the on-chip crystal oscillator, the expected crystal frequency is 27MHz, and the Voltage Tune in the Crystal Oscillator block (i.e. the VCXO) is disabled. The default output frequency (CLK freq.) requested is 100MHz, with a maximum error of 10ppm, or about 100Hz. The Output Stage defaults to CMOS mode. The Loop Filter block is set to internal, and the Check Loop Stability switch is on. As an exercise, click on Calculate Solutions. The program takes into account all of the screen settings and calculates all possible combinations of Reference, Feedback, and Post Divider values that will generate the output frequency (100MHz) from the input frequency (27MHz) within the desired tolerance (10ppm). A box will momentarily appear: "Calculating Solutions: Press cancel to stop with the solutions calculated so far." A number in the box will increment for every unique solution that is found. This example will create six unique solutions, which are then displayed in a window in the lower right portion of the program screen.
The best PLL performance is obtained by running the VCO at as high a speed as possible. The last three solutions show a VCO speed of 200MHz. Furthermore, good PLL performance is obtained with the smallest dividers possible, which means solution #4 should provide the best results.
Figure 21: Frequency Synthesizer Screen
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April 1999
Figure 22: Line-Locked Screen
Table 23: Cable Interface
Color Red White Green Blue Brown Black J1 1 2 3 4 5 6 DB25 2, 13 3, 12 8 5 4 25 Signal SCL SDA ADDR GND
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April 1999
Table 24: Sample Text Output
Figure 24: Board Silkscreen
1H (1) 40H (64) 2H (2) 20H (32) 3H (3) 24H (36) 0H (0) 17H (23)
Figure 25: Board Traces - Component Side
Figure 23: Cable Connections
Figure 26: Board Traces - Solder Side
DB-25
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April 1999
Applications Information
A signal reflection will occur at any point on a PC-board trace where impedance mismatches exist. Reflections cause several undesirable effects in high-speed applications, such as an increase in clock jitter and a rise in electromagnetic emissions from the board. Using a properly designed series termination on each high-speed line can alleviate these problems by eliminating signal reflections.
11.1.1 Example Calculation In PECL mode, the output driver does not source current, so the VIH value is determined by the ratios of the terminating resistors using the equation
where Rp1 is the pull-up resistor, Rp2 is the pull-down resistor, and VNMH is the desired noise margin, and
PECL Output Mode
The resistor ratio must also match the line impedance via the equation
where zL is the line impedance. Combining these equations, and solving for Rp1 gives
VCC VCC
Rp1 PECL Mode Output CLKP CLKN Ri zO zL zL
from PLL
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April 1999
CMOS Output Mode
Serial Communications
If a CMOS interface is desired, a transmission line is typically terminated using a series termination. Series termination adds no dc loading to the driver, and requires less power than other resistive termination methods. In addition, no extra impedance exists from the signal line to a reference voltage, such as ground.
Figure 28: Series Termination (CMOS)
zO DRIVER RS LINE zL
RECEIVE
Connection of devices to a standard-mode implementa2 tion of the I C-bus is similar to that shown in Figure 29. Selection of the pull-up resistors (RP) and the optional series resistors (RS) on the SDA and SCL lines depends on the supply voltage, the bus capacitance, and the number of connected devices with their associated input currents. Control of the clock and data lines is done through open drain / collector current-sink outputs, and thus requires external pull-up resistors on both lines. A guideline is
When the source impedance (zO+RS) is matched to the line impedance, then by voltage division the incident wave amplitude is one-half of the full signal amplitude.
where tr is the maximum rise time (minus some margin) 2 and Cbus is the total bus capacitance. Assuming an I C controller and 8 to 10 other devices on the bus, including this one, results in values in the 5k to 7k range. Use of a series resistor to provide protection against high voltage spikes on the bus will alter the values for RP.
Figure 29: Connections to the Serial Bus
SDA SCL
(optional)
However, the full signal amplitude may take up to twice as long as the propagation delay of the line to develop, reducing noise immunity during the half-amplitude period. Note that the voltage at the receive end must add up to a signal amplitude that meets the receiver switching thresholds. The slew rate of the signal may be reduced due to the additional RC delay of the load capacitance and the line impedance. Also, note that the output driver impedance will vary slightly with the output logic state (high or low).
(optional)
Data In Clock Out Data Out Clock In
Data In
Data Out
TRANSMITTER
RECEIVER
11.3.1 For More Information 2 More information on the I C-bus can be found in the 2 document The I C-bus And How To Use It (Including Specifications), available from Philips Semiconductors at http://www-us2.semiconductors.philips.com.
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April 1999
Device Application: Stand-Alone Clock Generation
The length of the reference and feedback dividers, their granularity, and the flexibility of the post Divider make the FS6131 the most flexible monolithic stand-alone PLL clock generation device available. The effective block diagram of the FS6131 when programmed for StandAlone mode is shown in Figure 30. The source of the Feedback Divider in the Stand-Alone mode is the output of the VCO. By dividing the input reference frequency down by Reference Divider (NR), then multiplying it up in the Main Loop through the Feedback Divider (NF), and finally dividing the Main Loop output frequency by the Post Divider (NPx), we have the defining relationship for this mode. The equation for the output clock frequency (fCLK) can be written as
where the reference source frequency (fREF) can be either supplied by the VCXO or applied to the REF pin. Great flexibility is permitted in the programming of the FS6131 to achieve exact desired output frequencies since three integers are involved in the computation.
Example Calculation
A Visual BASIC program is available to completely program the FS6131 based on the given parameters. Suppose that the reference source frequency is 14.318MHz and the desired output frequency is 100MHz. First, factor the 14.318MHz reference frequency (which is four times the NTSC television color sub-carrier) into prime numbers. The exact expression is
(Eqn.1)
Figure 30: Block Diagram: Stand-Alone Clock Generation
LFTC CLF CLP XLROM2:0 XLPDEN, XLSWAP
XTUNE
(optional)
XCT3:0, XLVTEN
Control ROM VCXO Divider
CRYSTAL LOOP
XLCP1:0
XIN VCXO XOUT
(optional)
Internal Loop Filter
PhaseFrequency Detector
EXTLF
EXTLF STAT1:0 RIPRG
Charge Pump
(optional)
Lock Detect
REFDIV11:0
LOCK / IPRG
(optional)
(fREF)
REFDSRC
Reference Divider
MLCP1:0 PDREF UP
VCOSPD, OSCTYPE
POST31:0 POST21:0 POST11:0
PDFBK
PhaseFrequency Detector
Charge Pump
Voltage Controlled Oscillator
Clock Gobbler
OM1:0
Post Divider (NPx) CMOS / PECL Output
(fCLK)
ADDR Feedback Divider (NF) SCL SDA I2C Interface
FBKDSRC1:0
(fVCO)
Registers
MAIN LOOP
FBKDIV14:0
FS6131
3URJUDPPDEOH / LQH / RFN &ORFN HQHUDWRU , &
April 1999 Next, express the output and input frequencies as a ratio of fCLK to fREF, where fCLK has also been converted to a product of prime numbers. As Eqn. 3 shows, the VCO frequency can be doubled by multiplying the Feedback Divider by two. Set the Post Divider to two to return the output frequency to the desired modulus. These divider settings place the VCO frequency at 200MHz.
Example Programming
(Eqn. 2)
Deciding how to apportion the denominator integers between the Reference Divider and the Post Divider is an iterative process. To obtain the best performance, the VCO should be operated at the highest frequency possible without exceeding its upper limit of 230MHz. (see Table 16). The VCO frequency (fVCO) can be calculated by
Recall that the Reference Divider can have a value between 1 and 4096, but the Post Divider is limited to values derived from
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April 1999
Device Application: Line-Locked Clock Generation
Example Calculation
Line-locked clock generation, as used here, refers to the process of synthesizing a clock frequency that is some integer multiple of the horizontal line frequency in a graphics system. The FS6131 is easily configured to perform that function, as shown in Figure 31. A line reference signal (fHSYNC) is applied to the REF input for direct application to the Main Loop PFD. The Feedback Divider (NF) is programmed for the desired number of output clocks per line. The source for the Feedback Divider is selected to be the output of the Post Divider (NPx) so that the edges of the output clock maintain a consistent phase alignment with the line reference signal. The modulus of the Post Divider should be selected to maintain a VCO frequency that is comfortably within the operating range noted in Table 16.
Figure 31: Block Diagram: Line-Locked Clock Generation
LFTC CLF CLP XLROM2:0 XLPDEN, XLSWAP
XTUNE
(optional)
XCT3:0, XLVTEN
Control ROM VCXO Divider
CRYSTAL LOOP
XLCP1:0
XIN VCXO XOUT
(optional)
Internal Loop Filter
PhaseFrequency Detector
EXTLF
EXTLF STAT1:0 RIPRG
Charge Pump
(optional)
Reference HSYNC
REFDIV11:0
Lock Detect REF
(fREF)
REFDSRC POST31:0, POST21:0, POST11:0
LOCK / IPRG
(optional)
Reference Divider
MLCP1:0 PDREF UP
VCOSPD, OSCTYPE
PDFBK
PhaseFrequency Detector
Charge Pump
Voltage Controlled Oscillator
Clock Gobbler
OM1:0
Post Divider (NPx) CMOS / PECL Output
(fCLK)
ADDR Feedback Divider (NF) SCL SDA I2C Interface
FBKDSRC1:0
(fVCO)
Registers
MAIN LOOP
FBKDIV14:0
FS6131
3URJUDPPDEOH / LQH / RFN &ORFN HQHUDWRU , &
April 1999 However, the 31.5kHz line reference signal is too low in frequency for the internal loop filter to be used. A series combination of a 0.015µF capacitor and a 15k resistor from power (VDD) to the EXTLF pin provides an external loop filter. A 100pF to 220pF capacitor in parallel with the combination may improve the filter performance. For the best PLL performance, program the Post Divider modulus to allow the VCO to operate at a nominal frequency that is at least 70MHz but less then 230MHz. The VCO frequency (fVCO) can be calculated by
Example Programming
to avoid divider values from becoming too large. These settings place the VCO frequency at about 100MHz. Calculate the ideal charge pump current (Ipump) as
I pump
The output clock frequency fCLK is 25.175MHz, with an internal VCO frequency of 100.8MHz. Note that the Crystal Loop was unused in this application.
3URJUDPPDEOH / LQH / RFN &ORFN HQHUDWRU , &
April 1999 The output clock frequency is:
Device Application: Genlocking
The only remaining task is to select a Post Divider modulus (NPx) that allows the VCO frequency to be within its nominal range.
Genlocking refers to the process of synchronizing the horizontal sync pulses (HSYNC) of a target graphics system to the HSYNC of a source graphics system. In a genlocked mode, the FS6131 increases (or decreases) the frequency of the VCO until the FBK input is frequency matched and phase-aligned to the frequency applied to the REF input. Since the feedback divider is within the graphics system and the graphics system is the source of the signal applied to the FBK input of the FS6131, the graphics system is effectively synchronized to the REF input as shown in Figure 32. To configure the FS6131 for genlocking, the REF input (pin 12) and the FBK input (pin 13) are switched directly onto the feedback input of the PFD. The Reference and Feedback dividers are not used.
Example Calculation
A Visual BASIC program is available to completely program the FS6131 based on the given parameters. The FS6131 is being used to genlock an LCD projection panel system to a VGA card-generated HSYNC. The total number of pixel clocks generated by the VGA card, known as the horizontal total, are 800. Therefore, the LCD panel graphics system that is clocked by the FS6131 is set to divide the output clock frequency (fCLK) by 800. The input HSYNC reference frequency (fHSYNC) is 15kHz.
Figure 32: Block Diagram: Genlocking
LFTC CLF CLP XLROM2:0 XLPDEN, XLSWAP
XTUNE
(optional)
XCT3:0, XLVTEN
Control ROM VCXO Divider
CRYSTAL LOOP
XLCP1:0
XIN VCXO XOUT
(optional)
Internal Loop Filter
PhaseFrequency Detector
EXTLF
EXTLF STAT1:0 RIPRG
Charge Pump
(optional)
Reference HSYNC
REFDIV11:0
Lock Detect REF
(fCLK)
REFDSRC POST31:0, POST21:0, POST11:0
LOCK / IPRG
(optional)
Reference Divider
MLCP1:0 PDREF UP
VCOSPD, OSCTYPE
PDFBK
PhaseFrequency Detector
Charge Pump
Voltage Controlled Oscillator
Clock Gobbler
OM1:0
Post Divider (NPx) CMOS / PECL Output
(fCLK)
ADDR Feedback Divider (NF) SCL SDA I2C Interface
FBKDSRC1:0
(fVCO)
Registers
FBKDIV14:0
MAIN LOOP
FS6131
System HSYNC Video Graphics System Clock In
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April 1999 The output clock frequency is calculated as
For best performance, program the Post Divider (NPx) modulus to allow the VCO to operate at a nominal frequency that is at least 70MHz but less then 230MHz. The VCO frequency (fVCO) can be calculated by
Example Programming
to avoid divider values from becoming too large. The settings place the VCO frequency at about 72MHz. Calculate the ideal charge pump current (Ipump) as · ·
The output clock frequency fCLK is 12MHz, with an internal VCO frequency of 72MHz. Note that the Crystal Loop was unused in this application.
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April 1999
Device Application: Telecom Clock Regenerator
Example Calculation
The FS6131 can be used as a clock regenerator as shown in Figure 33. This mode uses the voltagecontrolled crystal oscillator (VCXO) in its own phaselocked loop, referred to as the Crystal Loop. The VCXO provides a "de-jittered" multiple of the reference frequency at the REF pin (usually 8kHz in telecom applications) for use by the Main Loop. In essence, the Crystal Loop "cleans up" the reference signal for the Main Loop. The Control ROM for the VCXO Divider is preloaded with the most common ratios to permit locking of most standard telecommunications crystals to an 8kHz signal applied to the REF pin. The de-jittered multiple of the reference frequency from the VCXO is then supplied to the Reference Divider in the Main Loop. The Reference Divider, along with the Feedback Divider, can be programmed to achieve the desired output clock frequency.
A Visual BASIC program is available to completely program the FS6131 based on the given parameters. In this example, an 8kHz reference frequency is supplied to the FS6131 and an output clock frequency of 51.84MHz is desired. First, select the frequency at which the VCXO will operate from Table 10. The table shows the external crystal frequency options available to choose from, since the VCXO runs at the crystal frequency. While the Main Loop can be programmed to work with any of the frequencies in the table, the best performance will be achieved with the highest frequency at the Main Loop PFD. The frequency at the Main Loop PFD (fMLpfd) is the VCXO frequency (fVCXO) divided by the Main Loop Reference Divider (NR).
f VCXO NR
Figure 33: Block Diagram: Telecom Clock Regenerator
CLF CLP
XTUNE
(optional)
XCT3:0, XLVTEN
Control ROM VCXO Divider
XLROM2:0 XLPDEN, XLSWAP
CRYSTAL LOOP
XLCP1:0
XIN VCXO XOUT
(optional)
Internal Loop Filter
PhaseFrequency Detector
EXTLF
EXTLF STAT1:0 RIPRG
Charge Pump
(optional)
8kHz IN (typical)
Lock Detect
REFDIV11:0
LOCK / IPRG
(optional)
(fREF)
REFDSRC
Reference Divider
MLCP1:0 PDREF UP
VCOSPD, OSCTYPE
POST31:0, POST21:0, POST11:0
PDFBK
PhaseFrequency Detector
Charge Pump
Voltage Controlled Oscillator
Clock Gobbler
OM1:0
Post Divider (NPx) CMOS / PECL Output
(fCLK)
ADDR Feedback Divider (NF) SCL SDA I2C Interface
FBKDSRC1:0
(fVCO)
Registers
MAIN LOOP
FBKDIV14:0
FS6131
3URJUDPPDEOH / LQH / RFN &ORFN HQHUDWRU , &
April 1999 The goal is to choose the highest crystal frequency from Table 10 that generates the smallest value of NR. The equation establishing the output frequency (fCLK) as a function of the input VCXO frequency is
Example Programming
(Eqn. 1)
where NF is the Feedback Divider modulus. Choose a few different crystal frequencies from Table 10 and factor both the input VCXO and output clock frequencies into prime numbers. Look for the factors that will give the smallest modulus for NR with the largest FVCXO. The output and VCXO frequencies and the reduced factors from Eqn. 1 are in Table 25.
Table 25: Clock Regenerator Example
VCXO FREQUENCY FROM Table 10 (fVCXO, MHz)
f CLK f VCXO