'LJLWDO $XGLR9LGHR &ORFN *HQHUDWRU July 1998 Features D

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'LJLWDO $XGLR9LGHR &ORFN *HQHUDWRU July 1998 Features D

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'LJLWDO $XGLR9LGHR &ORFN *HQHUDWRU
July 1998
Features
Description
Triple phase-locked loop (PLL) device provides exact ratiometric derivation Audio, Processor, Utility Clocks On-chip tunable voltage-controlled crystal oscillator (VCXO) allows precise system frequency tuning Serial interface Audio Utility Clock frequency selection Board-programmable Processor Clock frequency selection Supports 44.1, 48kHz 256x oversampled DACs well 384x 44.1kHz 512x 48kHz Tunable Audio Clock frequencies undetectable resynchronization audio video streams Small circuit board footprint (16-pin 0.150 SOIC) Custom frequency selections available contact your local Sales Representative more information
FS6011-02 monolithic CMOS clock generator designed minimize cost component count digital video/audio systems. core FS6011-02 circuitry that implements voltage-controlled crystal oscillator when external resonator (nominally 27MHz) attached. VCXO allows device frequencies precisely adjusted systems that have frequency matching requirements, such digital satellite receivers. Three high-resolution phase-locked loops independently generate three other selectable frequencies derived from VCXO frequency. These clock frequencies related VCXO frequency each other exact ratios. locking output frequencies together eliminate unpredictable artifacts video systems unpredictable electromagnetic interference (EMI) performance frequency harmonic stacking.
Figure Block Diagram
PSEL0 PSEL1 Processor Clock PCLK
Figure Configuration
SCLK SDATA
CLK27 ACLK UCLK PCLK PSEL0 PSEL1
XTUNE VCXO XOUT
Audio Clock
ACLK
SLOAD
FS6011
Utility Clock
UCLK
XOUT XTUNE
SLOAD SCLK SDATA
CLK_27 Serial Interface
FS6011
16-pin (0.150) SOIC
American Microsystems, Inc. reserves right change detail specifications required permit improvements design products.
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'LJLWDO $XGLR9LGHR &ORFN *HQHUDWRU
July 1998
Table Descriptions
Key: Analog Input; Analog Output; Digital Input; Input with Internal Pull-Up; Input with Internal Pull-Down; Digital Input/Output; DI-3 Three-Level Digital Input, Digital Output; Power/Ground; Active
TYPE
NAME SCLK SDATA SLOAD XOUT XTUNE PSEL1 PSEL0 PCLK UCLK ACLK CLK27 Serial Data Clock Serial Data Input Serial Port Load Ground VCXO Feedback VCXO Drive VCXO Tune Power Supply (+5V) PCLK Select PCLK Select Ground Processor Clock Output Utility Clock Output Power Supply (+5V) Audio Clock Output Reference Clock Output
DESCRIPTION
Functional Block Description
Phase-Locked Loops
Digital Interface
Each three on-chip PLLs FS6011 multiplies reference frequency desired frequency ratio integers. This frequency multiplication exact.
Output Tristate Control
four clock outputs FS6011 tristated facilitate circuit board testing. place outputs tristate mode, follow this sequence: force (i.e. ground) apply power device wait until internal power-on reset deasserted apply negative-going transition PSEL0 Outputs re-enabled removing reapplying power FS6011. re-enable outputs without removing power, apply rising edge transition follow with falling edge transition PSEL0 pin.
Digital data placed SDATA clocked into FS6011 internal shift register (D[0] first) with rising edge SCLK pin. shift register data transferred FS6011 control registers with rising edge SLOAD pin. Fifteen bits must shifted into internal registers before parallel load performed. addition normal control functions performed D[13:0], there reserved bit, D[14], that should zero. control registers initialized zero power-up.
Figure Communications Protocol
SCLK
thd:DAT tsu:DAT
SDATA
tsu:LD thd:LD
SLOAD
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'LJLWDO $XGLR9LGHR &ORFN *HQHUDWRU
July 1998
Voltage-Controlled Crystal Oscillator (VCXO)
Programming Information
VCXO provides tunable, low-jitter frequency reference rest FS6011 system components. Loading capacitance crystal internal FS6011. external components (other than resonator itself) required operation VCXO. resonator loading capacitance adjustable under register control. This permits factory coarse tuning inexpensive resonators necessary precision digital video applications. Refer Section 4.6. Continuous fine-tuning VCXO frequency accomplished varying voltage XTUNE pin. total change (from extreme other) effective loading capacitance 1.5pF nominal. oscillator operates crystal resonator parallel-resonant mode. Crystal warping, "pulling" crystal oscillation frequency, accomplished altering effective load capacitance presented crystal oscillator circuit. actual amount that changing load capacitance alters oscillator frequency will dependent characteristics crystal well oscillator circuit itself. Specifically, motional capacitance crystal (usually referred crystal manufacturers C1), static capacitance crystal (C0), load capacitance (CL) oscillator determine warping capability crystal oscillator circuit. simple formula obtain warping capability crystal oscillator
Table Register Summary
D[x] REGISTER DESCRIPTION ACLK Select (LSB) ACLK Select ACLK Select (MSB) ACLK Off-Speed Mode Disable Off-Speed Mode Enable Off-Speed Mode
ACLK Speed Control Speed High Speed
UCLK Select (LSB) UCLK Select UCLK Select (MSB) CLK27 Select
Selects VCXO Frequency Selects UCLK Frequency
Crystal Oscillator Coarse Tune (LSB) Crystal Oscillator Coarse Tune Crystal Oscillator Coarse Tune Crystal Oscillator Coarse Tune (MSB) VCXO Enable/Disable Control
Disable VCXO Mode Enable VCXO Mode
ppm)
Reserved (should
where extremes applied load capacitance. crystal with following parameters used. With 0.02pF, 5pF, 10pF, 22.66pF, coarse tuning range
0.02 (22.66 22.66
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'LJLWDO $XGLR9LGHR &ORFN *HQHUDWRU
July 1998
Audio Clock Frequencies (ACLK)
Utility Clock Frequencies (UCLK)
ACLK frequency controlled register bits D[0], D[1], D[2] accessed serial interface. ACLK frequencies listed below derived Divider Ratio from reference frequency 27MHz.
UCLK frequency controlled register bits D[5], D[6] D[7], accessed serial interface. UCLK frequencies listed below derived Divider Ratio from reference frequency 27MHz.
Table ACLK Frequency Select
D[2] D[1] D[0] DIVIDER AUDIO RATIO OVERSAMPLING 1024 2250 1024 3375 1024 4500 1024 6750 1568 3750 1568 2500 1568 7500 1024 1125 48kHz 32kHz 48kHz 32kHz 44.1kHz 44.1kHz 44.1kHz 48kHz ACLK (MHz) 12.288 8.192 6.144 4.096 11.2896 16.9344 5.6448 24.576
Table UCLK Frequency Select
D[7] D[6] D[5] DIVIDER RATIO 1568 3750 1024 1125 UCLK (MHz) 16.0000 28.6363 11.2896 27.0000 39.1680 52.4160 30.0000 24.5760
NOTE: Contact custom frequencies
NOTE: Contact custom frequencies
Audio Clock Off-Speed Frequencies
ACLK frequencies shown smoothly modified slightly higher lower value under register control. Register D[3] must logic-one activate this mode. value D[4] controls whether frequency will adjusted slightly (D[4] high (D[4]
Processor Frequencies (PCLK)
PCLK frequency controlled logic levels PSEL0 PSEL1 inputs. These inputs have weak pull-downs. PCLK frequencies listed below derived Divider Ratio from reference frequency 27MHz.
Table Audio Speed Frequencies
D[4] D[3] D[2] D[1] D[0] DIVIDER RATIO 1023 2250 1023 3375 1023 4500 1023 6750 1567 3750 1567 2500 1567 7500 1023 1125 1025 2250 1025 3375 1025 4500 1025 6750 1569 3750 1569 2500 1569 7500 1025 1125 ACLK (MHz) 12.276 8.184 6.138 4.092 11.2824 16.9236 5.6412 24.5520 12.3000 8.2000 6.1500 4.1000 11.2968 16.9432 5.6484 24.6000
Table PCLK Frequency Select
PSEL1 PSEL0 DIVIDER RATIO PCLK (MHz) 32.0000 40.0000 50.0000 39.5122
NOTE: Contact custom frequencies
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'LJLWDO $XGLR9LGHR &ORFN *HQHUDWRU
July 1998
Reference Frequencies (CLK27)
CLK27 output frequency controlled register D[8] that selects either VCXO reference frequency UCLK frequency.
Table CLK27 Frequency Select
D[8] CLK27 Output VCXO Frequency UCLK Frequency
Figure shows typical effect coarse fine tuning mechanisms. difference VCXO frequency parts-per-million (ppm) shown fine tuning voltage XTUNE varies from coarse tune range shown about 350ppm. crystal load capacitance increased (with increasing Coarse Tune setting) frequency pulled somewhat less with each coarse step fine tuning range decreases. fine tuning range always overlaps coarse tuning ranges, eliminating possibility holes VCXO response. Note that different crystal warping characteristics will change scaling Y-axis, overall characteristic curves.
VCXO Coarse Tuning Enable
VCXO Range (ppm)
VCXO coarse tuned programmable adjustment crystal load capacitance D[12:9]. actual amount frequency warping caused tuning capacitance will depend crystal used. VCXO tuning capacitance includes external load capacitance (12pF from ground 12pF from XOUT ground). fine tuning capability VCXO enabled setting D[13] logic-one disabled clearing logic-zero.
Figure VCXO Coarse Fine Tuning
VCXO Range (ppm) XTUNE Voltage
-100 -150 -200 Coarse Tune Setting D[11:14]
XTUNE Voltage 0.0V XTUNE Voltage 5.0V
Table VCXO Tuning Capacitance
D[12] D[11] D[10] D[9] VCXO TUNING CAPACITANCE (pF) 10.00 10.84 11.69 12.53 13.38 14.22 15.06 15.91 16.75 17.59 18.43 19.28 20.13 20.97 21.81 22.66
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'LJLWDO $XGLR9LGHR &ORFN *HQHUDWRU
July 1998
Electrical Specifications
Table Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. These conditions represent stress rating only, functional operation device these other conditions above operational limits noted this specification implied. Exposure maximum rating conditions extended conditions affect device performance, functionality, reliability.
PARAMETER Supply Voltage (VSS ground) Input Voltage, Output Voltage, Input Clamp Current, VDD) Output Clamp Current, VDD) Storage Temperature Range (non-condensing) Ambient Temperature Range, Under Bias Junction Temperature Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection (human-body model)
SYMBOL
MIN. VSS-0.5 VSS-0.5 VSS-0.5
MAX. VDD+0.5 VDD+0.5
UNITS
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting loss functionality performance occur this device subjected high-energy electrostatic discharge.
Table Operating Conditions
PARAMETER Supply Voltage Ambient Operating Temperature Range Output Load Capacitance Crystal Resonator Frequency Crystal Resonator Motional Capacitance Serial Data Transfer Rate SYMBOL fXIN CMOT CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS kb/s
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'LJLWDO $XGLR9LGHR &ORFN *HQHUDWRU
July 1998
Table Electrical Specifications
Unless otherwise stated, 5.0V 10%, load output, ambient temperature range 70°C. Parameters denoted with asterisk represent nominal characterization data production tested specific limits. Where given, characterization data from typical. Negative currents indicate current flows device.
PARAMETER Overall Supply Current, Dynamic, with Loaded Outputs
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
fCLK 27MHz; 50pF
Serial Communication Inputs (SCLK, SDATA, SLOAD) High-Level Input Voltage Low-Level Input Voltage Hysteresis Voltage Input Leakage Current PCLK Select Inputs (PSEL0, PSEL1) High-Level Input Voltage Low-Level Input Voltage High-Level Input Current (pull-down) Low-Level Input Current Crystal Oscillator Feedback (XIN) Threshold Bias Voltage Input Leakage Current Crystal Loading Capacitance Input Loading Capacitance Crystal Oscillator Drive (XOUT) High-Level Output Source Current Low-Level Output Sink Current VCXO Tuning Input (XTUNE) Input Leakage Current Clock Outputs (ACLK, CLK27, PCLK, UCLK) High-Level Output Source Current Low-Level Output Sink Current Output Impedance Tristate Output Current Short Circuit Source Current Short Circuit Sink Current IOSH IOSL shorted 30s, max. shorted 30s, max. 2.4V 0.4V 0.5VDD; output driving high 0.5VDD; output driving D[13] V(XTUNE) D[13] D[13] V(XTUNE) D[13] CL(xtal) CL(XIN) seen external crystal connected XOUT; VCXO tuning disabled seen external clock driver XIN; XOUT unconnected; VCXO disabled 0.5VDD VSS-0.3 12.7 VDD+0.3 Vhys VSS-0.3 VDD+0.3
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'LJLWDO $XGLR9LGHR &ORFN *HQHUDWRU
July 1998
Table Timing Specifications
Unless otherwise stated, 5.0V 10%, load output, ambient temperature range 70°C. Parameters denoted with asterisk represent nominal characterization data production tested specific limits. Where given, characterization data from typical.
PARAMETER Clock Output (ACLK)
SYMBOL
CONDITIONS/DESCRIPTION
CLOCK (MHz)
MIN.
TYP.
MAX.
UNITS
12.288 8.192 6.144
Duty Cycle
From rising edge rising edge 2.5V
4.096 11.289 16.344 5.644 24.576 12.288 8.192 6.144
Jitter, Absolute (long term)
tj(ab)
Measured from rising edge rising edge after 0.1s 2.5V; 15pF, fREF 27MHz
4.096 11.289 16.344 5.644 24.576 12.288 8.192 6.144
Jitter, Period
tj(P)
Measured rising edges 2.5V; 15pF, fREF 27MHz
4.096 11.289 16.344 5.644 24.576
Rise Time Fall Time Clock Stabilization Time
tSTB
0.5V 4.5V; 15pF 4.5V 0.5V; 15pF Output active from power-up
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Table Timing Specifications, continued
Unless otherwise stated, 5.0V 10%, load output, ambient temperature range 70°C. Parameters denoted with asterisk represent nominal characterization data production tested specific limits. Where given, characterization data from typical.
PARAMETER Clock Output (UCLK)
SYMBOL
CONDITIONS/DESCRIPTION
CLOCK (MHz)
MIN.
TYP.
MAX.
UNITS
16.000 28.636 11.289
2800 1500
Duty Cycle
From rising edge rising edge 2.5V
27.000 39.168 52.416 30.000 24.576 16.000 28.636 11.289
Jitter, Absolute (long term)
tj(ab)
Measured from rising edge rising edge after 0.1s 2.5V; 15pF, fREF 27MHz
27.000 39.168 52.416 30.000 24.576 16.000 28.636 11.289
Jitter, Period
tj(P)
Measured rising edges 2.5V; 15pF, fREF 27MHz
27.000 39.168 52.416 30.000 24.576
Rise Time Fall Time Clock Stabilization Time
tSTB
0.5V 4.5V; 15pF 4.5V 0.5V; 15pF Output active from power-up
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Table Timing Specifications, continued
Unless otherwise stated, 5.0V 10%, load output, ambient temperature range 70°C. Parameters denoted with asterisk represent nominal characterization data production tested specific limits. Where given, characterization data from typical.
PARAMETER Clock Output (PCLK)
SYMBOL
CONDITIONS/DESCRIPTION
CLOCK (MHz)
MIN.
TYP.
MAX.
UNITS
32.000
Duty Cycle
From rising edge rising edge 2.5V
40.000 50.000 39.512 32.000
Jitter, Absolute (long term)
tj(ab)
Measured from rising edge rising edge after 0.1s 2.5V; 15pF, fREF 27MHz
40.000 50.000 39.512 32.000
Jitter, Period
tj(P)
Measured rising edges 2.5V; 15pF, fREF 27MHz 0.5V 4.5V; 15pF 4.5V 0.5V; 15pF Output active from power-up
40.000 50.000 39.512
Rise Time Fall Time Clock Stabilization Clock Output (CLK27) Duty Cycle Clock Stabilization Time Rise Time Fall Time
tSTB
Crystal oscillator frequency out, from rising edge rising edge 2.5V tSTB Output active from power-up 0.5V 4.5V; 15pF 4.5V 0.5V; 15pF
Table Serial Interface Timing Specifications
Unless otherwise stated, 5.0V 10%, load output, ambient temperature range 70°C. Parameters denoted with asterisk represent nominal characterization data production tested specific limits. Where given, characterization data from typical.
PARAMETER SCLK clock frequency time, load Hold time, load time, data Hold time, data Rise time Fall time High time, serial clock time, serial clock
SYMBOL fSCLK tsu:LD thd:LD tsu:DAT thd:DAT
CONDITIONS/DESCRIPTION
MIN.
MAX.
UNITS
SLOAD SLOAD SDATA SDATA SDATA, SCLK SDATA, SCLK SCLK SCLK
1000
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July 1998
Package Information
Table 16-pin SOIC (0.150") Package Dimensions
DIMENSIONS INCHES MIN. 0.061 0.004 0.055 0.013 0.0075 0.386 0.150 0.230 0.010 0.016 MAX. 0.068 0.0098 0.061 0.019 0.0098 0.393 0.157 0.244 0.016 0.035 MILLIMETERS MIN. 1.55 0.102 1.40 0.33 0.191 9.80 3.81 5.84 0.25 0.41 MAX. 1.73
0.249 1.55 0.49 0.249 9.98 3.99 6.20 0.41 0.89
RADII: 0.005" 0.01"
typ.
SEATING PLANE
0.050
1.27
BASE PLANE
Table 16-pin SOIC (0.150") Package Characteristics
PARAMETER Thermal Impedance, Junction Free-Air Lead Inductance, Self Lead Inductance, Mutual Lead Capacitance, Bulk SYMBOL CONDITIONS/DESCRIPTION flow Corner lead Center lead lead adjacent lead lead TYP. UNITS °C/W
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Ordering Information
DEVICE NUMBER FS6011 FS6011 FONT PACKAGE TYPE 16-pin (0.150") SOIC (Small Outline Package) 16-pin (0.150") SOIC (Small Outline Package) OPERATING TEMPERATURE RANGE 70°C (Commercial) 70°C (Commercial) SHIPPING CONFIGURATION Tube Tape-and-Reel
ORDERING CODE
11228-003 11228-005
Copyright 1998 American Microsystems, Inc.
Devices sold covered warranty patent indemnification provisions appearing Terms Sale only. makes warranty, express, statutory implied description, regarding information forth herein regarding freedom described devices from patent infringement. makes warranty merchantability fitness purposes. reserves right discontinue production change specifications prices time without notice. AMI's products intended commercial applications. Applications requiring extended temperature range, unusual environmental requirements, high reliability applications, such military, medical life-support life-sustaining equipment, specifically recommended without additional processing such applications.
American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, 83201, (208) 233-4690, (208) 234-6796, Address: http://www.amis.com E-mail: tgp@amis.com
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'LJLWDO $XGLR9LGHR &ORFN *HQHUDWRU
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Demonstration Board
simple demonstration board DOS-based software available from American Microsystems that illustrates capabilities FS6011. board schematic shown below. Components listed with asterisk required actual application, used here preserve signal integrity with cabling associated with board. cabled interface between computer parallel port (DB25 connector) board (J1) provided. Contact your local sales representative company directly more information.
Figure Board Schematic
SCLK SDATA SLOAD PSEL1 PSEL0 12pF 12pF 27MHz 2.2µF 2.2µF R10* UCLK R11* PCLK CLK27 ACLK 0.1µF 100pF
SCLK SDATA SLOAD
CLK27 ACLK UCLK
FS6011
XOUT XTUNE
PCLK PSEL0 PSEL1
0.1µF
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Contents
Demonstration board Interface cable (DB25 6-pin connector) Data sheet Demonstration software, including: INSTALL.BAT FS6011.BAT FS6011G.BAS 0.75kB 0.24kB 5.3kB
following banner should appear: FS6011 Utility Program PRESS CONTINUE. After pressing key, menu should appear containing list program keys, message that computer parallel (LPT1) port found, address which port found. *********************** FS6011 Pgm. Utility chip (R)efresh chip (I)nitialize (A)clk a(O)ffset (C)lk27 (U)clk (V)cxo vcxo (E)nable (P)clk e(X)it *********************** Refer Table description each key. change frequency desired clock, press appropriate key. keys case sensitive. Refer FS6011 data sheet) Table Table ACLK frequencies, Table UCLK frequencies, Table PCLK frequencies. Observe response selection. Repeated pressing same will scroll through entire range frequencies selected clock, returning initial frequency. Pressing strobes 15-bit message demo board interface cable. response selection shown below: Writing. (0x000) Binary: 000000000000000 where numbers data binary. Note that PCLK frequency changed directly addressing pins (PSEL0 PSEL1) device. Therefore response message will unchanged when selecting (P)CLK key. Press exit demo program.
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Requirements
running MS-DOS Windows 3.1x, with accessible parallel (LPT1) port MS-QBasic later equivalent software) 6.3kB available space drive
Board Setup Software Installation Instructions
appropriate disk drive prompt (A:\) type Install automatically copy demo files drive. NOTE: This demo software requires Microsoft QBasic equivalent run. Make sure directory containing qbasic.exe path statement, move demo files directory containing Basic. Connect Volt power supply board: +5V, BLACK ground. Remove software keys from computer parallel port. Connect supplied interface cable parallel port (DB25 connector) demo board (6-pin connector). Make sure cable facing away from board wire. Connect clock outputs target application board with twisted-pair cable.
Demo Program
Type FS6011 C:\FS6011 prompt Qbasic-based demo program.
'LJLWDO $XGLR9LGHR &ORFN *HQHUDWRU
July 1998
Table Description
Command Refresh Initialize ACLK ACLK Offset UCLK CLK27 000-111 00-11 000-111 00001111 00-11 Bits Range Description Reloads register values into device Initializes register values zero (default setting) Cycles through ACLK frequencies (Table enables disables offspeed mode; adjusts ACLK off-speed high Cycles through UCLK frequencies (Table Switches CLK27 output between VCXO UCLK frequency Digital Coarse tune adjustment VCXO Enables fine tune VCXO XTUNE Cycles through PCLK frequencies PSEL0 PSEL1 pins (Table Exits demo program
Figure Board Silkscreen
Figure Board Traces Component Side
VCXO VCXO Enable PCLK Exit
9-12
Left
Right
Table Cable Interface
Color White Green Blue Brown Black DB25 Signal SCLK SDATA SLOAD PSEL1 PSEL0
Figure Board Traces Solder Side
Right
Left
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'LJLWDO $XGLR9LGHR &ORFN *HQHUDWRU July 1998 Features D

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