HIGH SPEED CMOS SRAM Document Title HIGH SPEED CMOS SRAM Revision

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HIGH SPEED CMOS SRAM Document Title HIGH SPEED CMOS SRAM Revision

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A61L6316 Series
HIGH SPEED CMOS SRAM
Document Title HIGH SPEED CMOS SRAM Revision History
History
Initial issue Final spec. release spec. Change ICC1 from 120mA 220mA (-12) Change ICC1 from 100mA 210mA (-15) Change ISB1 from 12mA Change ICDR from tBE, tBLZ, tBHZ, parameters
Issue Date
July 2000 2001
Remark
Preliminary Final
(May, 2001, Version 1.0)
AMIC Technology, Inc.
A61L6316 Series
HIGH SPEED CMOS SRAM
Features
Center power pinout Supply voltage: -10: 3.3V+10%, -12, -15: 3.3V±10% Access times: 10/12/15 (max.) Current: Operating: -10: 230mA (max) -12: 220mA (max.) -15: 210mA (max.) Standby: TTL: 25mA (max.) CMOS: 12mA (max.) Full static operation, clock refreshing required inputs outputs directly TTL-compatible Common using three-state output Data retention voltage: (min.) Available 44-pin 400mil 44-pin 400mil TSOP(II) forward packages.
General Description
A61L6316 high speed 1,048,576-bit static random access memory organized 65,536 words bits operates power supply voltage from 3.0V 3.6V. built using AMIC's high performance CMOS process. Inputs three-state outputs compatible allow direct interfacing with common system structures. chip enable input provided POWER-DOWN, disable device. byte enable inputs output enable input included easy interfacing. Data retention guaranteed power supply voltage
Configuration
TSOP(II)
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
A61L6316S(V)
(May, 2001, Version 1.0)
AMIC Technology, Inc.
A61L6316 Series
Block Diagram
1,048,576-BIT DECODER
MEMORY ARRAY
COLUMN INPUT DATA CIRCUIT
INPUT DATA CIRCUIT
CONTROL CIRCUIT
(May, 2001, Version 1.0)
AMIC Technology, Inc.
A61L6316 Series
Description SOJ/TSOP(II)
27,42 Symbol
Description Address Inputs Chip Enable Input
I/O0 I/O15
Data Input/Outputs Write Enable Input Byte Enable Input (I/O0 I/O7) Byte Enable Input (I/O8 I/O15) Output Enable Input Power Ground Connection
Recommended Operating Conditions
70°C) Symbol *VCC Parameter Supply Voltage Ground Input High Voltage Input Voltage Output Load Min. -0.3 Typ. Max. Unit
VCCmin: 3.135V
(May, 2001, Version 1.0)
AMIC Technology, Inc.
A61L6316 Series
Absolute Maximum Ratings*
-0.5V +4.6V IN/OUT Volt -0.5V 0.5V Operating Temperature, Topr +70°C Storage Temperature, Tstg -55°C +125°C Power Dissipation, 0.7W Soldering Temp. Time 260°C,
*Comments
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage this device. These stress ratings only. Functional operation this device these other conditions above those indicated operational sections this specification implied intended. Exposure absolute maximum rating conditions extended periods affect device reliability.
Electrical Characteristics 70°C, -10: 3.3V+10%, -5%; -12, -15: 3.3V±10%)
Symbol Parameter A61L6316-10 Min. Input Leakage Output Leakage Max. A61L6316-12 Min. Max. A61L6316-15 Min. Max. VIH, VI/O VIL, II/O Min. Cycle, Duty 100% 0.2V, -0.2V 0.2V Unit Conditions
ICC1
Dynamic Operating Current
ISB1
Standby Power Supply Current
Output Voltage Output High Voltage
Notes: -3.0V pulses less than ICC1 dependent output loading, cycle rates, Read/Write patterns.
(May, 2001, Version 1.0)
AMIC Technology, Inc.
A61L6316 Series
Truth Table
I/O0 I/O7 Mode selected Read Read High Write Write Write/Hi High High selected
I/O8 I/O15 Mode selected Read High Read Write Write/Hi Write High High selected
Current ISB1, ICC1, ICC2, ICC1, ICC2, ICC1, ICC2, ICC1, ICC2, ICC1, ICC2, ICC1, ICC2, ICC1, ICC2, ICC1, ICC2, ISB1,
Note:
Capacitance 25°C, 1.0MHz)
Symbol CIN* CI/O* Parameter Input Capacitance Input/Output Capacitance Min. Max. Unit Conditions VI/O
These parameters sampled 100% tested.
(May, 2001, Version 1.0)
AMIC Technology, Inc.
A61L6316 Series
Characteristics +70°C, -10: 3.3V+10%, -5%; -12, -15: 3.3V±10%)
Symbol Parameter A61L6316-10 Min. Read Cycle tACE tCLZ tOLZ tBLZ tCHZ tBHZ tOHZ Read Cycle Time Address Access Time Chip Enable Access Time Byte Enable Access Time Output Enable Output Valid Chip Enable Output Output Enable Output Byte Enable Output Chip Disable Output High Byte Disable Output High Output Disable Output High Output Hold from Address Change Max. A61L6316-12 Min. Max. A61L6316-15 Min. Max. Unit
Write Cycle tWHZ Write Cycle Time Chip Enable Write Byte Enable Write Address Setup Time Write Address Valid Write Write Pulse Width Write Recovery Time Write Output High Data Write Time Overlap Data Hold from Write Time Output Active from Write
Notes: tCHZ, tBHZ, tOHZ tWHZ defined time which outputs achieve open circuit condition referred output voltage levels.
(May, 2001, Version 1.0)
AMIC Technology, Inc.
A61L6316 Series
Timing Waveforms
Read Cycle 1(1,
Address
DOUT
Read Cycle 2(1,
Address
tACE tCLZ
tCHZ
tBLZ5
tBHZ5
tOHZ5
tOLZ DOUT
Notes:
high Read Cycle. Device continuously enabled VIL, and, VIL. Address valid prior coincident with and, transition low. VIL. Transition measured ±200mV from steady state. This parameter sampled 100% tested.
(May, 2001, Version 1.0)
AMIC Technology, Inc.
A61L6316 Series
Timing Waveforms (continued)
Write Cycle (Write Enable Controlled)
Address tWR3
tAS1
tWP2
DATA tWHZ4
DATA
(May, 2001, Version 1.0)
AMIC Technology, Inc.
A61L6316 Series
Timing Waveforms (continued)
Write Cycle (Chip Enable Controlled)
Address tCW2 tWR3
DATA tWHZ4
DATA
(May, 2001, Version 1.0)
AMIC Technology, Inc.
A61L6316 Series
Timing Waveforms (continued)
Write Cycle (Byte Enable Controlled)
Address
tWR3
tAS1
tBW2
DATA tWHZ4 DATA
Notes: measured from address valid beginning Write. Write occurs during overlap (tWP, tBW) and, measured from earliest and, going high Write cycle. level high low. Transition measured ±200mV from steady state. This parameter sampled 100% tested.
(May, 2001, Version 1.0)
AMIC Technology, Inc.
A61L6316 Series
Test Conditions
Input Pulse Levels Input Rise Fall Time Input Output Timing Reference Levels Output Load 3.0V Figures
+3.3V RL=50 VT=1.5V Including scope jig.
OUTPUT ZO=50
5pF*
Figure Output Load
Figure Output Load tCLZ, tOLZ, tCHZ, tOHZ, tWHZ,
Data Retention Characteristics 70°C)
Symbol Parameter Data Retention Min. Max. Unit Conditions
0.2V
ICCDR
Data Retention Current
2.0V 0.2V 0.2V 0.2V
tCDR
Chip Disable Data Retention Time Operation Recovery Time
TRC*
Retention Waveform
Read Cycle Time
(May, 2001, Version 1.0)
AMIC Technology, Inc.
A61L6316 Series
Data Retention Waveform
DATA RETENTION MODE 3.0V tCDR 0.2V 3.0V
Ordering Information
Part A61L6316S-10 A61L6316V-10 A61L6316S-12 A61L6316V-12 A61L6316S-15 A61L6316V-15 TSOP(II) TSOP(II) TSOP(II) Access Time (ns) Operating Current Max. (mA) Standby Current Max. (mA) Package
(May, 2001, Version 1.0)
AMIC Technology, Inc.
A61L6316 Series
Package Information Outline Dimensions
unit: inches/mm
0.004
0.025"
Seating Plane
Symbol
Dimensions inches 0.128 0.082 0.105 0.015 0.026 0.007 1.120 0.435 0.394 0.138 0.110 0.028 1.125 0.440 0.400 0.370 0.050 0.030 0.035 0.040 0.148 0.115 0.020 0.032 0.013 1.130 0.445 0.405
Dimensions 3.25 2.08 2.67 0.38 0.66 0.18 28.45 11.05 10.01 3.51 2.79 0.71 28.58 11.18 10.16 9.40 1.27 0.76 0.89 1.02 3.76 2.92 0.51 0.81 0.21 28.70 11.30 10.29
Notes: maximum value dimension includes flash. Dimension does include resin fins. Dimension Board surface mount pitch design reference only.
(May, 2001, Version 1.0)
AMIC Technology, Inc.
A61L6316 Series
Package Information TSOP (Type Outline Dimensions
unit: inches/mm
Dimensions inches
Dimensions 0.05 0.95 0.30 0.12 18.28 11.56 10.03 0.49 1.00 18.41 0.805 11.76 10.16 0.59 0.80 0.80 1.20 0.15 1.05 0.45 0.21 18.54 11.96 10.29 0.69
Symbol
0.002 0.037 0.012 0.005 0.720 0.455 0.395 0.019
0.039 0.725 0.032 0.463 0.400 0.023 0.031 0.031
0.047 0.006 0.041 0.018 0.008 0.730 0.471 0.405 0.027
0.004
0.10
Notes: maximum value dimension includes flash. Dimension does include resin fins. Dimension includes flash.
(May, 2001, Version 1.0)
AMIC Technology, Inc.

HIGH SPEED CMOS SRAM Document Title HIGH SPEED CMOS SRAM Revision

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