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AMD Geode SC2200 Processor Data Book

Publication ID: Revision 5.1

AMD Geode SC2200 Processor Data Book
March 2004
Publication ID: Revision 5.1
AMD Geode SC2200 Processor Data Book
Contacts www.amd.com pcs.support@amd.com Trademarks AMD, the AMD Arrow logo, and combinations thereof, and Geode and Virtual System Architecture are trademarks of Advanced Micro Devices, Inc. Microsoft and Windows are registered trademarks of Microsoft Corporation in the United States and other jurisdictions. MMX is trademark of Intel Corporation. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
AMD Geode SC2200 Processor Data Book
Contents
Revision 5.1
Contents
AMD Geode SC2200 Processor Data Book
Revision 5.1
Contents
Appendix A
A.1 A.2
AMD Geode SC2200 Processor Data Book
List of Figures
Revision 5.1
List of Figures
AMD Geode SC2200 Processor Data Book
Revision 5.1
List of Figures
Figure 7-5. Figure 7-6. Figure 7-7. Figure 7-8. Figure 7-9. Figure 7-10. Figure 7-11. Figure 7-12. Figure 7-13. Figure 7-14. Figure 7-15. Figure 9-1. Figure 9-2. Figure 9-3. Figure 9-4. Figure 9-5. Figure 9-6. Figure 9-7. Figure 9-8. Figure 9-9. Figure 9-10. Figure 9-11. Figure 9-12. Figure 9-13. Figure 9-14. Figure 9-15. Figure 9-16. Figure 9-17. Figure 9-18. Figure 9-19. Figure 9-20. Figure 9-21. Figure 9-22. Figure 9-23. Figure 9-24. Figure 9-25. Figure 9-26. Figure 9-27. Figure 9-28. Figure 9-29. Figure 9-30. Figure 9-31. Figure 9-32. Figure 9-33. Figure 9-34. Figure 9-35. Figure 9-36. Figure 9-37. Figure 9-38. Figure 9-39. Figure 9-40. Figure 9-41. Figure 9-42. Figure 9-43. Figure 9-44.
AMD Geode SC2200 Processor Data Book
List of Figures
Revision 5.1
Figure 9-45. Figure 9-46. Figure 9-47. Figure 9-48. Figure 9-49. Figure 9-50. Figure 9-51. Figure 9-52. Figure 9-53. Figure 9-54. Figure 9-55. Figure 9-56. Figure 9-57. Figure 9-58. Figure 10-1. Figure 10-2. Figure 10-3.
AMD Geode SC2200 Processor Data Book
Revision 5.1
List of Figures
AMD Geode SC2200 Processor Data Book
List of Tables
Revision 5.1
List of Tables
AMD Geode SC2200 Processor Data Book
Revision 5.1
List of Tables
Table 5-27. Table 5-28. Table 5-29. Table 5-30. Table 5-31. Table 5-32. Table 5-33. Table 5-34. Table 5-35. Table 5-36. Table 5-37. Table 5-38. Table 5-39. Table 5-40. Table 5-41. Table 5-42. Table 5-43. Table 5-44. Table 5-45. Table 5-46. Table 5-47. Table 5-48. Table 5-49. Table 5-50. Table 5-51. Table 5-52. Table 5-53. Table 5-54. Table 5-55. Table 5-56. Table 5-57. Table 5-58. Table 5-59. Table 5-60. Table 5-61. Table 5-62. Table 6-1. Table 6-2. Table 6-3. Table 6-4. Table 6-5. Table 6-6. Table 6-7. Table 6-8. Table 6-9. Table 6-10. Table 6-11. Table 6-12. Table 6-13. Table 6-14. Table 6-15. Table 6-16. Table 6-17. Table 6-18. Table 6-19.
AMD Geode SC2200 Processor Data Book
List of Tables
Revision 5.1
Table 6-20. Table 6-21. Table 6-22. Table 6-23. Table 6-24. Table 6-25. Table 6-26. Table 6-27. Table 6-28. Table 6-29. Table 6-30. Table 6-31. Table 6-32. Table 6-33. Table 6-34. Table 6-35. Table 6-36. Table 6-37. Table 6-38. Table 6-39. Table 6-40. Table 6-41. Table 6-42. Table 6-43. Table 6-44. Table 6-45. Table 6-46. Table 6-47. Table 6-48. Table 6-49. Table 7-1. Table 7-2. Table 7-3. Table 7-4. Table 7-5. Table 7-6. Table 7-7. Table 7-8. Table 8-1. Table 9-1. Table 9-2. Table 9-3. Table 9-4. Table 9-5. Table 9-6. Table 9-7. Table 9-8. Table 9-9. Table 9-10. Table 9-11. Table 9-12. Table 9-13. Table 9-14. Table 9-15. Table 9-16.
AMD Geode SC2200 Processor Data Book
Revision 5.1
List of Tables
Table 9-17. Table 9-18. Table 9-19. Table 9-20. Table 9-21. Table 9-22. Table 9-23. Table 9-24. Table 9-25. Table 9-26. Table 9-27. Table 9-28. Table 9-29. Table 9-30. Table 9-31. Table 9-32. Table 9-34. Table 9-35. Table 9-36. Table 9-37. Table 9-38. Table 9-39. Table 9-40. Table 9-41. Table 9-42. Table 9-43. Table 9-44. Table 9-45. Table 9-46. Table 10-1. Table 10-2. Table A-1. Table A-2.
AMD Geode SC2200 Processor Data Book
AMD Geode SC2200 Processor
Revision 5.1
1.0AMD Geode SC2200 Processor
1.1 General Description
Memory Controller 2D Graphics Accelerator PCI Bus Controller Display Controller
Video Processor
CRT I / F Video Scaling Config. Block Video Input Port (VIP) Host Interface Fast-PCI Bus Clock & Reset Logic Fast X-Bus Video Mixer TFT I / F
CPU Core
IDE I / F Bridge USB PCI / Sub-ISA Bus I / F GPIO Audio Codec I / F LPC I / F X-Bus PCI Bus
Core Logic
PIT PIC DMAC Pwr Mgmnt Configuration ISA Bus I / F
Parallel Port ACB1 I / F
SuperI / O
ACB2 I / F UART1 UART2
UART3 & IR
Figure 1-1. Block Diagram
AMD Geode SC2200 Processor Data Book
Revision 5.1
AMD Geode SC2200 Processor
Features
Video Processor Module
Video Accelerator:
General Features
32-Bit x86 processor, up to 300 MHz, with MMX
instruction set support
Memory controller with 64-bit SDRAM interface 2D graphics accelerator CRT controller with hardware video accelerator CCIR-656 video input port with direct video for full
- Flexible video scaling support of up to 8x (horizontally and vertically) - Bilinear interpolation filters (with two taps, and eight phases) to smooth output video
Video / Graphics Mixer:
screen display
PC / AT functionality PCI bus controller IDE interface, two channels USB, three ports, OHCI (OpenHost Controller Interface)
- 8-bit value alpha blending - Three blending windows with constant alpha value - Color key
Video Input Port (VIP):
version 1.0 compliant
Audio, AC97 / AMC97 version 2.0 compliant Virtual System Architecture (VSA) technology support Power management, ACPI (Advanced Configuration
- Video capture or display - CCIR-656 and VESA Video Interface Port v1.1 compliant - Lock display timing to video input timing (GenLock) - Able to transfer video data into main memory - Direct video transfer for full screen display - Separate memory location for VBI
CRT Interface:
Power Interface) version 1.0 compliant
Package:
Uses three 8-bit DACs Supports up to 135 MHz 1280x1024 non-interlaced CRT @ 8 bpp, up to 75 Hz 1024x768 non-interlaced CRT @ 16 bpp, up to 85 Hz
- 432-Terminal EBGA (Enhanced Ball Grid Array) - 481-Terminal TEPBGA (Thermally Enhanced Plastic Ball Grid Array) GX1 Processor Module
CPU Core:
TFT Interface:
- 32-Bit x86, 300 MHz, with MMX compatible instruction set support - 16 KB unified L1 cache - Integrated FPU (Floating Point Unit) - Re-entrant SMM (System Management Mode) enhanced for VSA
2D Graphics Accelerator:
- Direct connection to TFT panels - 800x600 non-interlaced TFT @ 16 bpp graphics, up to 85 Hz - 1024x768 non-interlaced TFT @ 16 bpp graphics, up to 75 Hz - TFT on IDE: FPCLK max is 40 MHz - TFT on Parallel Port: FPCLK max is 80 MHz Core Logic Module
Audio Codec Interface:
- AC97 / AMC97 (Rev. 2.0) codec interface - Six DMA channels
PC / AT Functionality:
Accelerates BitBLTs, line draw and text Supports all 256 raster operations Supports transparent BLTs Runs at core clock frequency
Memory Controller:
- Programmable Interrupt Controller (PIC), 8259A-equivalent - Programmable Interval Timer (PIT), 8254-equivalent - DMA Controller (DMAC), 8237-equivalent
Power Management:
- 64-Bit SDRAM interface - 66 MHz to 100 MHz frequency range - Direct interface with CPU / cache, display controller and 2D graphic accelerator - Supports clock suspend and power-down / self-refresh - Up to two banks of SDRAM (8 devices total) or one SODIMM
Display Controller:
- Hardware graphics frame buffer compress / decompress - Hardware cursor, 32x32 pixels
ACPI v1.0 compliant Sx state control of three power planes Cx / Sx state control of clocks and PLLs Thermal event input Wakeup event support: - Three general-purpose events - AC97 codec event - UART2 RI# signal - Infrared (IR) event
AMD Geode SC2200 Processor Data Book
AMD Geode SC2200 Processor General Purpose I / Os (GPIOs):
Revision 5.1
Other Features
High-Resolution Timer:
- 27 multiplexed GPIO signals
Low Pin Count (LPC) Bus Interface:
- 32-Bit counter with 1 µs count interval
WATCHDOG Timer:
- Specification v1.0 compatible
PCI Bus Interface:
- Interfaces to INTR, SMI, Reset
Clocks:
PCI v2.1 compliant with wakeup capability 32-Bit data path, up to 33 MHz Glueless interface for an external PCI device Fixed priority 3.3V signal support only
Sub-ISA Bus Interface:
- Up to 16 MB addressing - Supports a chip select for ROM or Flash EPROM boot device - Supports either: - M-Systems DiskOnChip DOC2000 Flash file system - NAND EEPROM - Supports up to two chip selects for external I / O devices - 8-Bit (optional 16-bit) data bus width - Shares balls with PCI signals - Is not a subtractive agent
IDE Interface:
- Input (external crystals): - 32.768 KHz (internal clock oscillator) - 27 MHz (internal clock oscillator) - Output: - AC97 clock (24.576 MHz) - Memory controller clock (66 MHz to 100 MHz) - PCI clock (33 MHz)
JTAG Testability:
- Bypass, Extest, Sample / Preload, IDcode, Clamp, HiZ
Voltages:
- Internal logic: - 233 MHz @ 1.8V - 266 MHz @ 1.8V - 300 MHz @ 2.1V - Standby logic: - 233 MHz @ 1.8V - 266 MHz @ 1.8V - 300 MHz @ 2.1V - I / O: 3.3V - Standby I / O: 3.3V - Battery (if used): 3.0V
- Two IDE channels for up to four external IDE devices - Supports ATA-33 synchronous DMA mode transfers, up to 33 MB / s
Universal Serial Bus (USB):
- USB OpenHCI v1.0 compliant - Three ports SuperI / O Module
Real-Time Clock (RTC):
- DS1287, MC146818 and PC87911 compatible - Multi-century calendar
ACCESS.bus (ACB) Interface:
- Two ACB interface ports
Parallel Port:
- EPP 1.9 compliant - IEEE 1284 ECP compliant, including level 2
Serial Port (UART):
- UART1, 16550A compatible (SIN, SOUT, BOUT pins), used for SmartCard interface - UART2, 16550A compatible - Enhanced UART with fast Infrared (IR)
AMD Geode SC2200 Processor Data Book
Revision 5.1
AMD Geode SC2200 Processor
AMD Geode SC2200 Processor Data Book
Architecture Overview
Revision 5.1
2.0Architecture Overview
As illustrated in Figure 1-1 on page 13, the SC2200 processor contains the following modules in one integrated device: · GX1 Module: - Combines advanced CPU performance with MMX support, fully accelerated 2D graphics, a 64-bit synchronous DRAM (SDRAM) interface and a PCI bus controller. Integrates GX1 silicon revision 8.1.1. · Video Processor Module: - A low-power CRT and TFT support module with a video input port, and a hardware video accelerator for scaling, filtering and color space conversion. · Core Logic Module: - Includes PC / AT functionality, an IDE interface, a Universal Serial Bus (USB) interface, ACPI 1.0 compliant power management, and an audio codec interface. · SuperI / O Module: - Includes two Serial Ports, an Infrared (IR) Port, a Parallel Port, two ACCESS.bus interfaces, and a Real-Time Clock (RTC). The device ID of the SC2200 processor is contained in the GX1 module. Software can detect the revision by reading the DIR0 and DIR1 Configuration registers (see Configuration registers in the AMD Geode GX1 Processor Data Book). The AMD Geode SC2200 Processor Specification Update document contains the specific values.
Memory Controller
GX1 Module
The GX1 processor (silicon revision 8.1.1) is the central module of the SC2200. For detailed information regarding the GX1 module, refer to the AMD Geode GX1 Processor Data Book and the AMD Geode GX1 Processor Silicon Revision 8.1.1 Specification Update document.
AMD Geode SC2200 Processor Data Book
Revision 5.1
Architecture Overview
Table 2-1. SC2200 Memory Controller Register Summary
Table 2-2. SC2200 Memory Controller Registers
Ratio does not take effect until the SDCLKSTRT bit (bit 17 of this register) transitions from 0 to 1. 17 SDCLKSTRT (Start SDCLK). Start operating SDCLK using the new ratio and shift value (selected in bits 20:18 of this register). 0: Clear. 1: Enable. This bit must transition from zero (written to zero) to one (written to one) in order to start SDCLK or to change the shift value. 16:8 7:6 RFSHRATE (Refresh Interval). This field determines the number of processor core clocks multiplied by 64 between refresh cycles to the DRAM. By default, the refresh interval is 00h. Refresh is turned off by default. RFSHSTAG (Refresh Staggering). This field determines number of clocks between the RFSH commands to each of the four banks during refresh cycles: 00: 0 SDRAM clocks 01: 1 SDRAM clocks (Default) 10: 2 SDRAM clocks 11: 4 SDRAM clocks Staggering is used to help reduce power spikes during refresh by refreshing one bank at a time. If only one bank is installed, this field must be written as 00.
AMD Geode SC2200 Processor Data Book
Architecture Overview
Revision 5.1
Table 2-2. SC2200 Memory Controller Registers (Continued)
AMD Geode SC2200 Processor Data Book
Revision 5.1
Architecture Overview
Table 2-2. SC2200 Memory Controller Registers (Continued)
LTMODE (CAS Latency). CAS latency is the delay, in SDRAM clock cycles, between the registration of a read command and the availability of the first piece of output data. This parameter significantly affects system performance. Optimal setting should be used. If an SODIMM is used, BIOS can interrogate EEPROM across the ACCESS.bus interface to determine this value: 000: Reserved 001: Reserved 010: 2 CLK 011: 3 CLK 100: 4 CLK 101: 5 CLK 110: 6 CLK 111: 7 CLK
RAS (ACT to PRE Command Period, tRAS). Minimum number of SDRAM clocks between ACT and PRE commands:
RSVD (Reserved). Write as 0. RP (PRE to ACT Command Period, tRP). Minimum number of SDRAM clocks between PRE and ACT commands: 000: Reserved 001: 1 CLK 010: 2 CLK 011: 3 CLK 100: 4 CLK 101: 5 CLK 110: 6 CLK 111: 7 CLK
RSVD (Reserved). Write as 0. RCD (Delay Time ACT to READ / WRT Command, tRCD). Minimum number of SDRAM clock between ACT and READ / WRT commands. This parameter significantly affects system performance. Optimal setting should be used: 000: Reserved 001: 1 CLK 010: 2 CLK 011: 3 CLK 100: 4 CLK 101: 5 CLK 110: 6 CLK 111: 7 CLK AMD Geode SC2200 Processor Data Book
Architecture Overview
Revision 5.1
Table 2-2. SC2200 Memory Controller Registers (Continued)
Bit 11 10:8 Description RSVD (Reserved). Write as 0. RRD (ACT(0) to ACT(1) Command Period, tRRD). Minimum number of SDRAM clocks between ACT and ACT command to two different component banks within the same module bank. The memory controller does not perform back-to-back Activate commands to two different component banks without a READ or WRITE command between them. Hence, this field should be written as 001. RSVD (Reserved). Write as 0. DPL (Data-in to PRE command period, tDPL). Minimum number of SDRAM clocks from the time the last write datum is sampled till the bank is precharged: 000: Reserved 001: 1 CLK 3:0 Note: 010: 2 CLK 011: 3 CLK 100: 4 CLK 101: 5 CLK 110: 6 CLK 111: 7 CLK
D (Dirty Bit). This bit is read / write accessible. V (Valid Bit). This bit is read / write accessible.
AMD Geode SC2200 Processor Data Book
Revision 5.1
Architecture Overview
Fast-PCI Bus
Video Processor Module
The GX1 module communicates with the Core Logic module via a Fast-PCI bus that can work at up to 66 MHz. The Fast-PCI bus is internal for the SC2200 and is connected to the General Configuration Block (see Section 4.0 on page 87 for details on the General Configuration Block). This bus supports seven bus masters. The requests (REQs) are fixed in priority. The seven bus masters in order of priority are: 1) 2) 3) 4) 5) 6) 7) VIP IDE Channel 0 IDE Channel 1 Audio USB External REQ0# External REQ1#
The Video Processor provides high resolution and graphics for a CRT or TFT / DSTN interface. The following subsections provide a summary of how the Video Processor interfaces with the other modules of the SC2200. For detailed information about the Video Processor, see Section 7.0 "Video Processor Module" on page 325.
GX1 Module Interface
Video Input Port
Display
Core Logic Module Interface
The Video Processor interfaces to the Core Logic module for accessing PCI function configuration registers.
CRT DAC
The Video Processor drives three CRT DACs with up to 135M pixels per second. The interface for these DACs can be monitored via external balls of the SC2200. For more information, see Section 3.4.4 "CRT / TFT Interface Signals" on page 67.
AMD Geode SC2200 Processor Data Book
Architecture Overview
Revision 5.1
Core Logic Module
The Core Logic module is described in detail in Section 6.0 "Core Logic Module" on page 157. The Core Logic module is connected to the Fast-PCI bus. It uses signal AD28 as the IDSEL for all PCI configuration functions except for USB which uses AD29.
Other Interfaces of the Core Logic Module
The following interfaces of the Core Logic module are implemented via external balls of the SC2200. Each interface is listed below with a reference to the descriptions of the relevant balls. · IDE: See Section 3.4.9 "IDE Interface Signals" on page 75. · AC97: See Section 3.4.14 "AC97 Audio Interface Signals" on page 80. · PCI: See Section 3.4.6 "PCI Bus Interface Signals" on page 68. · USB: See Section 3.4.10 "Universal Serial Bus (USB) Interface Signals" on page 76. The USB function uses signal AD29 as the IDSEL for PCI configuration. · LPC: See Section 3.4.8 "Low Pin Count (LPC) Bus Interface Signals" on page 74. · Sub-ISA: See Section 3.4.7 "Sub-ISA Interface Signals" on page 73, Section 6.2.5 "Sub-ISA Bus Interface" on page 163, and Section 4.2 "Multiplexing, Interrupt Selection, and Base Address Registers" on page 88 · GPIO: See Section 3.4.16 "GPIO Interface Signals" on page 82. · More detailed information about each of these interfaces is provided in Section 6.2 "Module Architecture" on page 158. · Super / IO Block Interfaces: See Section 4.2 "Multiplexing, Interrupt Selection, and Base Address Registers" on page 88, Section 3.4.5 "ACCESS.bus Interface Signals" on page 68, Section 3.4.13 "Fast Infrared (IR) Port Interface Signals" on page 79, and Section 3.4.12 "Parallel Port Interface Signals" on page 78.
SuperI / O Module
The SuperI / O (SIO) module is PC98 and ACPI compliant. It offers a single-cell solution to the most commonly used ISA peripherals. The SIO module incorporates: two Serial Ports, an Infrared Communication Port that supports FIR, MIR, HP-SIR, Sharp-IR, and Consumer Electronics-IR, a full IEEE 1284 Parallel Port, two ACCESS.bus Interface (ACB) ports, System Wakeup Control (SWC), and a Real-Time Clock (RTC) that provides RTC timekeeping.
AMD Geode SC2200 Processor Data Book
Revision 5.1
Architecture Overview
Clock, Timers, and Reset Logic
In addition to the four main modules (i.e., GX1, Core Logic, Video Processor and SIO) that make up the SC2200, the following blocks of logic have also been integrated into the SC2200: · Clock Generators as described in Section 4.5 "Clock Generators and PLLs" on page 99. · Configuration Registers as described in Section 4.2 "Multiplexing, Interrupt Selection, and Base Address Registers" on page 88. · A WATCHDOG timer as described in Section 4.3 "WATCHDOG" on page 95. · A High-Resolution timer as described in Section 4.4 "High-Resolution Timer" on page 97.
2.5.1.1 Power-On Reset Power-on reset is triggered by assertion of the POR# signal. Upon power-on reset, the following things happen: · Strap balls are sampled. · PLL4, PLL5, and PLL6 are reset, disabling their output. When the POR# signal is negated, the clocks lock and then each PLL outputs its clock. PLL6 is the last clock generator to output a clock. See Section 4.5 "Clock Generators and PLLs" on page 99. · Certain WATCHDOG and High-Resolution Timer register bits are cleared. 2.5.1.2 System Reset System reset causes signal PCIRST# to be issued, thus triggering a reset of all PCI and LPC agents. A system reset is triggered by any of the following events: · Power-on, as indicated by POR# signal assertion. · A WATCHDOG reset event (see Section 4.3.2 "WATCHDOG Registers" on page 96). · Software initiated system reset.
Reset Logic
This section provides a description of the reset flow of the SC2200.
AMD Geode SC2200 Processor Data Book
Signal Definitions
Revision 5.1
3.0Signal Definitions
This section defines the signals and describes the external interface of the SC2200 processor. Figure 2-1 shows the signals organized by their functional groups. Where signals are multiplexed, the default signal name is listed first and is separated by a plus sign (+). A slash ( / ) in a signal name means that the function is always enabled and available (i.e., cycle multiplexed).
System Interface
HSYNC VSYNC VREF SETRES RED, GREEN, BLUE
CRT Interface
Straps
Memory Interface
AMD Geode SC2200 Processor
ACCESS.bus Interface
AB1C+GPIO20+DOCCS# AB1D+GPIO1+IOCS1# GPIO12+AB2C GPIO13+AB2D ACK#+TFTDE AFD# / DSTRB#+TFTD2 BUSY / WAIT#+TFTD3 ERR#+TFTD4 INIT#+TFTD5 PD7+TFTD13 PD6+TFTD1 PD5:0+TFTD11:6 PE+TFTD14 SLCT+TFTD15 SLIN# / ASTRB#+TFTD16 STB# / WRITE#+TFTD17 VPD7:0 VPCKIN
IDE / TFT Interface
Parallel Port / TFT Interface
Video Port Interface
Note:
Straps are not the default signal, shown with system signals for reader convenience. However, they are also listed with the appropriate functional group.
Figure 3-1. Signal Groups
AMD Geode SC2200 Processor Data Book 25
Revision 5.1
Signal Definitions
USB Interface
Serial Ports (UARTs) / IDE Interface
IR Port Interface
AC97 Audio Interface
Power Management Interface
JTAG Interface
Sub-ISA / PCI Bus Interface
GPIO / LPC Bus Interface
Test and Measurement Interface
Figure 3-1.
The remaining subsections of this chapter describe:
Signal Groups (Continued)
· Section 3.3 "Multiplexing Configuration": Lists multiplexing options and their configurations. · Section 3.4 "Signal Descriptions": Detailed descriptions of each signal according to functional group.
· Section 3.1 "Ball Assignments": Provides a ball assignment diagram and tables listing the signals sorted according to ball number and alphabetically by signal name. · Section 3.2 "Strap Options": Several balls are read at power-up that set up the state of the SC2200. This section provides details regarding those balls.
AMD Geode SC2200 Processor Data Book
Signal Definitions
Revision 5.1
Ball Assignments
Table 3-1. Signal Definitions Legend
Mnemonic A AVSS AVCC GCB Definition Analog Ground ball: Analog Power ball: Analog General Configuration Block registers. Refer to Section 4.0 "General Configuration Block" on page 87. Location of the General Configuration Block cannot be determined by software. See the AMD Geode SC2200 Processor Specification Update. I I / O MCRx Input ball Bidirectional ball Miscellaneous Configuration Register Bit x: A register, located in the GCB. Refer to Section 4.1 "Configuration Block Addresses" on page 87 for further details. Output ball Open-drain Pull-down Pin Multiplexing Register Bit x: A register, located in the GCB, used to configure balls with multiple functions. Refer to Section 4.1 "Configuration Block Addresses" on page 87 for further details. Pull-up TRI-STATE Power ball: 1.2V Power ball: 3.3V Ground ball The # symbol in a signal name indicates that the active or asserted state occurs when the signal is at a low voltage level. Otherwise, the signal is asserted when at a high voltage level. A / in a signal name indicates both functions are always enabled (i.e., cycle multiplexed). A + in signal name indicates the function is available on the ball, but that either strapping options or register programming is required to select the desired function.
The SC2200 is highly configurable as illustrated in Figure 3-1 on page 25. Strap options and register programming are used to set various modes of operation and specific signals on specific balls. This section describes which signals are available on which balls and provides configuration information: · Figure 3-2 on page 28 and Figure 3-3 on page 43: Illustrations of EBGA and TEPBGA ball assignments. · Table 3-2 on page 29 and Table 3-4 on page 44: Lists signals according to ball number. Power Rail, Signal Type, Buffer Type and, where relevant, Pull-Up or PullDown resistors are indicated for each ball in this table. For multiplexed balls, the necessary configuration for each signal is listed as well. · Table 3-3 on page 39 and Table 3-5 on page 54: Quick reference signal list sorted alphabetically - listing all signal names and ball numbers.The tables in this chapter use several common abbreviations. Table 3-1 lists the mnemonics and their meanings Notes: 1) For each GPIO signal, there is an optional pull-up resistor on the relevant ball. After system reset, the pull-up is present. This pull-up resistor can be disabled via registers in the Core Logic module. The configuration is without regard to the selected ball function (except for GPIO12, GPIO13, and GPIO16). Alternate functions for GPIO12, GPIO13, and GPIO16 control pull-up resistors. For more information, see Section 6.4.1 "Bridge, GPIO, and LPC Registers - Function 0" on page 206. 2) Configuration settings listed in this table are with regard to the Pin Multiplexing Register (PMR). See Section 4.2 "Multiplexing, Interrupt Selection, and Base Address Registers" on page 88 for a detailed description of this register.
O OD PD PMRx
PU TS VCORE VIO VSS #
AMD Geode SC2200 Processor Data Book
Revision 5.1
Signal Definitions
VSS VIO
VIO VSS
AD3 VSS AD4 VIO AD0 AD2 IDAT13 IDAT10 IDAT8 IRST# IDAT5 IDAT1 IORDY0 IAD0 ICS0# GP18
AD29 AD26 AD22 AD19 AD16 CBE3# SERR# CBE1# AD14 AD12 CBE0# AD5 AD31 AD27 DVSL# VIO
VSS VIO VPLL3 LED#
VSS TRDY# PERR# AD15
AD7 AD8
VSS IDAT15 IDAT12 VIO
IDAT7 IDAT4 IDAT0
VSS SOUT1 PWRE TEST2 VSS VIO X32I
RQ0# AD30
AD28 AD24 AD21 AD17 IRDY# LOCK# PAR
AD13 AD11 AD10
AD6 ICS1# IAD2 IDAT14 IDAT11 IDAT9 IIOR0# IDAT6 IDAT3 IDRQ0 IDCK0# IAD1 OVCR# TEST1 VCORE VSS VCORE VSS
PRST# GNT1# PCK0 GNT0# AD25 AD20 AD18 CBE2# STP#
VSS VCORE VSS VCORE VSS VCORE AD1 VCORE VSS
IDAT2 IIOW0# IRQ14 SIN1 X27O TEST0 X32O VBAT
FRM# PCLK REQ1# PCK1
AVSSP3 PBTN# OCTL# GPW0 THRM# VSB GPW1 GPW2 VSS PCNT1 VIO PCNT2
IOR# WR#
VSS VIO
IOW# RMCS# GP20 GP19
TRDE# GP1
VSBL CK32 GP11 SDIN2 IRRX1 POR# MD0 VSS MD2 MD3 VSS VIO MD1 MD4 MD6 DQM0
HSYN VSYN IRTX GP17 RED VSSCRT VCCCRT VSS AVSSCRT VSS AVCCCRT VCORE VCCCRT VIO GREEN VSS AVCCCRT BLUE AVSSCRT VCORE VREF STRS AVSSCRT VSS VPLL2 BSY PD7 PD4 VSS AVSSP2 VCORE VIO VSS PD5 PE SLCT
VCORE MD5 VSS MD7
VCORE WEA# CASA# RASA#
ACK# VCORE PD6 VSS
SLIN# PD3 PD1 PD0 VIO VSS
PD2 VCORE INIT# VSS
AMD Geode SC2200 Processor
BA0 VSS
BA1 MA0
VCORE MA10
DQM4 MA2 VCORE MA1 VCORE MD33 VSS VSS MD32
MD36 MD35 MD34
VCORE MD39 MD38 MD37 VSS MD46 VIO VSS MD47 MD45
ERR# VCORE NC VIO NC VSS VSS NC
VCORE MD44 VSS
STB# AFD# NC NC NC INTB# NC NC VIO VSS
MD41 MD42 MD43
CKEA SDCK0 DQM5 MD40 MA6 MA7 MA4 MA8 VIO VSS MA9 MA5 DQM1
INTA# D+P3 D-P3 AVCCUSB GP9 GP7 SIN2 TDP TDO VPCKI VPD4 VPD0
(Top View)
VSS VCORE VSS VCORE VSS VCORE SDCK1 VCORE VSS VCORE VSS VCORE VSS
MD14 MD15 MA11 MD9
AVSSUSB D-P2 D-P1 D+P2 D+P1 GP10 VIO VSS GP8 GP6 VIO
MD8 MD13
MD28 MD55 MD51 MD48 MD23 SDCKO MA12 MD11 MD10 VIO SDCKI MD12 VSS VIO VIO VSS
TMS VPD7 VPD6 VPD2 GP38 GP35 GP32 GP12 AB1C ACCK ACRT# SDCK3 MD56 MD58 MD61 DQM7 DQM3 MD25 MD29 MD54 MD50 DQM6 MD22 MD19
VSS SOUT2 TRST# TDI VIO TDN
VPD1 GP37 GP34
VSS SDATO SDATI
MD59 MD62
MD26 MD30 MD53
MD21 MD18 CS1#
TCK GTST VPD5 VPD3 GP39 GP36 GP33 GP13 AB1D SYNC BITCK GP16 GXCK MD57 MD60 MD63 SDCK2 MD24 MD27 MD31 MD52 MD49 DQM2 MD20 MD17 MD16
Note:
Figure 3-2. 432-EBGA Ball Assignment Diagram
AMD Geode SC2200 Processor Data Book
Signal Definitions
Revision 5.1
Table 3-2. 432-EBGA Ball Assignment - Sorted by Ball Number
INPCI, I / O (PU22.5) ODPCI I / O (PU22.5) I / O (PU22.5) I / O O I / O O I / O (PU22.5) I / O (PU22.5) I / O O I / O O I / O O I / O O I / O O INPCI, OPCI INPCI, OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI
Cycle Multiplexed
AMD Geode SC2200 Processor Data Book
Revision 5.1
Signal Definitions
Table 3-2.
432-EBGA Ball Assignment - Sorted by Ball Number (Continued)
I / O Buffer1 Power Rail Configuration (PU / PD) Type I / O O PWR GND I / O O I / O O GND PWR GND I / O O I / O O PWR GND I / O I I / O O I / O O PWR GND O INPCI, OPCI OPCI --INPCI, OPCI OPCI INPCI, OPCI OPCI ---INTS1, TS1 / 4 O1 / 4 INTS1, TS1 / 4 O1 / 4 --INTS1, TS1 / 4 INTS INTS1, TS1 / 4 O1 / 4 INTS1, TS1 / 4 O1 / 4 --O8 / 8 VIO Cycle Multiplexed
I INSTRP (PD100) O O I / O GND PWR O1 / 4 O2 / 5 INT, TS2 / 5 ---
INPCI I (PU22.5) I / O I / O PWR INPCI, OPCI INPCI, OPCI --
AMD Geode SC2200 Processor Data Book
Signal Definitions
Revision 5.1
Table 3-2.
432-EBGA Ball Assignment - Sorted by Ball Number (Continued)
I INSTRP (PD100) O OPCI
INSTRP I (PD100) O OPCI
INSTRP I (PD100) I / O I / O I / O O I / O O I / O (PU22.5) I / O (PU22.5) INPCI, OPCI INPCI, OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI INPCI, OPCI
I INSTRP (PD100) GND I (PU100) O I / O (PU100) -INBTN OD14 INTS, TS2 / 14
AMD Geode SC2200 Processor Data Book
Revision 5.1
Signal Definitions
Table 3-2.
Ball No. F1 Signal Name IOR# DOCR# GPIO14 F2 F3 VSS RD# CLKSEL0 F4 AD23 A23 F28 F29 F30 F314, 5 G1 G2 G3 THRM# VSB VSS PWRCNT1 WR# VIO IOW# DOCW# GPIO15 G4 ROMCS# BOOT16 G28 G29 G30 GPWIO1 GPWIO2 VIO
432-EBGA Ball Assignment - Sorted by Ball Number (Continued)
I / O Buffer1 Power Rail Configuration (PU / PD) Type PWR O I / O (PU22.5) I (PU22.5) I (PU22.5) I O O O O I / O (PU22.5) O (PU22.5) O (PU22.5) I I I I / O I / O O GND PWR GND GND I / O I / O I / O GND GND PWR PWR PWR I / O GND I / O PWR PWR O -O2 / 5 INTS, O8 / 8 INTS INTS1 INTS O1 / 4 O1 / 4 O8 / 8 O8 / 8 INTS, O3 / 5 O3 / 5 O1 / 4 INTS INTS INTS INT, TS2 / 5 INT, TS2 / 5 WIRE ----INT, TS2 / 5 INT, TS2 / 5 INT, TS2 / 5 -----INT, TS2 / 5 -INT, TS2 / 5 --WIRE VSB VIO VIO VIO VIO AVCCCRT ----VIO VIO VIO -----VIO -VIO --AVCCCRT
-VSB VIO
INSTRP I (PD100) I / O O I PWR GND O O PWR O O I / O (PU22.5) O INPCI, OPCI OPCI INTS --OD14 O3 / 5 -O3 / 5 O3 / 5 INTS, O3 / 5 O3 / 5
VSB VIO VIO VIO
----J4
GPIO17 IOCS0# TFTDCK
IRRX1 SIN3
J29 J30
POR# MD0 MD1 RED VSSCRT VCCCRT VSS VSS
J314 K1
INSTRP I (PD100) I / O (PU100) I / O (PU100) PWR O O I / O (PU22.5) INTs, TS2 / 14 INTS, TS2 / 14 -OD14 O3 / 5 INTS, O3 / 5
K3 K4 K28 K29
G314, 5 PWRCNT2 H1 TRDE# GPIO0 H2 GPIO1 IOCS1# TFTD12 H3 GPIO20 DOCCS# TFTD0 H4 GPIO19 INTC# IOCHRDY
MD2 MD3 MD4 AVSSCRT VSS AVCCCRT VCORE VCORE MD5 VSS
K304 K314 L1 L2 L3 L4 L28 L294 L30 L31 M1 M2 M3
INT, O3 / I / O (PU22.5) 5 O (PU22.5) O (PU22.5) O3 / 5 O1 / 4
INT, O3 / I / O (PU22.5) 5 O (PU22.5) O (PU22.5) I / O (PU22.5) I (PU22.5) I (PU22.5) O3 / 5 O1 / 4 INTS, O3 / 5 INTS INTS1
MD6 AVCCCRT VIO GREEN
AMD Geode SC2200 Processor Data Book
Signal Definitions
Revision 5.1
Table 3-2.
Ball No. M4 M28 M29 M30 M31 N1 N2 N3 N4 N28 N29 N30 N31 P1 P2 P3 P4 P28 P29 P30 P31 R1 R2 R3 R4 R28 R29 R30 R31 T1
432-EBGA Ball Assignment - Sorted by Ball Number (Continued)
Signal Name VSS VSS MD7 VIO DQM0 AVCCCRT BLUE AVSSCRT VCORE VCORE WEA# CASA# RASA# VREF SETRES AVSSCRT VSS VSS CS0# BA0 BA1 VPLL2 VSS AVSSPLL2 VCORE VCORE MA10 VSS MA0 BUSY / WAIT#
I / O Buffer1 Power Rail Configuration (PU / PD) Type GND GND I / O PWR O PWR O GND PWR PWR O O O I / O I GND GND GND O O O PWR GND GND PWR PWR O GND O I --INT, TS2 / 5 -O2 / 5 -WIRE ---O2 / 5 O2 / 5 O2 / 5 WIRE WIRE ---O2 / 5 O2 / 5 O2 / 5 -----O2 / 5 -O2 / 5 INT --VIO -VIO -AVCCCRT ---VIO VIO VIO AVCCCRT AVCCCRT ---VIO VIO VIO -----VIO -VIO VIO ---------------
TFTD14
T44, 5
TFTD15
T28 --T31 -----------U2 U3
DQM4 MA2 VCORE MA1 PD7
T29 T30
U14, 5
TFTD13
VSS ACK#
FPCICLK
TFTD3
VCORE VCORE MD33 VSS MD32 PD4
--INT, TS2 / 5 -INT, TS2 / 5 INT, O14 / 14 O1 / 4
TFTD10
AMD Geode SC2200 Processor Data Book
Revision 5.1
Signal Definitions
Table 3-2.
Ball No. V24, 5 Signal Name PD5
432-EBGA Ball Assignment - Sorted by Ball Number (Continued)
TFTD11
TFTD7
V34, 5
Y2 Y34, 5
TFTD1
VIO INIT#
-O14 / 14
TFTD5
V4 V28 V294 V30
VSS VSS MD36 MD35 MD34 SLIN# / ASTRB#
--INT, TS2 / 5 INT, TS2 / 5 INT, TS2 / 5 O14 / 14
VSS VSS MD46 VIO MD47
--INT, TS2 / 5
Y28 Y294
V314 W14, 5
TFTD16
AA14, 5 PD0
TFTD6
W24, 5
TFTD9
AA2 AA34, 5
VSS ERR#
TFTD4
W34, 5
TFTD8
VCORE VCORE MD44 VSS MD45
--INT, TS2 / 5 -INT, TS2 / 5
W4 W28 W29
VCORE VCORE MD39 MD38
--INT, TS2 / 5 INT, TS2 / 5
AMD Geode SC2200 Processor Data Book
Signal Definitions
Revision 5.1
Table 3-2.
Ball No. Signal Name
432-EBGA Ball Assignment - Sorted by Ball Number (Continued)
Ball No. AE29 AE30 AE31 AF1 AF2 AF34 AF4 AF28
I / O Buffer1 Power Rail Configuration (PU / PD) Type O PWR O I (PU22.5) GND I / O PWR I / O I / O GND O GND I / O I / O I / O (PU22.5) I (PU22.5) O (PU22.5) O (PU22.5) O I / O I / O I / O I / O I / O I / O (PU22.5) O (PU22.5) O (PU22.5) O (PU22.5) O2 / 5 -O2 / 5 INPCI -INUSB, OUSB -INT, TS2 / 5 INT, TS2 / 5 -O2 / 5 -INUSB, OUSB INUSB, OUSB INTS, O1 / 4 INTS O1 / 4 O2 / 5 O2 / 5 INT, TS2 / 5 INT, TS2 / 5 INT, TS2 / 5 INUSB, OUSB INUSB, OUSB INTS, O1 / 4 O1 / 4 O1 / 4 O2 / 5 VIO VIO VIO VIO AVCCUSB AVCCUSB VIO VIO -VIO VIO -AVCCUSB
AB14, 5 STB# / WRITE#
TFTD17
AB24, 5 AFD# / DSTRB#
-VIO VIO -VIO -AVCCUSB AVCCUSB VIO
TFTD2
AF294 AF30 AF31 AG1 AG24 AG34 AG4
AB3 AB4 AB28 AB294 AB304 AB314 AC1 AC2 AC3 AC4 AC28 AC29 AC30 AC31 AD1 AD2 AD3 AD4 AD28 AD29 AD30 AD31 AE1 AE2 AE3 AE44 AE28
---INT, TS2 / 5 INT, TS2 / 5 INT, TS2 / 5 ----O2 / 5 O2 / 5 O2 / 5 INT, TS2 / 5 ----O2 / 5 O2 / 5 O2 / 5 O2 / 5 --INPCI INUSB, OUSB O2 / 5
--VIO VIO VIO
--VIO VIO VIO VIO
AG28 AG29
AG304 AG314
-----AH3 --------AH24 AH14
VIO VIO VIO VIO
-VIO AVCCUSB VIO
AMD Geode SC2200 Processor Data Book
Revision 5.1
Signal Definitions
Table 3-2.
432-EBGA Ball Assignment - Sorted by Ball Number (Continued)
LPCPD# AJ1