Programmable Interrupt Controller July 1997, ver. Features

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Programmable Interrupt Controller July 1997, ver. Features

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a8259
Programmable Interrupt Controller
July 1997, ver.
Features
Optimized FLEX® MAX® architectures Offers eight levels individually maskable interrupts Expandable interrupts Offers flexible priority resolution scheme Provides programmable interrupt modes vectors Uses approximately logic elements (LEs) FLEX devices Functionally based Intel 8259 device, except noted "Variations Clarifications" section page
General Description
Altera® a8259 MegaCorefunction programmable interrupt controller. a8259 initialized microprocessor through eight data lines (din[7.0] dout[7.0]), ncs, nrd, nwr, int, ninta control signals. Figure shows symbol a8259.
Figure a8259 Symbol
A8259
nMRST nINTA CASIN[2.0] IR[7.0] DIN[7.0] CASOUT[2.0] CAS_EN DOUT[7.0]
Altera Corporation
A-DS-A8259-01
a8259 Programmable Interrupt Controller
Table describes input output ports a8259.
Table a8259 Ports
Name
nmrst ninta
Type
Input Input Input Input Input Input Input Input
Polarity
High
Description
Master reset. When nmrst asserted, internal registers assume their default state. a8259 idle, awaiting initialization. Clock. registers clocked positive edge clock. Chip select. When low, this signal enables signals register access from a8259. Write control. When this signal (and signal also low), enables write transactions a8259. Read control. When this signal (and signal also low), enables read transactions from a8259. Address. This signal serves register selector when writing reading from internal a8259 registers. Interrupt acknowledge. This signal serves primary handshake between a8259 microprocessor during interrupt service cycle. Slave processor. This signal indicates that a8259 should configured slave. However, this signal ignored when a8259 configured single device. This signal should also ignored buffered mode. Cascade data bus. These signals cascade mode control slave a8259. a8259 configured master, should driven low.
casin[2.0]
Input
High
ir[7.0] din[7.0]
Inputs Input Output
High Interrupt request. These eight maskable, prioritized interrupt service request signals. High High Data bus. This inputs data when writing internal a8259 registers. Interrupt. This signal indicates that a8259 made unmasked service request. Cascade data bus. These signals cascade mode control, should connected casin[2.0] slave a8259. When a8259 configured master, casout[2.0]bus ignored. Cascade directional enable. This signal intended tri-state enable signal external bidirectional buffers cascade control bus. Data bus. output data when reading from internal a8259 registers. Data enable. This signal indicates that read cycle being performed internal a8259 register, intended tri-state enable external bidirectional buffers.
casout[2.0] Output
cas_en dout[7.0]
Output Output Output
High
Note:
interrupt request signals active high positive-edge-triggered Initialization Command Word (ICW) (see "ICW page more information).
Altera Corporation
a8259 Programmable Interrupt Controller
Functional Description
Figure shows a8259 block diagram.
Figure a8259 Block Diagram
ir[7.0]
Interrupt Request Register
Priority Resolution
In-Service Register
ninta casin[2.0] nmrst Interrupt Control Logic
cas_en cas_out[2.0]
Interrupt Vector
din[7.0]
Read/Write Control Logic Initialization/ Command Registers
dout[7.0]
ninta signals provide handshaking mechanism a8259 signal microprocessor. a8259 requests service signal receives acknowledgment acceptance from microprocessor ninta signal. signal applied directly microprocessor's interrupt input. Whenever a8259 receives valid interrupt request (ir1 through ir7), signal goes high. ninta input connected microprocessor's interrupt acknowledgment signal. microprocessor pulses ninta signal twice during interrupt acknowledgment cycle, which tells a8259 that interrupt request been acknowledged. Then, a8259 sends highest priority active interrupt type number onto din[7.0] microprocessor acknowledge. inputs used external devices request service, they configured level-sensitive edge-sensitive operation.
Altera Corporation
a8259 Programmable Interrupt Controller
casin[2.0]and casout[2.0] buses, cas_en pins used implement cascade interface. These pins used when more than a8259 functions interconnected master/slave configuration, expanding number interrupts from
Programming Initialization
a8259 operation depends initial programming. types command words used programming a8259: initialization command words (ICWs) operation command words (OCWs). ICWs used load a8259 internal control registers, while OCWs permit microprocessor initiate variations basic operating modes defined registers. Table summarizes access registers programming initialization (for more information registers, "Register Descriptions" page 62).
Table Register Access Programming Initialization
Register
Note
Access Method
Mnemonics
Description
Don't Care write with high interpreted beginning initialization sequence. This register always follows this register depends value SINGLE (see Figure page 61). this register depends value (see Figure page 61).
Don't Care Don't Care
Don't Care Don't Care
Sequential access which starts with timed pulsing signal.
Don't Care
Don't Care
Note:
Don't Care
Don't Care
These registers accessed Random access randomly (see "Operation Command Word Registers" page more details).
"Don't Care" indicates that address significance this register access method. However, will usually have data significance.
begin initialization sequence, must low, din[7.0] must high during valid write cycle. Figure shows a8259 initialization sequence flow diagram.
Altera Corporation
a8259 Programmable Interrupt Controller
Figure a8259 Initialization Sequence Flow Diagram
SINGLE low? Note
high? Note
Ready accept interrupts
Note:
more information SINGLE IC4, Table page
Figures show typical write read cycles, respectively. ncs, nwr, signals enable data written read from a8259. This data clocked rising edge clk. signals must held entire clock cycle order read write valid data.
Figure Typical Write Cycle
indicates "don't care." indicates "data valid."
din[7.0]
Altera Corporation
a8259 Programmable Interrupt Controller
Figure Typical Read Cycle
indicates "don't care." indicates "data valid."
din[7.0]
Register Descriptions
a8259 contains three type registers:
Initialization command word (ICW) registers Operation command word (OCW) registers Interrupt registers
Initialization Command Word Registers
There four command registers:
Input data sent din[7.0] must din[7.0] must held high). deselected with rising edge signal. Table describes register format.
Table Register Format (Part
Mnemonic
Description
When low, this causes reset (i.e., nonbuffered mode, automatic EOI, 3-byte interrupt sequence), initialization cycle skip When high, accessed normally. Single mode. When high, this indicates that a8259 cascaded with other a8259 functions. When low, this causes a8259 operate cascade mode. Address interval. When using 3-byte interrupt sequence, this selects address interval. When low, address interval eight; otherwise, four.
SINGLE
Altera Corporation
a8259 Programmable Interrupt Controller
Table Register Format (Part
Mnemonic
LTIM
Description
Level-sensitive edge-triggered input mode. When high, ir[7.0] pins level-sensitive inputs; otherwise, they positive-edge-triggered. This used conjunction with signal select other command registers (see "Interrupt Registers" page 69). These bits interrupt vector address (bits through 3-byte interrupt sequence (see "Interrupt Sequencing" page 70).
selected after signal been high. Input data sent din[7.0] bus, data clocked rising edge clk. deselected with next falling edge signal. Table describes register format.
Table Register Format
Mnemonic
Description
These bits interrupt vector address. bits through interrupt vector address singlebyte interrupt sequence mode. bits through interrupt vector address same mode. "Operating Modes Sequence Events" page more information.
SINGLE (bit low, next register selected (see "ICW page 64). SINGLE high, skipped. next register considered (see Figure page 61). high, then next register selected; low, skipped. When write transaction completed 4-or skipped-the initialization sequence finished, a8259 ready accept interrupts.
Altera Corporation
a8259 Programmable Interrupt Controller
SINGLE low, must initialized. Input data sent din[7.0] bus, data clocked rising edge clk. deselected with next falling edge signal. meaning contents depends whether a8259 configured master slave. Table describes register format a8259 configured master.
Table Register Format (a8259 Master Configuration)
Mnemonic
Description
These bits slave inputs. When high, each indicates that corresponding interrupt request line cascaded slave input. instance, high, treated slave input receives data from signal another a8259.
Table describes register format when a8259 configured slave.
Table Register Format (a8259 Slave Configuration)
Mnemonic
Description
Slave identification. These bits slave a8259. These bits used when a8259 configured slave, they should low.
this point initialization process, next register selected depends whether high. high, selected (see "ICW page 65). low, skipped a8259 ready accept interrupts.
Altera Corporation
a8259 Programmable Interrupt Controller
initialized when high. Input data sent din[7.0] bus, data clocked rising edge clk. deselected with next falling edge signal. When write transaction finished-or skipped- initialization sequence complete, a8259 ready accept interrupts. Table describes register formats.
Table Register Format
Mnemonic
Description
Microprocessor mode. When this low, a8259 operates 3-byte interrupt sequence mode. high, operates single-byte interrupt sequence mode. Automatic interrupt. When this high, AEOI enabled; otherwise, AEOI disabled. Master/slave. When this high buffered mode,
AEOI
a8259 configured slave, when low, a8259 configured master. When device
buffered mode, this "don't care" condition. Buffered mode. When this high, a8259 buffered mode. "Operating Modes Sequence Events" page more information. Special fully nested mode. When this high, a8259 special fully nested mode. These bits unused should low.
SFNM
Operation Command Word Registers
Once appropriate registers have been issued a8259, they will ready operation. There three registers: These command registers control operation a8259, permit interrupt interface operation further modified-after a8259 been initialized. Unlike initialization sequence, which requires outputs special sequence, OCWs issued under program control whenever needed order.
Altera Corporation
a8259 Programmable Interrupt Controller
selected setting high. Input data sent din[7.0] bus, data clocked rising edge clk. Table describes register format.
Table Register Format
Mnemonic
Description
When more than these bits high, corresponding interrupt request inputs masked; otherwise, they masked.
selected setting resetting bits din[7.0] low. Input data sent din[7.0] bus, data clocked rising edge clk. Table describes register format.
Table Register Format
Mnemonic
Description
Interrupt level. These bits determine interrupt level that acted upon when (SL) asserted (see Table 10). These bits used address decode must always low. These bits control rotate interrupt (EOI) commands (see Table page 67).
Altera Corporation
a8259 Programmable Interrupt Controller
Table describes interrupt levels acted upon when (bit asserted.
Table Interrupt Levels (Bit
Interrupt Level
Mnemonic
Table describes rotate commands controlled bits through command register.
Table Rotate Commands Controlled Bits Through
Command
Non-specific command Specific command Rotate non-specific command Rotate automatic mode (set) Rotate automatic mode (clear) Rotate specific command (L0, used) Specific priority command (L0, used) operation
selected setting pin, resetting low, high. Input data sent din[7.0] bus, data clocked rising edge clk.
Altera Corporation
a8259 Programmable Interrupt Controller
Table describes register format.
Table Register Format
Decode
Description
Read register command. These bits control which status register will accessed next read cycle (see Table 13). When this high high, a8259 enters poll mode; next cycle ends poll mode (see "Poll Command" page 75). These bits used address decode. must must high. Special mask mode. These bits used enable, set, clear special mask mode function (see Table 14). This unused should tied GND.
Note:
ESMM
Enable special mask mode.
Table describes read register commands bits command register.
Table Read Register Commands Bits
action action
Command
Read interrupt request register (IRR) next read cycle Read in-service register (ISR) next read cycle
Table describes special mask mode commands bits command register.
Table Read Register Commands Bits
ESMM
Command
action action Reset special mask special mask
Altera Corporation
a8259 Programmable Interrupt Controller
Interrupt Registers
a8259 contains interrupt registers:
Interrupt request register (IRR) In-service register (ISR)
Interrupt Request Register
stores interrupts that requesting service. edge-triggered mode (when low), each synchronized signal. Positive-edge detection performed, result clocked into IRR. level-triggered mode (when high), each signal clocked directly into IRR. falling edge first ninta signal from microprocessor freezes interrupts evaluated. level signal from microprocessor must maintained until after falling edge ninta signal. Interrupt handshaking protocol must completed before next interrupt received. Table shows format.
Table Format
Decode
In-Service Register
stores interrupt level currently being serviced. Data enabled first ninta signal interrupt acknowledge sequence. AEIO mode, data reset upon final rising edge ninta signal interrupt sequence. Otherwise, microprocessor must issue command writing appropriate value command register. Table shows format.
Altera Corporation
a8259 Programmable Interrupt Controller
Table Format
Decode
ISR0 ISR1 ISR2 ISR3 ISR4 ISR5 ISR6 ISR7
Interrupt Sequencing
a8259 supports interrupt sequencing modes:
3-byte interrupt sequence mode Single-byte interrupt sequence mode
3-Byte Interrupt Sequence Mode
3-byte interrupt sequence mode provides 24-bit interrupt vector. interrupt sequence this mode follows: more interrupt request signals (ir[7.0]) high, which sets corresponding IRR. a8259 checks priority masks interrupt, appropriate, sets signal. microprocessor responds asserting ninta a8259. a8259 latches interrupt request signals falling edge ninta signal (when level-triggered). a8259 sets corresponding following rising edge ninta. Simultaneously, reset. a8259 places fixed vector opcode binary 11001101 dout[7.0] while ninta signal low. vector opcode indicates that following bytes will contain interrupt vector. microprocessor responds vector opcode sending more ninta pulses. falling edge first ninta pulse causes lower eight interrupt vector address bits placed dout[7.0] bus. contents lower eight bits depend value address interval (bit Tables
Altera Corporation
a8259 Programmable Interrupt Controller
Table Contents First Interrupt Vector Bytes
Notes (1),
dout2
dout7
dout6
dout5
dout4
dout3
dout1
dout0
Table Contents First Interrupt Vector Bytes
Notes (2),
dout2
dout7
dout6
dout5
dout4
dout3
dout1
dout0
Notes tables:
Interval (bit high). through derived from contents bits Interval (bit low).
upper eight interrupt vector address bytes released falling edge second ninta pulse. contents upper eight interrupt vector address bytes always derived from contents Table
Table Contents Second Interrupt Vector Bytes
dout7
dout6
dout5
dout4
dout3
dout2
dout1
dout0
AEOI mode, reset rising edge last ninta pulse. When AEOI mode, appropriate command must issued interrupt sequence.
Altera Corporation
a8259 Programmable Interrupt Controller
Figure shows timing waveforms 3-byte interrupt sequence mode.
Figure 3-Byte Interrupt Sequence Mode Timing Waveforms
indicates "Don't Care."
Level-triggered interrupt request Edge-triggered interrupt request
Level-triggered interrupt request clocked falling edge ninta.
ninta dout[7.0]
Call Code
Vector Data
Vector Data
Single-Byte Interrupt Sequence Mode
single-byte interrupt sequence mode provides 8-bit interrupt vector. interrupt sequence this mode follows: more ir[7.0] signals high, which sets corresponding IRR. a8259 checks priority masks interrupt, appropriate, sets signal. microprocessor responds asserting ninta a8259. a8259 latches signal falling edge ninta signal (when level-triggered). a8259 sets corresponding following rising edge ninta signal. Simultaneously, interrupt request reset, data driven onto dout[7.0] this cycle. microprocessor issues second ninta pulse. 8-bit interrupt vector driven onto dout[7.0] bus. Table
Altera Corporation
a8259 Programmable Interrupt Controller
Table Contents Interrupt Vector Bytes
Note:
Note
dout2
dout7
dout6
dout5
dout4
dout3
dout1
dout0
through derive from contents (bits through
AEOI mode, reset rising edge last ninta pulse. When AEOI mode, appropriate command issued interrupt sequence.
Figure shows timing waveforms single-byte interrupt sequence mode.
Figure Single-Byte Interrupt Sequence Mode Timing Waveforms
indicates "Don't Care." indicates "Vector Data."
Level-triggered interrupt request Edge-triggered interrupt request
Level-triggered interrupt request clocked falling edge ninta.
ninta dout[7.0]
Altera Corporation
a8259 Programmable Interrupt Controller
Operational Commands
a8259 supports several operational commands:
Priority rotation Special mask mode (SMM) Trigger modes Poll command
Priority Rotation
priority rotation command adjust interrupt request priority. a8259 supports types rotation commands: automatic specific rotation. automatic rotation command rotates interrupt that just been serviced lowest priority. example, interrupt just been serviced, assigned lowest priority, interrupt then given highest priority. system with equal priority interrupts, this process ensures that interrupt waits more than seven other devices serviced. Automatic priority configured operate non-specific EOI, automatic using command register. specific rotation command similar automatic rotation command, except interrupt assigned lowest priority specified using bits through command register. Specific rotation accomplished issuing priority command rotate-on-specific command.
Interrupt
command used clear last interrupt request serviced bit. There methods used issue command: automatic non-specific. automatic command used (bit high), non-specific command issued rising edge last ninta pulse interrupt sequence. non-specific clears currently highest priority. long specific rotation used, non-specific will always clear last interrupt request serviced bit. When interrupt priority scheme disturbed (usually specific rotation), specific command issued clear interrupt request specified bits through command register.
Altera Corporation
a8259 Programmable Interrupt Controller
Special Mask Mode
SMM, masking interrupt does inhibit reception lower priority interrupts. Only interrupt being serviced masked. With SMM, interrupt selectively enabled using mask register.
Trigger Modes
Interrupt request lines configured edge- level-triggered mode. edge-triggered mode, interrupt request clocked rising edge clock. level-triggered mode, interrupt generated merely placing high pin. This level must maintained until after falling edge first ninta pulse interrupt sequence. trigger mode programmed command register.
Poll Command
poll command provides expand system allowing microprocessor service more than interrupts. poll mode, signal should ignored. Each a8259 "polled" individually determine which interrupts requesting service. After setting poll (using microprocessor simply reads from each a8259 (each interrupt read transaction must preceded write transaction poll order reset ISR). interrupt pending, corresponding falling edge read cycle, interrupt byte (bit high placed dout[7.0] bus. Table shows interrupt word format poll command.
Table Interrupt Word Format
Decode
Don't Care Don't Care Don't Care Don't Care
Description
Interrupt These bits identify pending interrupt. Interrupt pending. When set, this indicates interrupt pending. this cleared, interrupt will ignored.
Altera Corporation
a8259 Programmable Interrupt Controller
Figure shows timing waveforms poll mode.
Figure Poll Mode Timing Waveforms
indicates "Don't Care." indicates "Vector Data."
Level-triggered interrupt request Edge-triggered interrupt request
Level-triggered interrupt request clocked falling edge nrd.
dout
dout[7.0]
Operating Modes Sequence Events
a8259 operate four different modes:
Fully nested mode Cascade mode Special fully nested mode Buffered mode
Fully Nested Mode
fully nested mode default mode, after master clear. a8259 will enter this mode when initialization completed, unless another mode specifically programmed. When a8259 fully nested mode, following sequence events occurs: interrupt requests prioritized from (highest priority) (lowest priority). When interrupt request acknowledged, highest priority, unmasked request determined, corresponding set, reset. While being set, further interrupts from lower priority sources ignored. Interrupts from higher priority sources clocked, causing signal remain active until interrupt serviced.
Altera Corporation
a8259 Programmable Interrupt Controller
During appropriate handshaking sequence using inta ninta signals, interrupt vector information placed dout[7.0] bus. AEOI mode, reset rising edge last ninta pulse. When AEOI mode, appropriate command issued interrupt sequence.
Cascade Mode
cascade mode provides easy expansion a8259. this mode, single a8259 configured master, while other a8259 functions (from a8259 functions) configured slaves. signal each slave connected input master. master's signal serves interrupt microprocessor. master's casout[2.0] connected slave's casin[2.0] bus. Each a8259 unique signal other inputs a8259 connected parallel. When slave receives interrupt, master asserts signal. master enables slave placing slave's address casout[2.0] rising edge first ninta pulse. slave then responsible completing ninta handshaking required interrupt sequence. slave will place interrupt vector information dout[7.0] required interrupt sequence.
3-Byte Interrupt Sequence Cascade Mode
3-byte interrupt sequence cascade mode, handshaking between ninta signals follows: master clocks that corresponds slave input falling edge first ninta pulse. master also simultaneously resets places fixed vector opcode binary 11001101 dout[7.0] bus. vector opcode indicates that bytes that follow will contain interrupt vector. master enables slave placing slave's address casout[7.0] rising edge first ninta pulse.
Altera Corporation
a8259 Programmable Interrupt Controller
microprocessor responds vector opcode sending more ninta pulses. slave sets appropriate falling edge second ninta pulse. Simultaneously, slave's reset. falling edge second ninta pulse also causes slave place lower eight interrupt vector address bits slave's dout[7.0] bus. upper eight interrupt vector address bits released falling edge third ninta pulse. commands must issued interrupt sequence: master other slave.
Single-Byte Interrupt Sequence Cascade Mode
single-byte interrupt sequence cascade mode, handshaking between ninta signals follows: master sets that corresponds slave input falling edge first ninta pulse. master also simultaneously resets data driven onto dout[7.0] this cycle. master enables slave placing slave's address casout[7.0] rising edge first ninta pulse. microprocessor issues second ninta pulse. slave sets corresponding falling edge second ninta pulse. Simultaneously, slave's reset. slave drives eight interrupt vector address bits onto dout[7.0] bus. commands must issued interrupt sequence: master slave.
slave's address will remain casout[2.0] until rising edge last ninta pulse.
Special Fully Nested Mode
This mode used conjunction with cascade mode preserve priority structure within each slave. operate this mode, only master should high. slaves configured normal fully nested mode. When slave service, will locked master's priority logic; master recognize interrupts from higher priority sources within that slave.
Altera Corporation
a8259 Programmable Interrupt Controller
complete interrupt service ensure that interrupts from slave have been serviced, microprocessor sends non-specific command slave reads slave's interrupt request register active signals. interrupt request register low, non-specific command issued master. Otherwise, master services pending interrupt request.
Buffered Mode
buffered mode originally intended support board designs where tri-state buffers were needed drive data bus. a8259 separate signals, signal always available. Instead using signal, buffered mode determine master/slave configuration using bits command register.
Variations Clarifications
following characteristics distinguish Altera a8259 function from Intel 8259A device:
master clear provided with a8259. clock signal been added, synchronous design rules have been incorporated improve operation reliability. input signals except nmrst should synchronous clock signal. inputs must asserted clock cycle ensure reliable operation. Bidirectional pins split into separate inputs, outputs, corresponding tri-state control lines. This features makes a8259 compatible with multiplexer scheme used internally design. dout[7.0], casout[2.0], int, cas_en, outputs driven complex logic structures prone glitches. appropriate, these signals should registered target application. Because a8259 used various Altera architectures, timing information included this data sheet. Automatic slave mode implemented within a8259.
Altera Corporation
Copyright 1995, 1996, 1997, 1998, 1999 Altera Corporation, Innovation Drive, Jose, 95134, USA, rights reserved. accessing this information, agree bound terms Altera's Legal Notice.

Programmable Interrupt Controller July 1997, ver. Features

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