Universal Asynchronous Receiver/Transmitter September 1996, ver.

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Universal Asynchronous Receiver/Transmitter September 1996, ver.

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a6402
Universal Asynchronous Receiver/Transmitter
September 1996, ver.
Features
a6402 MegaCore function implementing universal asynchronous receiver/transmitter (UART) Optimized FLEX® MAX® architectures Uses approximately FLEX logic elements (LEs) Programmable word length, stop bits, parity Full duplex operation Includes status flags parity, framing, overrun errors Functionally based Harris HD-6402 device, except noted "Variations Clarifications" section page
General Description
a6402 MegaCore function implements universal asynchronous receiver/transmitter (UART), which provides interface between microprocessor serial communications channel. Figure
Figure a6402 Symbol
A6402
cls1 cls2 ndrr ntbrl tbr[7.0]
rbr[7.0] tbre
Altera Corporation
A-DS-A6402-01
a6402 Universal Asynchronous Receiver/Transmitter
Ports
Table shows input output ports a6402.
Table a6402 Ports
Name
cls1 cls2
Type
Input
Polarity
Description
Character length select bits. These bits determine length data word. 5-bit word format 6-bit word format 7-bit word format 8-bit word format Control register load. Controls data word loaded into control register. Data received reset. Clears output. Even parity enable. When high, even parity; when low, parity. Master reset. Clears outputs, asserts tbre outputs. Parity inhibit. When asserted, parity neither generated checked. Receiver register clock. Operates times receive data rate. Receiver register input. Serial input data. Stop select. When high, generates stop bits (1.5 stop bits 5-bit format); when low, generates stop bit. Transmitter buffer register load. Enables load transmitter buffer register. Transmitter buffer register input bus. Transmitter register clock. Operates times transmit data rate. Data received. Indicates that data word been transferred receiver buffer register. Framing error. Asserted when expected stop bit(s) detected. Overrun error. Asserted when data receiver buffer register overwritten while output still asserted. Parity error. when calculated parity does match received parity. When asserted, low. Receiver buffer register bus. Transmitter buffer register empty. Indicates that transmitter buffer register empty. Transmitter register empty. Indicates that data word completely transmitted transmitter register. Transmitter register output. Serial output data.
ndrr ntbrl tbr[7.0] rbr[7.0] tbre
Input Input Input Input Input Input Input Input Input Input Input Output Output Output Output Output Output Output Output
High High/low High High High/low High High High High/low High High
Altera Corporation
a6402 Universal Asynchronous Receiver/Transmitter
Configurations
a6402 receives transmits data variety configurations, including 8-bit data words; odd, even, parity; 1.5, stop bits. Table shows available configuration options.
Table a6402 Available Configurations
Character Format Data Bits Parity
Even Even None None Even Even None None Even Even None None Even Even None None Note:
indicates "don't care."
Control Word Stop Bits
Start
cls2
cls1
Note
Altera Corporation
a6402 Universal Asynchronous Receiver/Transmitter
Functional Description
Figure a6402 Block Diagram
cls2 cls1 tbre
Figure shows block diagram a6402.
Control Register
Transmitter
Transmitter Control
ntbrl
Start Transmitter Buffer Register Transmitter Register Parity Generator Transmitter Multiplexer
Stop
ndrr Receiver Control
Receiver
Receiver Buffer Register
Receiver Register
Parity Check Stop Check
Altera Corporation
a6402 Universal Asynchronous Receiver/Transmitter
Master Reset
When input asserted, outputs asynchronously cleared tbre asserted. assertion also sets state machines default idle state. This condition does affect receiver buffer register. input must pulsed high least once after power-up. When deasserted, normal operation resumes next rising edge rrc. Once outputs set, only exit condition available through asserting
Control Register
control register contains configuration data word, including number bits, calculated parity, number stop bits. input, active high register enable, controls data word loaded into control register. When asserted, cls2, cls1, epe, inputs loaded next rising edge input.
Transmitter
transmitter consists following elements:
Transmitter control-The transmitter control contains three interconnected state machines. first state machine regulates baud rate performing divide-by-16 operation input. second state machine detects low-to-high transition ntbrl, starts serial transmission through tro, transfers data from transmitter buffer register transmitter register, generates status signals tbre tre. third state machine controls multiplexing data bits output. Transmitter buffer register-The transmitter buffer register loaded ntbrl, active-low register enable, that causes tbr[7.0] loaded from microprocessor next clock edge. Transmitter register-The transmitter register loads data from transmitter buffer register holds that data until transmission complete.
Altera Corporation
a6402 Universal Asynchronous Receiver/Transmitter Data Sheet
Parity generator-The parity generator calculates appropriate parity value depending input (even parity) inputs (data word length). Transmitter multiplexer-The transmitter multiplexer selects single-bit data value drives output. Inputs transmitter multiplexer include start bit, eight bits from transmitter register, parity bit, stop idle bit.
Receiver
receiver consists following elements:
Receiver control-The receiver control contains three interconnected state machines. first state machine performs divide-by-16 operation clock determine when sample serial input. second state machine detects high-to-low transition rri, determines valid start been received, transfers data from receiver register receiver buffer register, generates status signals third state machine loads individual bits receiver register outputs. Receiver register-The receiver register loads number data bits determined inputs. data word less than eight bits, data right-justified with MSBs filled with logic lows. When stop detected, receiver register transfers contents receiver buffer register. Parity check-The parity check calculates parity data word parity bit. error occurs, output asserted. Once asserted, output only cleared asserting input. Stop check-The stop check samples middle first expected stop bit. error occurs, output asserted. Once asserted, output only cleared asserting input.
Altera Corporation
a6402 Universal Asynchronous Receiver/Transmitter
Timing Waveforms
Figure shows timing waveforms a6402.
Figure a6402 Functional Timing Waveforms
Data Input Cycle
tbr[7.0] ntbrl Valid Data
Control Register Input Cycle
cls[2.1], epe, Valid Data
Serial Data Format Bits, Parity Bit, Stop Bit)
Start Data
Data Parity Stop
Variations Clarifications
following characteristics distinguish Altera® a6402 from Harris HD-6402:
a6402 does contain inputs, outputs tri-stated. a6402, control transmitter buffer registers implemented registers clock source; these registers implemented latches HD-6402 device. a6402, after deasserted, normal operation resume next rising clock edge. HD-6402 device, normal operation does resume clock cycles. synchronization process a6402, tbre deasserted clock cycles after low-to-high transition ntbrl. HD-6402 device, tbre deasserted immediately after low-to-high transition ntbrl. a6402, output registered remove glitches. This register uses clock source. Once outputs asserted, HD-6402 device exit condition other than through asserting
Altera Corporation
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Universal Asynchronous Receiver/Transmitter September 1996, ver.

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