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approved method attenuation. Provides 20dB suppression. Generates spre
Top Searches for this datasheetPanel Reduction approved method attenuation. Provides 20dB suppression. Generates spread spectrum clock input frequency. Input frequency range: 30MHz 110MHz. Optimized VGA, SVGA, higher resolution Panels. Internal loop filter minimizes external components board space. selectable high spread ranges selectable modulation rates. SSON# control spread spectrum enable disable options. cycle-to-cycle jitter. Wide operating range. 16mA output drives. CMOS compatible outputs. power CMOS design. Supports most mobile graphic accelerator specifications. Products available automotive temperature range. (Refer Spread Spectrum Range Selection Tables) Available 8-pin SOIC TSSOP. P2040A implemented proprietary digital method. P2040A modulates output single order "spread" bandwidth synthesized clock, more importantly, decreases peak amplitudes harmonics. This results significantly lower system compared typical narrow band signal produced oscillators most frequency generators. Lowering increasing signal's bandwidth called `spread spectrum clock generation'. Applications P2040A targeted towards digital flat panel applications notebook PCs, palm-size PCs, office automation equipments monitors. Product Description P2040A versatile spread spectrum frequency modulator designed specifically digital flat panel applications. P2040A reduces electromagnetic interference (EMI) clock source, allowing system wide reduction down stream clock data dependent signals. P2040A allows significant system cost savings reducing number circuit board layers ferrite beads, regulations. P2040A uses most efficient optimized modulation profile approved shielding other passive components that traditionally required pass Alliance Semiconductor 2575, Augustine Drive Santa Clara, Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com Notice: information this document subject change without notice. Block Diagram P2040A SSON# DIV2 Modulation CLKIN Frequency Divider Feedback Divider Phase Detector Loop Filter Output Divider ModOUT Configuration CLKIN ModOUT SSON# P2040A Description Pin# Name CLKIN SSON# ModOUT Type Description External reference frequency input. Connect externally generated reference signal. Digital logic input used select modulation rate. This internal pull-up resistor. Digital logic input used select Spreading Range. This internal pull-up resistor. Ground entire chip. Connect system ground. Digital logic input used enable Spread Spectrum function (Active LOW). Spread Spectrum function enabled when LOW, disabled when HIGH. This internal pull-low resistor. Spread spectrum clock output. Digital logic input used select Spreading Range. This internal pull-up resistor. Power supply entire chip (3.3V) Panel Reduction Notice: information this document subject change without notice. Modulation Selection (Commercial) Spreading Range 1.125 1.75 0.75 1.25 1.25 2.00 Reserved Reserved P2040A Modulation Rate (KHz) (FIN /40) 34.72 (FIN /40) 34.72 (FIN /40) 34.72 (FIN /40) 34.72 (FIN /40) 20.83 (FIN /40) 20.83 Reserved Reserved Spread Range Selection 50MHz (Automotive) Spreading Range 1.25 2.00 1.00 1.50 1.25 2.00 1.25 2.00 Modulation Rate (FIN/40) 34.72 (FIN/40) 34.72 (FIN/40) 34.72 (FIN/40) 34.72 (FIN/40) 20.83 (FIN/40) 20.83 (FIN/40) 20.83 (FIN/40) 20.83 Spread Range Selection 70MHz (Automotive) Spreading Range 1.00 1.50 0.70 1.00 1.15 2.00 1.15 1.75 Modulation Rate (FIN/40) 34.72 (FIN/40) 34.72 (FIN/40) 34.72 (FIN/40) 34.72 (FIN/40) 20.83 (FIN/40) 20.83 (FIN/40) 20.83 (FIN/40) 20.83 Panel Reduction Notice: information this document subject change without notice. Spread Spectrum Selection P2040A Modulation Selection Table defines possible spread spectrum options. optimal setting should minimize system fullest without affecting system performance. spreading described percentage deviation center frequency. (Note: center frequency frequency external reference input CLKIN, pin1). example, P2040A designed high-resolution, flat panel applications able support (1024 768) flat panel operating 65MHz (FIN) clock speed. spreading selection MRA=0, SR1=1 SR0=0 provides percentage deviation ±0.75% from FIN. This results frequency ModOUT being swept from 64.51 65.49MHz modulation rate 56.24KHz. Refer Modulation Selection Table. example following illustration common reduction method notebook panel already been implemented most leading mobile graphic accelerator manufacturers. Application Schematic Mobile Graphics Controllers 65MHz from graphics accelerator CLKIN ModOUT SSON# 0.1µF Modulated 65MHz signal with ±0.75 deviation modulation rate 56.24KHz. This signal connected back spread +3.3V spectrum input (SSIN) graphics accelerator. P2040A Digital control enable disable Panel Reduction Notice: information this document subject change without notice. Software Simulation P2040A using Alliance EMI-Lator®1 electromagnetic interference simulation software, radiated system level analysis made easier allow quantitative assessment reduction products. simulation engine this software already been characterized correlate electrical characteristics Alliance reduction ICs. following illustration example simulation result. Please visit website www.alsc.com information obtain free copy demonstration EMI-Lator simulation software. Simulation results From EMI-Lator® Panel Reduction Notice: information this document subject change without notice. Absolute Maximum Ratings Symbol VDD, TSTG Storage temperature Operating temperature-Commercial Parameter Voltage with respect Ground Rating +7.0 +125 P2040A Unit Operating temperature Automotive +125 Note: These stress ratings only implied functional use. Exposure absolute maximum ratings prolonged periods time affect device reliability. Electrical Characteristics Symbol ZOUT Input voltage Input high voltage Input current (pull-up resistor inputs SR0, MRA) Input high current (pull-down resistor input SSON#) Output voltage (VDD Output high voltage (VDD Static supply current standby mode Dynamic supply current (3.3V 10pF loading) Operating voltage Power-up time (first locked cycle after power Clock output impedance Parameter 0.18 Unit Electrical Characteristics Symbol fOUT tLH* tHL* Input frequency Output frequency Output rise time (measured 0.8V 2.0V) Output fall time (measured 2.0V 0.8V) Jitter (cycle cycle) Parameter Unit Output duty cycle *tLH measured into capacitive load 15pF Panel Reduction Notice: information this document subject change without notice. Package Information 8-Pin SOIC P2040A Symbol Dimensions inches 0.071 0.010 0.069 0.020 0.01 0.202 0.164 Dimensions millimeters 1.45 0.10 1.35 0.31 0.10 4.72 3.75 1.80 0.25 1.75 0.51 0.25 5.12 4.15 1.27 5.70 0.30 6.30 0.70 0.057 0.004 0.053 0.012 0.004 0.186 0.148 0.050 0.224 0.012 0.248 0.028 Panel Reduction Notice: information this document subject change without notice. 8-Pin TSSOP P2040A Dimensions inches Symbol 0.047 0.002 0.031 0.007 0.004 0.114 0.169 0.006 0.041 0.012 0.008 0.122 0.177 Dimensions millimeters 1.10 0.05 0.80 0.19 0.09 2.90 4.30 0.65 6.20 0.45 6.60 0.75 0.15 1.05 0.30 0.20 3.10 4.50 0.026 0.244 0.018 0.260 0.030 Panel Reduction Notice: information this document subject change without notice. P2040A Ordering Information Part Number A2040A-08ST A2040A-08SR A2040A-08TT A2040A-08TR I2040A-08ST I2040A-08SR I2040A-08TT I2040A-08TR P2040A-08ST P2040A-08SR P2040A-08TT P2040A-08TR Part Numbering Guide 2040 Marking A2040A A2040A A2040A A2040A I2040A I2040A I2040A I2040A P2040A P2040A P2040A P2040A Package Type 8-Pin SOIC, TUBE 8-Pin SOIC, TAPE REEL 8-Pin TSSOP, TUBE 8-Pin TSSOP, TAPE REEL 8-Pin SOIC, TUBE 8-Pin SOIC, TAPE REEL 8-Pin TSSOP, TUBE 8-Pin TSSOP, TAPE REEL 8-Pin SOIC, TUBE 8-Pin SOIC, TAPE REEL 8-Pin TSSOP, TUBE 8-Pin TSSOP, TAPE REEL 2500 2500 2500 2500 2500 2500 Qty/reel Temperature -40°C 125°C -40°C 125°C -40°C 125°C -40°C 125°C -40°C 125°C -40°C 125°C -40°C 125°C -40°C 125°C 70°C 70°C 70°C 70°C Flow Prefix: Automotive temperature range (-40°C 125°C) Industrial Temperature range (-40°C 85°C) Commercial temperature range (0°C 70°) Device Number Deviation spread option identifier Device count Package identifier SOIC TUBE SOIC TAPE REEL TSSOP TUBE TSSOP TAPE REEL Panel Reduction Notice: information this document subject change without notice. P2040A Licensed under Patent 5,488,627 5,631,921 Alliance Semiconductor Corporation 2595, Augustine Drive, Santa Clara, 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com Copyright Alliance Semiconductor Rights Reserved Preliminary Information Part Number: P2040A Document Version: v1.0 Copyright 2003 Alliance Semiconductor Corporation. rights reserved. three-point logo, name Intelliwatt trademarks registered trademarks Alliance. other brand product names trademarks their respective companies. Alliance reserves right make changes this document products time without notice. Alliance assumes responsibility errors that appear this document. data contained herein represents Alliance's best data and/or estimates time issuance. Alliance reserves right change correct this data time, without notice. product described herein under development, significant changes these specifications possible. information this product data sheet intended general descriptive information potential customers users, intended operate provide, guarantee warrantee user customer. Alliance does assume responsibility liability arising application product described herein, disclaims express implied warranties related sale and/or Alliance products including liability warranties related fitness particular purpose, merchantability, infringement intellectual property rights, except express agreed Alliance's Terms Conditions Sale (which available from Alliance). sales Alliance products made exclusively according Alliance's Terms Conditions Sale. purchase products from Alliance does convey license under patent rights, copyrights; mask works rights, trademarks, other intellectual property rights Alliance third parties. Alliance does authorize products critical components life-supporting systems where malfunction failure reasonably expected result significant injury user, inclusion Alliance products such life-supporting systems implies that manufacturer assumes risk such agrees indemnify Alliance against claims arising from such use. Panel Reduction Notice: information this document subject change without notice. Other recent searchesSi6981DQ - Si6981DQ Si6981DQ Datasheet SG-8003CE - SG-8003CE SG-8003CE Datasheet SG-8002 - SG-8002 SG-8002 Datasheet SG-8000CE - SG-8000CE SG-8000CE Datasheet MTV112M - MTV112M MTV112M Datasheet MC-4516CD646 - MC-4516CD646 MC-4516CD646 Datasheet APT30DL60HJ - APT30DL60HJ APT30DL60HJ Datasheet
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