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ORCA® ORT4622 Field-Programmable System Chip (FPSC) Four-Channel Mbits/s Backplane Transceiver
Lucent Technologies Microelectronics Group developed solution designers need many advantages FPGA-based design implementation, coupled with high-speed serial backplane data transfer. Mbits/s backplane transceiver offers clockless, high-speed interface interdevice communication board across backplane. built-in clock recovery ORT4622 allows higher system performance, easier-todesign clock domains multiboard system, fewer signals backplane. Network designers will benefit from backplane transceiver network termination device. backplane transceiver offers SONET scrambling/descrambling data streamlined SONET framing, pointer moving, transport overhead handling, plus programmable logic terminate network into proprietary systems. non-SONET applications, SONET functionality hidden from user prior networking knowledge required.
function uses Lucent Technologies Microelectronics Group's proven Mbits/s serial interface core. Four-channel function provides Mbits/s serial interface channel total chip bandwidth Gbits/s (full duplex). LVDS I/Os compliant with EIA*-644, support insertion. data multiplexing/demultiplexing 77.76 byte-wide data processing FPGA logic. On-chip phase-lock loop (PLL) clock meets jitter tolerance specification ITU-T Recommendation G.958 (0.6 UIP-P kHz). Powerdown option receiver perchannel basis. Highly efficient implementation with only overhead 8B10B coding. In-Band management configuration. Streamlined pointer processor (pointer mover) frame alignment system clocks. Built-in boundry scan (IEEE 1149.1 JTAG). FIFOs align incoming data across four channels STS-48 (2.5 Gbits/s) operation quad STS-12 format). protection supports STS-12/STS-48 redundancy either software hardware control protection switching applications.
Embedded Core Features
Implemented ORCA Series FPGA array. Allows wide range applications SONET network termination application well generic data moving high-speed backplane data transfer. knowledge SONET/SDH needed generic applications. Simply supply data, clock, frame pulse. High-speed interface (HSI) function clock/data recovery serial backplane data transfer without external clocks.
registered trademark Electronic Industries Association. IEEE registered trademark Institute Electrical Electronics Engineers, Inc.
Table ORCA ORT4622-Available FPGA Logic Device ORT4622 Usable System Gates 60K-120K Number LUTs 4032 Number Registers 5304 User User I/Os Array Size Number PFUs
embedded core interface included above gate counts. usable gate count range from logic-only gate count gate count assuming PFUs/SLICs being used RAMs. logic-only gate count includes each PFU/SLIC (counted gates PFU/SLIC), including gates pre-LUT/FF pair (eight PFU), gates SLC/FF pair (one PFU). Each four PIOs counted gates (two FFs, fast-capture latch, output logic, drivers, buffers). PFUs used counted four gates bit, with each capable implementing gates) PFU.
ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
Table Contents
Contents Page Contents Page
Introduction Embedded Core Features FPSC Highlights Software Support Description What FPSC? FPSC Overview FPSC Gate Counting FPGA/Embedded Core Interface ORCA Foundry Development System FPSC Design FPGA Logic Overview Logic Logic System Features Routing Configuration More Series Information ORT4622 Overview Device Layout Backplane Transceiver Interface Interface SMacrocell Interface FPGA Interface FPSC Configuration Generic Backplane Transceiver Application Backplane Transceiver Core Detailed Description Macro STransmitter (FPGA Backplane) SReceiver (Backplane FPGA) Powerdown Mode Redundancy Protection Switching Memory Definition Register Types Memory Overview Powerup Sequencing ORT4622 Device FPGA Configuration Data Format Using ORCA Foundry Generate Configuration Data FPGA Configuration Data Frame Stream Error Checking FPGA Configuration Modes Absolute Maximum Ratings Recommend Operating Conditions Electrical Characteristics Circuit Specifications Input Data Jitter Tolerance Generated Output Jitter Input Reference Clock Circuit Specifications Power Supply Decoupling Circuit LVDS LVDS Receiver Buffer Requirements Timing Characteristics Description Timing Timing SLIC Timing Timing Special Function Timing Clock Timing Configuration Timing Readback Timing Input/Output Buffer Measurement Conditions (on-LVDS Buffer) FPGA Output Buffer Characteristics LVDS Buffer Characteristics Termination Resistor LVDS Driver Buffer Capabilities Estimating Power Dissipation ORT4622 Clock Power Information Package Thermal Characteristics Summary FPGA Maximum Junction Temperature Package Thermal Characteristics Package Coplanarity Package Parasitics Package Outline Diagrams Terms Definitions 432-Pin EBGA 680-Pin PBGAM Ordering Information
List Figures
Figure ORCA ORT4622 Block Diagram Figure Architecture ORT4622 Backplane Transceiver Figure Functional Block Diagram Figure Byte Ordering Input/Output Interface STS-12 Mode. Figure Interconnect Streams FIFO. Figure Alignment Four STS-12 Streams Figure Examples Link Alignment Figure Pointer Mover State Machine Figure C1J1 Functionality Figure Stuff Bytes. Figure Serial Configuration Data Format- Autoincrement Mode.
Lucent Technologies
ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
Table Contents (continued)
Figure Page Table Page
Figure Serial Configuration Data Format- Explicit Mode. Figure Sample Power Supply Filter Network Analog Power Supply Pins. Figure Transmit Parallel Port Timing (Backplane FPGA). Figure Transmit Transport Delay (FPGA Backplane). Figure Receive Parallel Port Timing (Backplane FPGA). Figure Protection Switch Timing Figure Input Serial Port Timing (FPGA Backplane). Figure Output Serial Port Timing (Backplane FPGA). Figure Write Transaction Figure Read Transaction. Figure Test Loads Figure Output Buffer Delays Figure Input Buffer Delays Figure Sinklim Figure Slewlim Figure Fast Figure Sinklim Figure Slewlim Figure Fast Figure LVDS Driver Receiver Associated Internal Components Figure LVDS Driver Receiver. Figure LVDS Driver. Figure Package Parasitics
List Tables
Table ORCA ORT4622-Available FPGA Logic. Table ORT4622 Array Table Transmitter LVDS Output (Transparent Mode). Table Transmitter LVDS Output (TOH Insert Mode) Table Valid Starting Positions STS-Mc Table Receiver (Output Parallel Bus). Table C1J1 Functionality Table Structural Register Elements Table Memory Table Memory Descriptions Table Configuration Frame Format Contents. Table Configuration Modes Table Absolute Maximum Ratings. Table Recommend Operating Conditions
Table General Electrical Characteristics Table Electrical Characteristics FPGA I/O.40 Table Electrical Characteristics Embedded Core Other than LVDS Table Jitter Tolerance Table Table Input Reference Clock Table LVDS Driver Data Table LVDS Driver Data Table LVDS Receiver Data Table LVDS Receiver Data Table LVDS Receiver Power Consumption Table LVDS Operating Parameters.44 Table Derating Commercial Devices (I/O Supply VDD).45 Table Derating Commercial Devices (I/O Supply VDD2).45 Table ORT4622 Embedded Core FPGA Interface Clock Operation Frequencies Table Timing Requirements (Transmit Parallel Port Timing) Table Timing Requirements (Transmit Transport Delay) Table Timing Requirements (Receive Parallel Port Timing) Table Timing Requirements (Protection Switch Timing) Table Timing Requirements (TOH Input Serial Port Timing) Table Timing Requirements (TOH Output Serial Port Timing) Table Timing Requirements (CPU Write Transaction) Table Timing Requirements (CPU Read Transaction) Table Embedded Block Power Dissipation Table FPGA Common-Function Description Table FPSC Function Description Table Embedded Core/FPGA Interface Signal Description Table Embedded Core/FPGA Interface Signal Locations Table 432-Pin EBGA Pinout Table 680-Pin PBGAM Pinout Table ORCA ORT4622 Plastic Package Thermal Guidelines Table ORCA ORT4622 Package Parasitics.84 Table Voltage Options Table Temperature Options Table Package Type Options Table ORCA Series Package Matrix
Lucent Technologies Inc.
ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
Embedded Core Features
(continued)
Pseudo-SONET protocol including A1/A2 framing. SONET scrambling descrambling required ones density (optional). Selected transport overhead (TOH) bytes insertion extraction interdevice communication serial link.
FPSC Highlights
bined with FPGA logic create complex functions, such digital phase-locked loops, frequency counters, frequency synthesizers clock doublers. PCMs provided device. True internal 3-state, bidirectional buses with simple control provided SLIC. PFU, configurable single dual port. Create large, fast RAM/ROM blocks (128 only eight PFUs) using SLIC decoders bank drivers. Built-in boundary scan (IEEE 1149.1 JTAG) TS_ALL testability function 3-state pins.
Implemented embedded core ORCA Series FPSC architecture. Allows user integrate core with 120K gates programmable logic (all device) provides user I/Os addition embedded core pins. FPGA portion retains features ORCA Series FPGA architecture: High-performance, cost-effective, 0.25 5-level metal technology. Twin-quad programmable function unit (PFU) architecture with eight 16-bit look-up tables (LUTs) PFU, organized nibbles nibble- byte-wide functions. Allows mixed arithmetic logic functions single PFU. Softwired LUTs (SWL) allow fast cascading three levels logic single PFU. Supplemental logic interconnect cell (SLIC) provides 3-statable buffers, 10-bit decoder, PAL*-like AND-OR-INVERT (AOI) each programmable logic cell (PLC). three ExpressCLK inputs allow extremely fast clocking signals off-chip plus access internal general clock routing. Dual-use microprocessor interface (MPI) used configuration, well generalpurpose interface FPGA. Glueless interface i960 PowerPC processors with userconfigurable address space provided. Programmable clock manager (PCM) adjusts clock phase duty cycle input clock rates from MHz. com-
High-speed, on-chip interface provided between FPGA logic embedded core reduce bottlenecks typically found when interfacing off-chip.
Software Support
Supported ORCA Foundry software thirdparty tools implementing ORCA Series devices simulation/timing analysis with embedded core functions. Embedded core configuration options simulation netlists generated FPSC Configuration Manager utility.
trademark Advanced Micro Devices, Inc. i960 registered trademark Intel Corporation. PowerPC registered trademark International Business Machines Corporation.
Lucent Technologies Inc. Lucent Technologies Inc.
ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
FPGA/Embedded Core Interface
interface between FPGA logic embedded core designed look like FPGA I/Os from FPGA side, simplifying interface signal routing providing unified approach with general FPGA design. Effectively, FPGA designed signals were going device embedded core, on-chip interface much faster than going off-chip requires less power. delays interface precharacterized accounted ORCA Foundry Development System. Clock spines also pass across FPGA/embedded core boundary. This allows fast, low-skew clocking between FPGA embedded core. Many special signals from FPGA, such DONE global set/reset, also available embedded core, making possible fully integrate embedded core with FPGA system. even greater system flexibility, FPGA configuration RAMs available embedded core. This allows user-programmable options embedded core, turn allowing greater flexibility. Multiple embedded core configurations designed into single device with user-programmable control over which configurations implemented, well capability change core functionality simply reconfiguring device.
Description
What FPSC?
FPSCs, field-programmable system chips, devices that combine field-programmable logic with ASIC mask-programmed logic single device. FPSCs provide time market flexibility FPGAs, design effort savings using soft intellectual property (IP) cores, speed, design density, economy ASICs.
FPSC Overview
Lucent's Series FPSCs created from Series ORCA FPGAs. create Series FPSC, several rows programmable logic cells (see FPGA Logic Overview section FPGA logic details) removed from Series ORCA FPGA, area replaced with embedded logic core. Other than replacing some FPGA gates with ASIC gates, greater than 10:1 efficiency, none FPGA functionality changed-all Series FPGA capability retained: MPI, PCMs, boundary scan, etc. rows programmable logic replaced bottom device, allowing pins bottom sides replaced rows used pins embedded core. remainder device pins retain their FPGA functionality special function FPGA pins within embedded core area. embedded cores take many forms generally come from Lucent Technologies ASIC libraries. Other offerings allow customers supply their core functions creation custom FPSCs.
ORCA Foundry Development System
ORCA Foundry Development System used process design from netlist configured FPSC. This system used design onto ORCA architecture then place route using ORCA Foundry's timing-driven tools. development system also includes interfaces libraries for, other popular tools design entry, synthesis, simulation, timing analysis. ORCA Foundry Development System interfaces front-end design entry tools provides tools produce configured FPSC. design flow, user defines functionality FPGA portion FPSC embedded core settings points design flow: design entry stream generation stage. Following design entry, development system's map, place, route tools translate netlist into routed FPSC. static timing analysis tool provided determine device speed, backannotated netlist created allow simulation.
FPSC Gate Counting
total gate count FPSC embedded core (standard-cell/ASIC gates) FPGA gates. Because FPGA gates generally expressed usable range with nominal value, total FPSC gate count sometimes expressed same manner. Standard-cell ASIC gates are, however, times more silicon area efficient than FPGA gates. Therefore, FPSC with embedded function gate equivalent FPGA with much larger gate count.
Lucent Technologies Inc. Lucent Technologies Inc.
ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
Description (continued)
Timing simulation output files from ORCA Foundry also compatible with many third-party analysis tools. stream generator then used generate configuration data which loaded into FPSC's internal configuration RAM. When using stream generator, user selects options that affect functionality FPSC. Combined with front-end tools, ORCA Foundry produces configuration data that implements various logic routing options discussed this data sheet.
FPSC Design
Development facilitated FPSC design which, together with ORCA Foundry third-party synthesis simulation engines, provides software documentation required design verify FPSC implementation. Included FPSC configuration manager, gate-level structural netlists, necessary synthesis libraries, complete online documentation. kit's software couples with ORCA Foundry, providing seamless FPSC design environment. More information obtained visiting ORCA website contacting local sales office, both listed last page this document.
ORCA Series FPGA logic consists three basic elements: programmable logic cells (PLCs), programmable input/output cells (PICs), system-level features. array PLCs surrounded PICs. Each contains programmable function unit (PFU), supplemental logic interconnect cell (SLIC), local routing resources, configuration RAM. Most FPGA logic performed PFU, decoders, PAL-like functions, 3-state buffering performed SLIC. PICs provide device inputs outputs used register signals perform input demultiplexing, output multiplexing, other functions output signals. Some system-level functions include microprocessor interface (MPI) programmable clock manager (PCM).
Logic
Each within contains eight 4-input (16-bit) look-up tables (LUTs), eight latches/flip-flops (FFs), additional flip-flop that used independently with arithmetic functions. organized twin-quad fashion: sets four LUTs that controlled independently. LUTs also combined arithmetic functions using fast-carry chain logic either 4-bit 8-bit modes. carry-out either mode registered ninth pipelining. Each also configured synchronous single- dual-port ROM. latches) obtain input from outputs directly from invertible inputs, they tied high tied low. also have programmable clock polarity, clock enables, local set/reset. SLIC connected routing resources outputs PFU. contains 3-state, bidirectional buffers logic perform 10-bit function decoding, AND-OR with optional INVERT (AOI) perform PAL-like functions. 3-state drivers SLIC their direct connections outputs make fast, true 3-state buses possible within FPGA logic, reducing required routing allowing real-world system performance.
FPGA Logic Overview
ORCA Series FPGA logic generation SRAM-based FPGA logic built successful Series FPGA line from Lucent Technologies Microelectronics Group, with enhancements innovations geared toward today's high-speed designs single chip. Designed from start synthesis friendly reduce place route times while maintaining complete routability ORCA Series devices, Series more than doubles logic available each logic block incorporates system-level features that further reduce logic requirements increase system speed. ORCA Series devices contain many patented enhancements offered variety packages, speed grades, temperature ranges.
Lucent Technologies Inc. Lucent Technologies Inc.
ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
Routing
abundant routing resources ORCA Series FPGA logic organized route signals individually buses with related control signals. Clocks routed low-skew, high-speed distribution network sourced from logic, externally from pad, from very fast ExpressCLK pins. ExpressCLKs glitchlessly independently enabled disabled with programmable control signal using StopCLK feature. improved routing resources similar patented intra-PLC routing resources provide great flexibility moving signals from PIOs. This flexibility translates into improved capability route designs required speeds when signals have been locked specific pins.
Description (continued)
Logic
Series addresses demand everincreasing system clock speeds. Each contains four programmable inputs/outputs (PIOs) routing resources. input side, each contains fastcapture latch that clocked ExpressCLK. This latch followed latch/FF that clocked system clock from internal general clock routing. combination provides very setup requirements zero hold times signals coming on-chip. also used demultiplex input signal, such multiplexed address/data signal, register signals without explicitly building demultiplexer. input signals available array from each PIO, ORCA Series capability input clock other global input maintained. output side each PIO, outputs from array routed each output flip-flop, logic associated with each pad. output logic associated with each allows multiplexing output signals other functions output signals. output combination with output signal multiplexing, particularly useful registering address signals multiplexed with data, allowing full clock cycle data propagate output. buffer associated with each same ORCA Series buffer.
Configuration
FPGA logic's functionality determined internal configuration RAM. FPGA logic's internal initialization/configuration circuitry loads configuration data powerup under system control. loaded using several configuration modes, including serial EEPROM, microprocessor interface, embedded function core.
More Series Information
more information Series FPGAs, please refer Series FPGA data sheet, available ORCA worldwide website contacting Lucent Technologies directed back this data sheet.
System Features
Series also provides system-level functionality means dual-use microprocessor interface (MPI) innovative programmable clock manager (PCM). These functional blocks allow easy glueless system interfacing capability adjust varying conditions today's high-speed systems. Since these other Series features available every Series FPSC, they also interface embedded core providing easier system integration.
Lucent Technologies Inc. Lucent Technologies Inc.
ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
ORT4622 Overview
Device Layout
ORT4622 FPSC provides high-speed backplane transceiver combined with FPGA logic. device based OR3L125B FPGA. OR3L125B array programmable logic cells (PLCs). ORT4622, bottom rows PLCs array were replaced with embedded backplane transceiver core. ORT4622 embedded core comprises macrocell, synchronous transport module (STM) macrocell, interface, LVDS I/Os. four full-duplex channels perform data transfer, scrambling/descrambling framing rate Mbits/s. Figure shows ORT4622 block diagram. Table shows schematic view ORT4622. upper portion device array PLCs surrounded left, top, right programmable input/output cells (PICs). bottom array core interface cells (CICs) connecting embedded core region. embedded core region contains backplane transceiver functionality device. surrounded left, bottom, right backplane transceiver dedicated I/Os well power special function FPGA pins. Also shown interquad routing blocks (hIQ, vIQ) present Series FPGA devices. System-level functions (located corners array), routing resources, configuration shown Table
Backplane Transceiver Interface
advantage ORT4622 FPSC bring specific networking functions early market presence with programmable logic FPGA system. Mbits/s backplane transceiver core allows ORT4622 communicate across backplane given board aggregate speed Gbits/s, providing physical medium high-speed asynchronous serial data transfer between system devices. This device intended for, limited connecting terminal equipment SONET/SDH Asystems. networking applications, ORT4622 offers pseudo SONET framer scrambler/descrambler interface capable frame synchronization insertion/extraction selectable transport overhead bytes SONET scrambling descrambling four STS-12 (622 Mbits/s) channels. channels synchronized each other user-provided frame pulse. ORT4622 also provides STS-48 (2.5 Gbits/s) operation across four channels where each channel STS-12 format. pseudo-SONET framer OR4622 designed with reduced SONET framing algorithm. pointer processing capability more suitable error rate intersystem data communication, particular backplane transceiver applications. Figure shows architecture ORT4622 backplane transceiver core.
Mbits/s DATA
S
FULLDUPLEX SERIAL CHANNELS Mbits/s DATA
LVDS I/Os
CLOCK/DATA RECOVERY
BYTEWIDE DATA
POINTER MOVER SCRAMBLING FIFO ALIGNMENT PROCESSOR
FPGA LOGIC
STANDARD FPGA I/Os
5-8113(F)
Figure ORCA ORT4622 Block Diagram
Lucent Technologies Inc. Lucent Technologies Inc.
ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
ORT4622 Overview (continued)
Table ORT4622 Array IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII
PT10 PT11 PT12 PT13 PT14
IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII
PT15 PT16 PT17 PT18 PT19 PT20 PT21 PT22 PT23 PT24 PT25 PT26 PT27 PT28
IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII
IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII
PR10
PL10
PR11
PL11
PR12
PL12
PR13
PL13
PR14
IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII
PL14
IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII
PR15
PL15
ASB1
ASB2
ASB3
ASB4
ASB5
ASB6
ASB7
ASB8
ASB9
ASB10
ASB11
ASB12
ASB13
ASB14
ASB15
ASB16
ASB17
ASB18
ASB19
ASB20
ASB21
ASB22
ASB23
ASB24
ASB25
ASB26
ASB27
ASB28
PR16
PL16
PR17
PL17
PR18
PL18
EMBEDDED CORE AREA
IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII
IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII
Lucent Technologies Inc. Lucent Technologies Inc.
ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
ORT4622 Overview (continued)
Interface
high-speed interconnect (HSI) macrocell used clock/data recovery MUX/deMUX between 77.76 byte-wide internal data buses Mbits/s external serial links. interface receives four Mbits/s serial input data streams from LVDS inputs provides four independent 77.76 byte-wide data streams recovered clock Smacro. There requirement alignment since SONET type framing will take place inside ORT4622 core. transmit, converts four byte-wide 77.76 data streams serial streams Mbits/s LVDS outputs.
Interface
embedded core dedicated, asynchronous, MPC860 compatible, interface that used device setup, control, monitoring. Dual sets pins this interface with stream configurable scheme provide designers convenient flexible option configuration. pins goes chip allowing direct connection with onboard CPU. Another pins available FPGA logic allowing stand-alone system free external interface, itegration into Series FPGA interface. interface composed 8-bit data bus, 7-bit address bus, chip select signal, read/write signal, interrupt signal.
FPGA Interface SMacrocell
Sportion embedded core consists transmitter (Tx) receiver (Rx) sections. receiver receives four byte-wide data streams 77.76 associated clocks from HSI. section, incoming streams SONET framed descrambled before they written into FIFO which absorbs phase delay variations allows shift system clock. then extracted sent four serial ports. pointer Mover consists three blocks: pointer interpreter, elastic store, pointer generator. pointer interpreter finds synchronous transport signal (STS) synchronous payload envelopes (SPE) places into small elastic store from which pointer generator will produce four byte-wide STS-12 streams data that aligned system timing pulse. section, transmitted data each channel received through parallel serial port from FPGA circuit. bytes received from serial input port optionally inserted from programmable registers serial inputs STS-12 frame processor. Each four parallel input buses synchronized free-running system clock. Then data transferred HSI. Smacrocell also scrambler/descrambler disable feature, allowing user disable scrambler transmitter descrambler receiver. Also, unused channels disabled reduce power dissipation. FPGA logic will receive/transmit frame-aligned streams 77.76 data (maximum four streams each direction) from/to backplane transceiver embedded core. frames transmitted FPGA will aligned FPGA frame pulse which will provided FPGA user's logic Smacro. frames received from FPGA logic will aligned system frame pulse that will supplied Smacro from FPGA user's logic.
Lucent Technologies Inc. Lucent Technologies Inc.
ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
ORT4622 Overview (continued)
LINE LBPK (SOFT CTL) PROC. QUAD CHANNEL TRANSMITTER PROCESSOR FRAME PROC. (MACRO)
LVDS
PROCESSOR FRAME PROC. (MACRO)
LVDS
PROCESSOR FRAME PROC. (MACRO)
LVDS
PROCESSOR FRAME PROC. (MACRO) 77.76 77.76 Clks
LVDS
LINE FRAME PROT SWITCH FPGA SIGNALS SOFT SOFT DATA DATA SOFT DATA DATA PROT SWITCH SOFT SOFT DATA DATA SOFT DATA DATA TOH_EN
SOFT SOFT
FRAME CLOCK
FDBK
77.76 (MACROCELL)
LVDS
POINTER MOVER STS48 FIFO
77.76
(MACROCELL)
LVDS
77.76
(MACROCELL)
LVDS
SOFT
77.76
(MACROCELL)
LVDS
LVDS LPBK (SOFT CTL)
FPEN FRAME SOFT
PROCESSOR
QUAD CHANNEL RECEIVER
INTERFACE (ASYNC) ADDR DATA RST_N RD/WR_N INT_N CS_N
DEVICE FPGA SIGNALS (BIT STREAM SELECTABLE) 5-8576
Figure Architecture ORT4622 Backplane Transceiver Lucent Technologies Inc. Lucent Technologies Inc.
DEVICE
SYSTEM FRAME SYSTEM CLOCK
SYSTEM CLOCK (77.76 MHz)
ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
ORT4622 Overview (continued)
FPSC Configuration
Configuration ORT4622 occurs stages, FPGA stream configuration embedded core setup. FPGA Configuration Prior becoming operational, FPGA goes through sequence states, including powerup initialization, configuration, start-up, operation. FPGA logic configured standard FPGA stream configuration means discussed Series FPGA data sheet. Additionally, ORT4622, location interface embedded core, either device pins FPGA/embedded core boundary, configured FPGA configuration defined ORT4622 design kit. default configuration sets interface pins active. simple microprocessor emulation soft Intellectual Property (IP) core that uses very small FPGA logic available from Lucent. This microprocessor core sets embedded core state machine allows ORT4622 work independent system without external microprocessor interface. Embedded Core Setup embedded core operation embedded core interface. options operation core configured according device register presented detailed description section this data sheet. During powerup sequence, ORT4622 device (FPGA programmable circuit core) held reset. LVDS output buffers other output buffers held 3-state. flip-flops core area reset state, with exception boundry scan shift registers, which only reset Boundary Scan Reset. After powerup reset, FPGA start configuration. During FPGA configuration, ORT4622 core will held reset local interface signals forced high, following active-high signals (PROT_SWITCH_A, PROT_SWITCH_C, TX_TOH_CK_EN, SYS_FP, LINE_FP) forced low. CORE_READY signal sent from embedded core FPGA held low, indi-
cating core ready interact with FPGA logic. FPGA configuration sequence, CORE_READY signal will held SYS_CLK cycles after DONE, TRI_IO RST_N (core global reset) high. Then will active-high, indicating embedded core ready function interact with FPGA programmable circuit. During FPGA reconfiguration when DONE TRI_IO low, CORE_READY signal sent from core FPGA will held again indicate embedded core ready interact with FPGA logic. During FPGA partial configuration, CORE_READY stays active. same FPGA configuration sequence described previously will repeat again. initialization embedded core consists steps: register configuration synchronization alignment FIFO. order configure embedded core, registers need unlocked writing 0xA0 address 0x04 writing 0x01 address 0x05. Control registers 0x04 0x05 lock registers. output data, serial port, clock frame pulse controlled 3-state registers (the registers 3-state output control optional; these output 3-state enable signals brought across local interface available FPGA side), next step activate 3state output signals taking them functional state from high-impedance state. This done writing 0x01 correspond bits channel registers 0x20, 0x38, 0x50, 0x68. 3-state control done FPGA logic external logic instead embedded core registers, this step should done that particular control logic also. addition, synchronization selected streams recommended some networking systems applications. This resync alignment FIFO after enabled channels have valid frame pulse. Here procedures: streams aligned, including disabled streams, into their required alignment mode. Force AIS-L streams synchronized (refer register map, write 0x01 register 0x20, 0x38, 0x50, 0x68). Wait four frames. Write 0x01 FIFO alignment resync register, register 0x06. Wait four frames. Release AIS-L streams (write register 0x20, 0x38, 0x50, 0x68). This procedures allows normal data flow through embedded core.
Lucent Technologies Inc. Lucent Technologies Inc.
ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
Generic Backplane Transceiver Application
combination ORT4622 soft cores provides generic data moving solution non-SONET applications. There requirement SONET knowledge users. that needed supply embedded core interface with data, clock, frame pulse. provision registers also need this done through either FPGA state machine FPGA section (VHDL code available from Lucent). frame pulse must supplied SYS_FP signal. generic applications, frame pulse created FPGA logic from 77.76 SYS_CLK using simple resettable counter (the frame pulse should only high cycle SYS_CLK). VHDL core that automatically provides frame pulse available from Lucent. Byte-wide data then sent each transmit channels follows: first bytes transferred will invalid data (replaced overhead), where first byte sent rising edge SYS_CLK when SYS_FP high. next 1044 byte positions filled with valid data. This will repeat total nine times invalid bytes followed 1044 valid bytes) which time next frame pulse will found. Thus, (96.7%) data bytes sent valid user data. receive side, pulse must again supplied SYS_FP. this case, however, only signal DATA_RX*_SPE must monitored each channel, where high value this signal means valid data. Again bytes received (96.7%) will valid data. order provide easy user interface transfer arbitrary data streams through ORT4622, Lucent provides soft Intellectual Property (IP) core called protocol independent framer, PI-Framer. This block transfers user format described above allows smoothing/rate transfer this user data. This framer works with single channel Mbits/s, channels 1.25 Gbits/s, across four channels Gbits/s.
Backplane Transceiver Core Detailed Description
Macro
high-speed interface (HSI) provides physical medium high-speed asynchronous serial data transfer between ORT4622 other devices. devices mounted same board mounted different boards connected through shelf backplane. Mbits/s macro four-channel clock phase select (CPS) data retime function with serial-to-parallel demultiplexing incoming data stream parallel-to-serial multiplexing outgoing data. macro consists three functionally independent blocks: receiver, transmitter, synthesizer shown Figure synthesizer block receives 77.76 reference clock input, provides phase-locked 622.08 clock transmitter block phase control signal receiver block. synthesizer block common asset shared four receive transmit channels. receiver receives four channels differential 622.08 Mbits/s serial data without clock LVDS receive inputs. received data must scrambled, conforming SONET STS-12 STM-4 data formats using either sequence. characteristic polynomial characteristic polynomial ORT4622 supplies default scrambler using sequence. clock phase select data retime (CPS/DR) module performs clock recovery data retiming function using phase control information. resultant 622.08 Mbits/s data clock then passed deserializer module, which performs serial-to-parallel conversion provides 77.76 Mbits/s parallel data clock output. transmitter receives four channels 77.76 Mbits/s parallel data that synchronous reference clock inputs. serializer performs parallel-to-serial conversion using 622.08 clock provided PLL/synthesizer block. Mbits/s serial data streams then transmitted through LVDS drivers.
Lucent Technologies Inc. Lucent Technologies Inc.
ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
Backplane Transceiver Core Detailed Description (continued)
LVDS HDIN Mbits/s SELECT DEMUX Mbits/s SERIAL PARALLEL Mbits/s DATA BUFFER CLOCK/DATA ALIGNMENT Mbits/s DATA (77.76 Mbits/s DATA)
LOOPBKEN HSI_RX LOOPBACK
PHASE ADJUSTMENT
CLOCK
(77.76 CLOCK)
(77.76 CLOCK) REF78 REXT (RESISTOR) 622.08 SYNTHESIZER
622.08 CLOCK 77.76 PARALLEL Mbits/s SERIAL LOOPBACK BS-MUX
Mbits/s DATA
LVDS BUFFER
(77.76 Mbytes DATA)
HDOUT Mbits/s
77.76 Mbytes DATA
HSI_TX
BOUNDARYSCAN CONTROL
BSCANEN
5-8592
Figure Functional Block Diagram
Lucent Technologies Inc. Lucent Technologies Inc.
ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
data communication channel (DCC, D1-D3) line data communication channel (DCC, D4-D12) insertion (for intercard communications channel); scrambling outgoing data stream with optional scrambler disabling; optional stream disabling. When ORT4622 used nonnetworking applications generic high-speed backplane data mover, serial ports unused used slow-speed off-channel communication between devices. Data received parallel optionally scrambled transferred LVDS outputs. Byte Ordering Information core supports quad STS-12 mode operation input/output ports. STS-48 also supported when received quad STS-12 format. When operating quad STS-12 mode, each independent byte streams carries entire STS-12 within Figure reveals byte ordering individual STS-12 streams STS-48 operation. Note that recovered data will always continue same order transmitted.
Backplane Transceiver Core Detailed Description (continued)
STransmitter (FPGA Backplane)
Shas four STS-12 transmit channels which treated single STS-48 channel. general, transmitter circuit receives four byte-wide 77.76 data from FPGA, which nominally represents four STS-12 streams This data synchronized system (reference) clock, system frame pulse from FPGA logic. Transport overhead bytes then optionally inserted into these streams, streams forwarded HSI. byte timing pulses required isolate individual overhead bytes (e.g., D1-D3, etc.) generated internally based system frame pulse (SYS_FP) received from FPGA logic. streams operate byte-wide 77.76 modes. processor operates from 77.76 supports following signals: insertion optional corruption; pass transparently; BIP-8 parity calculation (after scrambling) byte insertion optional corruption (before scrambling); optional insert; optional S1/M0 insert; optional E1/F1/E2 insert; optional section
STS-12 STS-12 STS-12 STS-12
STS-48 QUAD STS-12 FORMAT
QUAD STS-12
STS-12 STS-12 STS-12 STS-12
5-8574
Figure Byte Ordering Input/Output Interface STS-12 Mode
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ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
Backplane Transceiver Core Detailed Description (continued)
Transport Overhead Band Communication byte used Band configuration, service, management since carried along same channel data. ORT4622, Band signaling efficiently utilized, since total cost overhead only 3.3%. Transport Overhead Insertion (Serial Link) serial links used insert bytes into transmit data. transmit data TOH_CLK_EN retimed TOH_CLK order meet setup hold specifications device. retimed data shifted into 288-bit (36-byte 8-bit) shift register then multiplexed 8-bit inserted into byte-wide data stream. Insertion from these serial links pass-through from byte-wide data under software control. Transport Overhead Byte Ordering (FPGA Backplane) transparent mode, data received parallel input transferred, unaltered, serial LVDS output. However, byte STS#1 always replaced with calculated value (the bytes following replaced with zeros). Also, bytes STS-1s always regenerated. serial port used transparent mode operation. insert mode, bytes transferred, unaltered, from input parallel serial LVDS output. other hand, bytes received from serial input port inserted STS12 frame before being sent LVDS output. Although bytes from STS-1s transferred into device from each serial port, them inserted frame. There three hardcoded exceptions byte insertion:
addition above hard-coded exceptions, source some bytes further controlled software. When configured pass-through mode, specific bytes must flow transparently from parallel input. Note that blocks STS-1 bytes forming STS-12 controlled whole. There software controls channel, listed below:
Source bytes STS-1s bytes) specified control (per channel control). Source bytes STS-1s bytes) specified control (per channel control). Source bytes STS-1s bytes) specified control (per channel control). Source bytes STS-1s bytes) specified control (per channel control). Source bytes STS-1s bytes) specified control (per channel control). Source bytes STS-1s bytes) specified control (per channel control). Source bytes STS-1s bytes) specified control (per channel control). Source bytes STS-1s bytes) specified control (per channel control). Source bytes STS-1s bytes) specified control (per channel control). Source bytes STS-1s bytes) specified control (per channel control). Source bytes STS-1s bytes) specified control (per channel control). Source bytes STS-1s bytes) specified control (per channel control). Source bytes STS-1s bytes) specified control (per channel control). Source bytes STS-1s bytes) specified control (per channel control). Source bytes STS-1s bytes) specified control (per channel control).
Framing bytes (A1/A2 STS-1s) inserted from serial input bus. Instead, they always regenerated. Parity byte STS#1) inserted from serial input bus. Instead, always recalculated (the bytes following replaced with zeros).
reconstruction dependent transmitter mode operation. transparent mode operation, bytes LVDS output shown Table
Pointer bytes (H1/H2/H3 STS-1s) inserted from serial input bus. Instead, they always flow transparently from parallel input LVDS output.
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ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
Backplane Transceiver Core Detailed Description (continued)
Table Transmitter LVDS Output (Transparent Mode)
Regenerated bytes. Transparent bytes from parallel input port.
Insert mode operation, bytes LVDS output shown following Table. This also shows order which data transferred serial interface, starting with must significant first byte. first first byte replaced even parity check over bytes from previous frame. Table Transmitter LVDS Output (TOH Insert Mode)
Regenerated bytes. Inserted transparent bytes. Blocks STS-1 bytes controlled whole. There controls/channel: K1/K2, S1/M0, E1/F1/E2, D10, D11, D12. Transparent bytes (from parallel input port). Inserted bytes from serial input port.
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ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
Backplane Transceiver Core Detailed Description (continued)
A1/A2 Frame Insert Testing bytes provide special framing pattern that indicates where STS-1 begins stream. bytes each STS-12 0xF6, bytes STS-12 0x28 when overridden with user-specified value testing. A1/A2 testing (corruption) controlled stream A1/A2 error insert register. When A1/A2 corruption detection particular stream, A1/A2 values corrupted A1/A2 value registers sent number frames defined corrupted A1/A2 frame count register. When corrupted A1/A2 frame count register zero, A1/A2 corruption will continue until A1/A2 error insert register cleared. per-device basis, byte values set, well number frames corruption. Then, insert specified A1/A2 values, each channel enable register. When enable register set, A1/A2 values corrupted number specified number frames corrupt. insert errors again, per-channel fault insert register must cleared, again. Only last first corrupted. Calculation Insertion interleaved parity (BIP-8) error check even parity over bits STS-1 frame. defined first STS-1 STS-N only. calculation block computes BIP-8 code, using even parity over bits previous STS-12 frame after scrambling inserted byte current STS-12 frame before scrambling. Per-bit corruption controlled force BIP-8 corruption register (register address 0F). this register, corresponding calculated BIP-8 inverted before insertion into byte position. Each stream independent fault insert register that enables inversion bytes. bytes other STS1s stream filled with zeros.
Stream Disable When disabled appropriate stream enable register, prescrambled data stream ones, feeding HSI. macro powered down per-stream basis, LVDS outputs. Scrambler data stream scrambled using frame synchronous scrambler sequence length 127. scrambling function disabled software. generating polynomial scrambler This polynomial conforms standard SONET STS-12 data format. scrambler reset 1111111 first byte (byte following byte twelfth STS-1). That byte subsequent bytes scrambled exclusive-ORed, with output from byte-wise scrambler. scrambler runs continuously from that byte throughout remainder frame. bytes scrambled. System Frame Pulse Line Frame Pulse System frame pulse (for transmitter) line frame pulse (for receiver) generated FPGA logic. A1/A2 framing used link locating frame location. frames sent FPGA aligned FPGA frame pulse LINE_FP which provided FPGA Smacro. frames sent from FPGA Swill aligned frame pulse SYS_FP that supplied Smacro. either directions, system frame pulse line frame pulse active system clock cycle, indicating location byte STS#1. They common four channels.
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ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
calculation block computes BIP-8 (Bit Interleaved Parity 8-bits) code, using even parity over bits previous STS-12 frame before descrambling; this value checked against byte current frame after descrambling. per-stream error counter incremented each that error. error counter read interface. Descrambling. streams descrambled using frame synchronous descrambler sequence length with generating polynomial A1/A2 framing bytes, section trace byte (J0) growth bytes (Z0) descrambled. descrambling function disabled software. AIS-L Insertion. Alarm indication signal (AIS) continuous stream unframed sent alert downstream equipment that near-end terminal failed, lost signal source, been temporarily taken service. enabled AIS_L force register, AIS-L inserted into received frame writing ones bytes descrambled stream. AIS-L Insertion Out-of-Frame. enabled register, AIS-L inserted into received frame writing ones bytes descrambled stream when framer indicates that out-of-frame condition exists. Internal Parity Generation Even parity generated data bytes routed parallel with data checked before protection switch parallel output. FIFO Alignment (Backplane FPGA) alignment FIFO allows transfer data system clock. FIFO sync block (Figure allows system configured allow frame alignment multiple slightly varying data streams. This optional alignment ensures that matching STS-12 streams will arrive FPGA perfect data sync. frame alignment configurable allow possibility fully independent (i.e., total frame misalignment) STS-12s.
Backplane Transceiver Core Detailed Description (continued)
SReceiver (Backplane FPGA)
ORT4622 four receiving channels that treated STS-48 stream, treated independent channels. Incoming data received through LVDS serial ports data rate Mbits/s. receiver handle data streams with frame offsets bytes which would timing skews between cards along backplane traces. received data streams processed STM, then passed through boundary FPGA logic. Framer Block framer block, Figure takes byte-wide data from HSI, outputs byte-aligned, byte-wide data stream sync pulse. framer algorithm determines out-of-frame/in-frame status incoming data will cause interrupts both errored frame out-of-frame (OOF) state. framer detects A1/A2 framing pattern generates frame pulse. When framer detects OOF, will generate interrupt. Also, framer detects errored frame increments A1/A2 frame error counter. counter monitored processor compile performance status quality backplane. Because ORT4622 intended between another ORT4622 other devices backplane, there only errored frame state. Thus after transitions missed, state machine goes into state there severely errored frame (SEF) loss-of-frame (LOF) indication. Calculate Descramble (Backplane FPGA) Each block receives byte-wide scrambled 77.76 data frame sync from framer. Since each independently clocked, block operates individual streams. Timing signals required locate overhead bytes extracted generated internally based frame sync. block produces byte-wide (optionally) descrambled data output frame sync alignment FIFO block.
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ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
Backplane Transceiver Core Detailed Description (continued)
alignment. read control block synched only once start-up; further synchronization software controlled. action resynching read control block will always cause loss data. register allows read control block resynched. Link Alignment. general operation link alignment algorithm wait clocks (i.e., half FIFO) from arriving frame pulse then signal read control block begin reading. perfectly aligned frame pulses across links, simply matter counting down then signaling read control block. algorithm down counts until frame pulses have arrived then when they present. example (Figure pulses arrive together, then alignment algorithm would count clocks); however, arriving pulses spread over four clocks, then would count first four pulses then clock afterward, which gives total clocks between first frame pulse first read. This puts center arriving frame pulses halfway point buffer. This extent algorithm, facility actively correcting problems once they occur. write control block receives byte-wide data 77.76 frame pulse clocks before first byte STS-12 frame. generates write address FIFO block. first every STS12 stream written same location (address FIFO. Also, frame passed through FIFO along with first byte before first STS12. read control block synchronizes reading FIFO streams that aligned. Reading begins when FIFO sync signals that applicable appropriate margin have been written FIFO. read blocks synchronized begin reading same time same location memory (address alignment algorithm takes difference between read address write address indicate relative clock alignments between STS-12 streams. this depth indication exceeds certain limits clocks), then interrupt given microprocessor (alignment overflow). Each STS-12 stream realigned software gets line (this would cause loss data). background applications that have less than 154.3 interlink skew, misalignment will occur.
STS-12 STREAM STS-12 STREAM FIFO SYNC STS-12 STREAM STS-12 STREAM
5-8577
Figure Interconnect Streams FIFO Alignment incoming data from clock data recovery separated into four STS-12 channels These streams frame aligned patterns shown Figure
STREAM STREAM STREAM STREAM
STREAM STREAM STREAM STREAM
5-8575
Figure Alignment Four STS-12 Streams There also provision allow certain streams disabled (i.e., producing interrupts affecting synchronization). These streams enabled later time without disrupting other streams. FIFO block consists 10-bit FIFO link. This FIFO used align ±154.3 interlink skew transfer system clock. FIFO sync circuit takes metastable hardened frame pulses from write control blocks produces sync signals that indicate when read control blocks should begin reading from first FIFO location. sync signals, this block produces error indicator which indicates that signals aligned apart alignment (i.e., greater than clocks apart). Sync error signals sent read control block
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ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
Backplane Transceiver Core Detailed Description (continued)
CLOCKS LAST ARRIVES ARRIVE TOGETHER (WRITING BEGINS) 24-byte FIFO SYNC. PULSE (READING BEGINS) CLOCKS FIRST ARRIVES (WRITING BEGINS) PERFECTLY ALIGNED FRAMES 4-byte SPREAD ARRIVING FRAMES 24-byte FIFO SYNC. PULSE (READING BEGINS) CLOCKS
5-8584
Figure Examples Link Alignment Pointer Mover Block (Backplane FPGA) pointer mover maps incoming frames line framing that supplied FPGA logic. K1/K2 bytes H1-SS bits also passed through pointer generator that FPGA receive them. pointer mover handles both concatenations inside STS-12, other STS-12s inside core. pointer mover block correctly process length concatenation frames (multiple three) long begins STS-3 boundary (i.e., STS-1 number one, four, seven, ten, etc.) contained within smaller STS-3, details Table Table Valid Starting Positions STS-Mc STS-1 Number STS-3cSPE STS-6cSPE STS-9cSPE STS-12cSPE STS-15cSPE STS-18c STS-48c SPEs
Note: STS-Mc start that STS-1. STS-Mc cannot start that STS-1. depending particular value
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ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
Backplane Transceiver Core Detailed Description (continued)
NORM
Pointer Interpreter State Machine. pointer interpreter's highest priority maintain accurate data flow (i.e., valid only) into elastic store. This will ensure that errors pointer value will corrected standard, fully SONET compliant, pointer interpreter without data hits. This means that error checking increment, decrement, data flag (NDF) (i.e., eight maintained order ensure accurate data flow. single valid pointer (i.e., 0-782) that differs from current pointer will ignored. consecutive incoming valid pointers that differ from current pointer will cause reset location latest pointer value (the generator will then produce NDF). This block designed handle single errors without affecting data flow changing state. pointer interpreter only three states (NORM, AIS, CONC). NORM state will begin whenever consecutive NORM pointers received. consecutive NORM pointers received that both differ from current offset, then current offset will reset last received NORM pointer. When pointer interpreter changes offset, causes pointer generator receive value position. When pointer generator gets unexpected resets offset value location declares NDF. interpreter only looking consecutive pointers that different from current value. These consecutive NORM pointers have have same value. example, current pointer NORM pointer with offset second NORM pointer with offset received, then interpreter will change current pointer receipt consecutive CONC pointers causes CONC state entered. Once this state, offset values from head concatenation chain used determine location each chain. consecutive pointers cause state occur. consecutive normal concatenation pointers will this state. This state will cause data leaving pointer generator overwritten with 0xFF.
CONC CONC
5-8589
Figure Pointer Mover State Machine Pointer Generator. pointer generator maps corresponding bytes into their appropriate location outgoing byte stream. generator also creates offset pointers based location byte indicated pointer interpreter. generator will signal NDFs when interpreter signals that coming state. pointer generator resets pointer value generates every time byte marked read from elastic store that doesn't match previous offset. Increment decrement signals from pointer interpreter latched once frame either byte times (depending collisions); this ensures constant values during through times. choice which byte time latching made once when relative frame phases (i.e., received system) determined. This latch point then stable unless relative framing changes received byte times collide with system times, which case latch point would switched collision-free byte time. There restriction many often increments decrements processed. received increment decrement immediately passed generator implementation regardless when last pointer adjustment made. responsibility meeting SONET criteria maximum frequency pointer adjustments left upstream pointer processor. When interpreter signals state, generator will immediately begin sending 0xFF place data This will continue until interpreter returns NORM CONC (pointer mover state machine) states byte received.
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ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
bytes each channel through four corresponding serial ports. four serial ports synchronized clock (the same clock that being used serial ports transmitter side). This free-running clock provided core external circuitry operates minimum frequency maximum frequency 77.76 MHz. Data transferred over serial links bursty fashion controlled clock enable signal, which generated ASIC common four channels. bytes STS-12 streams transferred over appropriate serial link same order which they appear standard STS-12 frame. Data transfer should preformed row-by-row basis such that internal data buffering needs kept minimum. Data transfers serial links will synchronized relative frame signal. Receiver Reconstruction
Backplane Transceiver Core Detailed Description (continued)
Transport Overhead Extraction Transport overhead extracted from receive data stream extract block. incoming data gets loaded into 36-byte shift register system clock domain. This, turn, clocked onto clock domain start time, where clocked out. During time, receiver frame pulse generated, RX_TOH_FP, which indicates start bytes. This pulse, along with receive clock enable, RX_TOH_CK_EN, well data, launched rising edge clock TOH_CLK. Byte Ordering (Backplane FPGA) processor responsible dropping Table Receiver (Output Parallel Bus)
Receiver reconstruction output parallel shown following table.
Regenerated bytes. Regenerated bytes (under pointer generator control-SS bits must transparent-AIS-P must supported). Bytes taken from Elastic Store Buffer, negative stuff opportunity-else, forced zeros. Transparent zeros (K1/K2 either taken from K1/K2 buffer forced zeros-soft, control). transparent mode, AIS-L must supported. zero bytes.
serial port, bytes dropped received LVDS input (MSB first). only exception most significant byte STS#1, which replaced with even parity bit. This parity calculated over previous frame. Also, AIS-L (either resulting from forced through software), bits forced ones with proper parity (parity automatically ends being AIS-L). Special Byte Functions Handling. bytes used automatic protection switch (APS) applications. bytes optionally passed through pointer mover under software control, zero with other bytes. Handling. discussed previously, bytes used framing header. bytes always regenerated hexadecimal respectively.
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ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
Backplane Transceiver Core Detailed Description (continued)
C1J1 Outputs. These signals each channel passed FPGA logic allow pointer processor other function extract payload without interpreting pointers. ORT4622, each frame STS-1s. region, there pulses each STS-1s. There C1(J0, SONET specifications instead section trace identify each STS-1 STS-N) pulse area frame. Thus, there total pulses C1(J0) pulse frame. C1(J0) pulse coincident with STS1 each frame, flag active when data stream area. behavior dependent pointer movement concatenation. Note that area, also carry valid data. When valid data carried this slot, high this particular time slot. region, there valid data during column, signal will low. allow pointer processor extract payload without interpreting pointers. C1J1 functionality described Table generic data operation, valid data available when C1J1 signal ignored. Table C1J1 Functionality C1J1 Description information excluding C1(J0) STS1 Position C1(J0) STS1 (one frame). Typically used provide unique link identification (256 possible unique links) help ensure cards connected into backplane correctly cables connected correctly. information excluding bytes. Position bytes.
Note: following rules observed generating C1J1 signals: occurrence AIS-P STS-1, there corresponding pulse. case concatenated payloads STS48c), only head STS-1 group associated pulse. C1J1 signal tracks pointer movements. During negative justification event, high during byte indicate that payload data available. During positive justification event, during positive stuff opportunity byte indicate that payload data available.
STS-12
BYTES STS-1S
STS-12
PULSE C1J1 PULSE STS-1
5-9330(F)
Notes: C1J1 signal behavior shown this figure just illustration purposes: pulse position must always shown; however, position pulses vary based path overhead location each STS-1 within STS-12 stream. C1J1 signal must always active during C1(J0) time slot STS#1. C1J1 signal must also active during twelve time slots. However, C1J1 must active STS-1 which AIS-P generated. Also, concatenated payloads, only head group must have pulse.
Figure C1J1 Functionality Lucent Technologies Inc. Lucent Technologies Inc.
ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
Backplane Transceiver Core Detailed Description (continued)
STS-12
NEGATIVE STUFF OPPORTUNITY BYTES
POSITIVE STUFF OPPORTUNITY BYTES
STS-12
SIGNAL SHOWS NEGATIVE STUFFING STS-1, POSITIVE STUFFING STS-1
5-9331
Notes: signal behavior shown this figure just illustration purposes: behavior dependent pointer movements concatenation. signal must high during negative stuff opportunity byte time slots (H3) which valid data carried (negative stuffing). signal must during positive stuff opportunity byte time slots which there valid data (positive stuffing).
Figure Stuff Bytes
Powerdown Mode
Powerdown mode will entered when corresponding channel disabled. Channels independently enabled disabled under software control. Parallel data output enable serial data output enable signals made available FPGA logic. macrocell's corresponding channel also powered down. device will power with four channels powerdown mode. addition, LVDS_EN been added control LVDS pins during boundary scan. During functional operation, enabling/disabling LVDS buffers controlled software registers. When boundary scan mode, LVDS_EN controls enabling/disabling LVDS buffers instead software registers. This LVDS_EN should pulled high board functional operation, pulled during boundary scan.
STS-12 mode, channel receive data port used both channel channel Similarly, channel receive data port used both channel channel Channel channel become redundant channels. channel channel receive data ports unused. Soft registers provide independent control protection switching MUXes both parallel data ports serial data ports. When direct hardware control protection switching needed, external protection switch pins available channels also channels external protection switch pins only support parallel SPE/TOH data protection switching, serial data. STS-48 mode, independent devices required work protect redundancy. Parallel serial port output pins FPGA side should 3-stated basis supporting redundancy. existing local enable signals used 3-state controls FPGA data needed, which easily accessed software control. Users also create their protection switch 3state enable signals either FPGA logic external device, depending specific application.
Redundancy Protection Switching
ORT4622 supports STS-12/STS-48 redundancy either software hardware control protection switching applications. transmitter mode, additional functionality required redundant operation. receiving data, STS-12 data redundancy implemented within same device, while STS-48 above data stream requires pair ORT4622 devices support redundancy. Lucent Technologies Inc. Lucent Technologies Inc.
ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
Memory
Definition Register Types
There structural register elements: sreg, creg, preg, iareg, isreg, iereg. There mixed registers chip. This means that bits particular register (particular address) structurally same. Table Structural Register Elements Element sreg Register Description
creg
preg
iareg
isreg
ereg
Status Register status register read only, and, name implies, used convey status information particular element function ORT4622 core. reset value sreg really reset value particular element function that being read. some cases, sreg really fixed value. example which fixed revision registers. Control Register control register read writable memory element inside core control. value creg will always value written Events inside ORT4622 core cannot effect creg value. only exception soft reset, which case creg will return default value. control register have default values defined default value column Table Pulse Register Each element, bit, pulse register control event signal that asserted then deasserted when value written This means that each always value until written upon which pulsed value then returned value pulse register will always have read value Interrupt Alarm Each interrupt alarm register event latch. When particular event Register produced ORT4622 core, occurrence latched associated iareg bit. clear particular iareg bit, value must written ORT4622 core, isreg reset values Interrupt Status Each interrupt status register physically logical-OR function. Register consolidation lower level interrupt alarms and/or isreg bits from other registers. direct result fact that each isreg logical-OR function means that will have read value consolidation signals value one, will value only consolidation signals value ORT4622 core, isreg default values Interrupt Enable Each status register alarm register associated enable bit. this Register value one, then event allowed propagate next higher level consolidation. this zero, then associated iareg isreg still asserted alarm will propagate next higher level. interrupt enable interrupt mask when value
Registers Access General Description memory comprises three address blocks:
Generic register block: revision, scratch pad, lock, FIFO alignment, reset registers. Device register block: control status bits, common four channels. Channel register blocks: each four channels have address block. four address blocks have exact same structure with constant address offset between channel register blocks.
registers write-protected lock register, except scratch register. lock register 16-bit read/write register. Write access given registers only when value 0xA001 present lock register. error flag will upon detecting write access when write permission denied. default value 0x0000. After powerup reset soft reset, unused register bits will read zeros. Unused address locations also read zeros. Write only register bits will read zeros. detailed information register access function described tables, memory map, memory description. Lucent Technologies Inc. Lucent Technologies Inc.
ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
Memory (continued)
Memory Overview
Table Memory
ADDR [6:0] Reg. Type Default Value Notes (hex)
Generic Register Block
sreg sreg sreg creg creg creg preg fixed [7:0] fixed [7:0] fixed [7:0] scratch [7:0] lockreg [7:0] lockreg [7:0]
FIFO align- global ment comreset mand command LVDS lpbk control
Device Register Block creg
creg
creg creg creg
creg creg creg
scrambler/ input/ descramoutput bler parallel control parity control error insert value [7:0] error insert value [7:0] transmitter error insert mask [7:0]
parallel parallel serial port serial port port out- port outoutput output select select select select FIFO aligner threshold value (min) [4:0] FIFO aligner threshold value (max) [4:0] line loopnumber consecutive A1/A2 errors back generate [3:0] control
frame clock enable control
prot
prot STS-48 STS-12 function (unused ORT4622)
Notes: 1.Generic register block. 2.Device register block-Rx. 3.Device register block-Tx.
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ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
Memory (continued)
Table Memory
ADDR [6:0] Reg. Type Default Value Notes (hex)
Device Register Block (continued) isreg iereg iareg
iereg
device interrupt interrupt interrupt interrupt enable/mask register [4:0] write frame locked offset register error flag error flag enable/mask register [1:0] force ais-l serial control behavior output port
Channel Register Block creg channel parallel K1/K2 ProtecProtec50, tion enable/ output source tion switching switching disable parity select 3-state control 3-state control control data parallel output data output creg mode K1/K2 opera- source source source source tion select select select select creg source source source source source select select select select select creg
source select source select
sreg
sreg
Concatindication Concatin- Concatin- Concatin- Concatin- Concatindication dication dication dication dication
Concatindication Concatindication
source select source select error insert command Concatindication Concatindication
source select source select A1/A2 error command Concatindication Concatindication
Notes: 1.Generic register block. 2.Device register block-Rx. 3.Device register block-Tx. 4.Top-level interrupts. 5.Rx control. 6.Tx control signals. 7.Per STS#1 flag. ADDR values delimited comma indicate address each four channels, from channel example, register control signals addresses This indicates that channel control signals address control control signals address
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ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
Memory (continued)
Table Memory
ADDR [6:0] Reg. Type Default Value Notes (hex)
Channel Register Block (continued) isreg
iereg iareg
elastic ais-p flag store STS-12 overflow alarm flag flag enable/mask register [2:0]
29,41,
iereg iareg
input LVDS link flag Receiver FIFO serial parallel parity internal aligner input port error flag path threshold parity parity parity error flag error flag error flag error flag enable/mask register [5:0] interrupt flag interrupt flag enable/ mask interrupt flag enable/ mask interrupt flag overflow flag interrupt interrupt flag flags interrupt interrupt flag flag enable/ enable/ mask mask interrupt interrupt flag flag enable/ enable/ mask mask interrupt interrupt flag flag overflow overflow flag flag
iareg
iereg
iereg
iareg
interrupt flags interrupt interrupt interrupt interrupt interrupt flag flag flag flag flag enable/ mask interrupt flag enable/ enable/ enable/ enable/ enable/ mask mask mask mask mask interrupt interrupt interrupt interrupt interrupt flag flag flag flag flag overflow flag
Notes: Generic register block. Device register block-Rx. Device register block-Tx. Top-level interrupts. control. control signals. STS#1 flag. channel interrupt. STS-12 interrupt flags. STS-1interrupt flags.
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ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
Memory (continued)
Table Memory
ADDR [6:0] Reg. Type Default Value Notes (hex)
Channel Register Block (continued) iareg overflow overflow overflow flag flag flag iereg
enable/ mask overflow flag counter overflow
counter overflow counter overflow
Notes: Generic register block. Device register block-Rx. Device register block-Tx. Top-level interrupts. control. control signals. STS#1 flag. channel interrupt. STS-12 interrupt flags. STS-1interrupt flags. Binning.
iereg
overflow overflow overflow overflow flag flag flag flag enable/ enable/ enable/ enable/ mask mask mask mask overflow overflow overflow overflow flags flag flags flags enable/ enable/ enable/ enable/ enable/ enable/ enable/ mask mask mask mask mask mask mask overflow overflow overflow overflow overflow overflow overflow flag flag flag flag flag flag flag LVDS link parity error counter counter A1/A2 frame error counter
overflow flag
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ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
Memory (continued)
Table Memory Descriptions
Bit/Register Name(s) Bit/ Default Register Register Value Location Type (hex) (hex)
Description
Generic Register Block
fixed [7:0] fixed [7:0] fixed [7:0] scratch [7:0] lockreg [7:0] lockreg [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] sreg
creg creg
FIFO alignment command global reset command
preg
scratch function used anywhere ORT4622 core. However, this register written read from. order write registers memory locations lockreg lockreg must respectively values lockreg values {A0, 01}, then values written registers memory locations will ignored. After reset (both hard soft), ORT4622 core write locked mode. ORT4622 core needs unlocked before written Also note that scratch register (03) always written since unaffected write lock mode. FIFO alignment global reset commands both accessed pulse register memory address FIFO alignment command used frame align outputs four receive stream FIFOs. global reset command soft (software initiated) reset. Nevertheless, global reset command will have exact reset effect hard (RST_N pin) reset.
Device Register Block
LVDS loopback control STS48 STS12 prot prot func [3:2] creg creg creg loopback. LVDS loopback, transmit receive This control signal untracked ORT4622 core. scratch bit, value effect ORT4622 core. Switching control master. prot prot func controlled software (one control MUX). Output buffer 3-state signals controlled software (one control channel). parallel output channel controlled Prot_Switch (0-> channel channel parallel output channel controlled Prot_Switch channel channel Output buffer 3-state signals controlled software (one control channel). controlled software (one control MUX). Output buffer 3-state signals parallel output channels controlled Prot_Switch (0-> buffers active, hi-z). Output buffer 3-state signals parallel output channels controlled Prot_Switch buffers active, hi-z).
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Memory (continued)
Table Memory Descriptions
Bit/Register Name(s) Bit/ Default Register Register Value Location Type (hex) (hex)
Description
Device Register Block (continued)
frame clock enable serial output port select creg creg toh_ck_fp_en used 3-state rx_toh_ck_en rx_toh_fp signals. Functional Mode. output port multiplexed channel output port multiplexed channel output port multiplexed channel output port multiplexed channel Parallel output data port multiplexed channel Parallel output data port multiplexed channel
Output Select Port
serial output port select
Output Select Port
parallel output port select
Parallel Port Output Select Port
parallel output port select FIFO aligner threshold value (min) [4:0] FIFO aligner threshold value (max) [4:0]
Parallel Port Output Select Port Parallel output data port multiplexed channel Parallel output data port multiplexed channel These minimum maximum thresholds values channel receive direction alignment FIFOs. when minimum maximum threshold value violated particular channel, then interrupt event FIFO aligner threshold error will generated that channel latched FIFO aligner threshold error flag respective STS-12 interrupt alarm register. allowable range minimum threshold values allowable range maximum threshold values Note that minimal maximum FIFO aligner threshold values apply four channels. These three-per-device control signals used conjunction with per-channel A1/A2 error insert command control bits force A1/A2 errors transmit direction. particular channel's A1/A2 error insert command control value one, then error insert values will inserted into that channels respective bytes. number consecutive frames corrupted determined number consecutive errors generate[3:0] control bits. error insertion based rising edge detector. such, control must value before trying initiate second A1/A2 corruption. loopback. Receive transmit loopback FPGA side. Even parity. parity.
[4:0]
creg
[4:0]
number consecutive A1/A2 errors generate [3:0] error insert value [7:0] error insert value [7:0]
[3:0]
creg
[7:0] [7:0]
line loopback control input/output parallel parity control
creg creg
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Memory (continued)
Table Memory Descriptions
Bit/Register Name(s) Bit/ Register Location (hex) Register Type Default Value (hex) Description
Device Register Block (continued)
scrambler/ descrambler control creg receive direction descramble/transmit direction scramble. receive direction, descramble channel after SONET frame recovery. transmit direction scramble data just before parallel-to-serial conversion. error insertion. Invert corresponding byte. Consolidation Interrupts interrupt. Mask interrupt enable/mask register. Interrupt. Enable interrupt enable/mask register.
transmit error insert mask [7:0] channel channel channel channel device enable/mask register [4:0] frame offset error flag write locked register error flag enable/mask register [1:0]
[7:0] [4:0]
creg creg creg creg creg creg iereg iareg iareg
[1:0]
iereg
receive direction phase offset between channels exceeds bytes, then frame offset error event will issued. This condition continuously monitored. ORT4622 core memory been unlocked writing lock registers), address other than lockreg registers scratch register written then write locked register event will generated.
Channel Register Block (Channel Channel Channel Channel
behavior Receive Behavior Force AIS-L control When receive direction occurs, insert AIS-L. When receive direction occurs, insert AIS-L. force AIS-L. Force AIS-L. insert parity error. Insert parity error parity receive serial output long this set. receive direction K1/K2 bytes Pass receive direction K1/K2 though pointer mover. insert parity error. Insert parity error parity receive direction parallel output long this set.
Force AIS-L Control
serial output port K1/K2 source select parallel output parity
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Memory (continued)
Table Memory Descriptions
Bit/Register Name(s) Bit/ Register Location (hex) Register Type Default Value (hex) Description
Channel Register Block (Channel Channel Channel Channel (continued)
channel enable/disable control creg Channel Enable/Disable Control Powerdown channel A/B/C/D LVDS used with data_rx_en 3-state output buses. Functional mode. used 3-state control protection switching FPGA data output. used 3-state control data output. Only channel enable signal brought out. Transmit Mode Operation Insert from serial ports. Pass through TOH. Other Registers Insert from serial ports. Pass through that particular byte.
Hi-z control parallel output bus.
creg
Hi-z control data output.
creg
mode operation
creg
source select source select source select D12-D9 source select D8-D1 source select A1/A2 error insert command
[3:0] [7:0]
creg creg creg creg creg creg
error insert command
creg
concatindication concatindication
[3:0] [7:0]
sreg sreg
STS-12 alarm flag AIS-P flag elastic store overflow flag enable/mask register [2:0] FIFO aligner threshold error flag receiver internal path parity error flag flag LVDS link parity error flag input parallel parity error flag serial input port parity error flag enable/mask register [5:0] interrupt flags interrupt flags enable/mask register enable/mask register
[2:0] [5:0] [3:0] [7:0] [3:0] [7:0]
isreg isreg isreg iereg iareg iareg iareg iareg iareg iareg iareg iareg iareg iereg iereg
insert error.* Insert error number frames register 0C.* insert error. Insert error frame bits defined register value location indi0 cates that STS# CONCAT mode. indicates that CONCAT mode, head concat group. These flag register bits STS-12 alarm flag, AIS-P flag, elastic store overflow flag per-channel inter3'b000 rupt status (consolidation) register. These STS-12 alarm flags with corresponding enable/mask register. 6'h00 4'h0 These AIS-P alarm flags with 8'h00 corresponding enable/mask 4'h0 register. 8'h00
4'h0 8'h00
error insertion based rising edge detector. such, control must value before trying initiate second A1/A2 corruption. error insertion based rising edge detector. such, control must value before trying initiate second corruption.
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Memory (continued)
Table Memory Descriptions
Bit/Register Name(s) Bit/ Register Location (hex) Register Type Default Value (hex) Description
Channel Register Block (Channel Channel Channel Channel (continued)
overflow flags overflow flags enable/mask register enable/mask register LVDS link parity error counter counter A1/A2 frame error counter [7:0] [3:0] [7:0] [7:0] [7:0] [7:0] [7:0] 4'h0 8'h00 4'h0 8'h00 8'h00 8'h00 8'h00 These elastic store overflow alarm flags.
counter counter counter
7-bit count overflow-reset read. 7-bit count overflow-reset read. 7-bit count overflow-reset read.
error insertion based rising edge detector. such, control must value before trying initiate second A1/A2 corruption. error insertion based rising edge detector. such, control must value before trying initiate second corruption.
Powerup Sequencing ORT4622 Device
ORCA Series ORT4622 device uses power supplies: power device I/Os ASIC core (VDD), which operation tolerance input pins, another supply internal FPGA logic (VDD2), which understood that many users will derive core logic supply from power supply, following recommendations made powerup sequence supplies allowable delays between power supplies reaching stable voltages. general, both supplies should ramp-up become stable close together time possible. There delay requirement VDD2 (2.5 supply becomes stable prior (3.3 supply. There delay requirement imposed supply becomes stable prior VDD2 supply. requirement that VDD2 (2.5 supply transition from within 15.7 (3.3 supply already stable minimum supply reached when VDD2 supply reached then requirement that VDD2 supply reach minimum within 15.7 when supply reaches chosen power supplies cannot meet this delay requirement, always possible hold configuration FPGA asserting INIT PRGM until VDD2 supply reached This process eliminates power supply sequencing issues.
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FPGA Configuration Data Format
ORCA Foundry development system interfaces with front-end design entry tools provides tools produce fully configured FPSC. This section discusses using ORCA Foundry development system generate configuration data then provides details configuration frame format.
FPGA Configuration Data Frame
Configuration data presented FPSC frame formats: autoincrement explicit. detailed description frame formats shown Figure Figure Table modes similar except that autoincrement mode uses assumed address incrementation reduce stream size, explicit mode requires address each data frame. both cases, header frame begins with series preamble 0010, followed 24-bit length count field representing total number configuration clocks needed complete loading FPSC. mandatory frame contains data used determine stream being loaded correct type ORCA device (i.e., stream generated ORT4622 being sent ORT4622). Error checking always enabled Series devices, through 8-bit checksum. frame also selects between autoincrement explicit address modes this load configuration data. configuration data frame follows frame. data frame starts with one-start pair ends with enough one-stop bits reach byte boundary. using autoincrement configuration mode, subsequent data frames follow. using explicit mode, more address frames must follow each data frame, telling FPSC what addresses preceding data frame stored (each data frame sent multiple addresses). Following data address frames postamble. format postamble same address frame with highest possible address value with checksum ones.
Using ORCA Foundry Generate Configuration Data
configuration data stream defines embedded core configuration, FPGA logic functionality, configuration interconnection. data stream generated ORCA Foundry development tools. stream created stream generation tool series used write FPSC configuration RAM. loaded into FPSC using configuration modes discussed elsewhere this data sheet. FPSCs, stream prepared separate steps design flow. configuration options embedded core specified using ORCA ORT4622 Design Software beginning design process. This offers designer specific configuration simulate design FPGA logic Upon completion design, stream generator combines embedded core options FPGA configuration into single stream download into FPSC.
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FPGA Configuration Data Format (continued)
CONFIGURATION DATA CONFIGURATION DATA
PREAMBLE LENGTH COUNT
FRAME
CONFIGURATION DATA FRAME
CONFIGURATION DATA FRAME
POSTAMBLE 5-5759(F)
CONFIGURATION HEADER
Figure Serial Configuration Data Format-Autoincrement Mode
CONFIGURATION DATA
CONFIGURATION DATA
PREAMBLE LENGTH COUNT
FRAME
CONFIGURATION DATA FRAME
ADDRESS FRAME
CONFIGURATION DATA FRAME
ADDRESS FRAME
POSTAMBLE 5-5760(F)
CONFIGURATION HEADER
Figure Serial Configuration Data Format-Explicit Mode Table Configuration Frame Format Contents Header 11110010 24-bit Length Count 11111111 0101 1111 1111 1111 Configuration Mode Reserved [41:0] Checksum 11111111 Data Bits Alignment Bits Checksum 11111111 Address Bits Checksum 11111111 11111111 111111 1111111111111111 Preamble. Configuration frame length. Trailing header-8 bits. frame header. autoincrement, explicit. Reserved bits 20-bit part 8-bit checksum. Eight stop bits (high) separate frames. Data frame header. Number data bits depends upon device. String bits added stream make frame header, plus data bits reach byte boundary. 8-bit checksum. Eight stop bits (high) separate frames. Address frame header. 14-bit address location start data storage. 8-bit checksum. Eight stop bits (high) separate frames. Postamble header. Dummy address. stop bits.
Frame
Configuration Data Frame (repeated each data frame) Configuration Address Frame
Postamble
Note: slave parallel mode, byte containing preamble must 11110010. number leading header dummy bits must where nonnegative integer number trailing dummy bits must where positive integer. number stop bits/frame slave parallel mode must where positive integer. Note also that stream generator tool supplies stream that compatible with configuration modes, including slave parallel mode.
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FPGA Configuration Data Format
(continued)
FPGA Configuration Modes
There eight methods configuring FPSC. configuration modes selected input shown Table fourth input, used select frequency internal oscillator, which source CCLK some configuration modes. nominal frequencies internal oscillator 1.25 MHz. 1.25 frequency selected when input unconnected driven high state. Note that Master parallel mode configuration that available ORCA Series FPGAs available ORT4622. More information general FPGA modes configuration found ORCA Series data sheet. Table Configuration Modes CCLK Output Input Output Configuration Mode Master Serial Slave Parallel Microprocessor: Motorola* PowerPC Microprocessor: Intel i960 Reserved Async Peripheral Reserved Slave Serial Data Serial Parallel Parallel
Stream Error Checking
There three different types stream error checking performed ORCA Series FPSCs: frame, frame alignment, checking. data frame sent dedicated location FPSC. This frame contains unique code device which generated. This device code compared internal code FPSC. differences flagged error. This frame automatically created stream generation program ORCA Foundry. Each data address frame FPSC begins with frame start pair bits ends with eight stop bits previous stop bits were when frame start pair encountered, flagged frame alignment error. Error checking also done FPSC each frame means checksum byte. error found evaluation checksum byte, then checksum/parity error flagged. When three possible errors occur, FPSC forced into idle state, forcing INIT low. FPSC will remain this state until either RESET PRGM pins asserted. using either modes configure FPSC, specific type stream error written registers FPGA configuration logic. PGRM control register also used reset error condition restart configuration.
Output
Parallel
Output Input
Parallel Serial
Motorola registered trademark Motorola, Inc. Intel registered trademark Intel Corporation.
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Absolute Maximum Ratings
Stresses excess absolute maximum ratings cause permanent damage device. These absolute stress ratings only. Functional operation device implied these other conditions excess those given operations sections this data sheet. Exposure absolute maximum ratings extended periods adversely affect device reliability. ORCA Series FPSCs include circuitry designed protect chips from damaging substrate injection currents prevent accumulations static charge. Nevertheless, conventional precautions should observed during storage, handling, avoid exposure excessive electrical stress. Table Absolute Maximum Ratings Parameter Storage Temperature Supply Voltage with Respect Ground Internal Supply Voltage Input Signal with Respect Ground CMOS Tolerant Signal Applied High-impedance Output Maximum Package Body Temperature Junction Temperature Symbol Tstg VDD2 -0.5 -0.5 -0.5 Unit
Recommend Operating Conditions
Table Recommend Operating Conditions ORT4622 Temperature Range (Ambient) Supply Voltage (VDD) Internal Supply Voltage (VDD2)
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Electrical Characteristics
Table General Electrical Characteristics ORT4622 Commercial: VDD2 Symbol IDDSB Parameter Standby Current Test Conditions ORT4622 Unit
IDDSB
VDD2 internal oscillator running, output loads, inputs (after configuration) Standby Current VDD2 internal oscillator stopped, output loads, inputs (after configuration) Data Retention Voltage Powerup Current Power supply current approximately within recommended power supply ramp rate ms-200
Table Electrical Characteristics FPGA ORT4622 Commercial: VDD2 Parameter Input Voltage: High Input Voltage: High Output Voltage: High Input Leakage Current Input Capacitance Output Capacitance Symbol Test Conditions Input configured CMOS (clamped VDD) Input configured tolerant COUT min, min, max, VDD2 test frequency VDD2 test frequency (VDD VSS, (VDD VSS, all, VSS, all, VDD, 14.4 50.9 ORT4622 Unit
DONE Pull-up Resistor* RDONE M[3:0] Pull-up Resistors* Static Pull-up Current* Static Pull-down Current Pull-up Resistor* Pull-down Resistor
pull-up resistor will externally pull level below VDD.
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(continued)
Electrical Characteristics
Table Electrical Characteristics Embedded Core Other than LVDS Symbol Parameter Input High Voltage (TTL input) Input Voltages (TTL input) Output High Voltage (TTL output) Output Voltage (TTL output) Unit
Note: outputs driving except data pins which drive assumed that buffers from standard-cell library handle load.
Circuit Specifications
Input Data
Mbits/s scrambled input data stream must conform SONET STS-12 STM-4 data format using either sequence. characteristic characteristic ORT4622 supplies default scrambler using sequence. longest allowable stream nontransitional Mbits/s input data bits. This sequence should occur more often than once minute. input signal phase change more than allowed over time interval, which translates frequency change ppm. signal opening must greater than UIp-p (unit interval peak-to-peak), unit interval Mbits/s 1.6075
requires external pull-down resistor. Table Parameter Loop Bandwidth Jitter Peaking Powerup Reset Duration Lock Acquisition Unit
Input Reference Clock
Table Input Reference Clock Parameter Frequency Deviation Frequency Change Phase Change
Jitter Tolerance
input jitter tolerance ORT4622 shown Table Table Jitter Tolerance Frequency UIp-p
Generated Output Jitter
generated output jitter maximum UIp-p from MHz.
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Circuit Specifications
(continued)
Power Supply Decoupling Circuit
macro contains both analog digital circuitry. data recovery function, example, implemented primarily digital function, relies conventional analog phase-locked loop provide reference frequency. internal analog phase-locked loop contains voltage-controlled oscillator. This circuit will sensitive digital noise generated from rapid switching transients associated with internal logic gates parasitic inductive elements. Generated noise that contains frequency components beyond bandwidth internal phase-locked loop (about MHz) will attenuated phase-locked loop will impact error rate directly. Thus, separate power supply pins provided these critical analog circuit elements. Additional power supply filtering form filter section will used between power supply source these device pins shown Figure corner frequency filter chosen based power supply switching frequency, which between most applications. Capacitors large electrolytic capacitors provide basic cutoff frequency filter. example, cutoff frequency combination these elements might fall between kHz. Capacitor smaller ceramic capacitor designed provide low-impedance path wide range high-frequency signals analog power supply pins device. physical location capacitor must close device lead possible. Multiple instances capacitors used necessary. recommended filter macro shown below: 0.01 0.01
FROM POWER SUPPLY SOURCE
DEVICE PLL_VDDA
PLL_VSSA
5-9344(F)
Figure Sample Power Supply Filter Network Analog Power Supply Pins
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LVDS
Table LVDS Driver Data* Parameter Driver Output Voltage High, Driver Output Voltage Low, Driver Output Differential Voltage (VOA VOB) (with External Reference Resistor) Driver Output Offset Voltage (VOA VOB)/2 Output Impedance, Single Ended Mismatch Between Change |VOD| Between Change |VOS| Between Output Current Output Current Power-off Output Leakage Symbol Test Conditions RLOAD RLOAD RLOAD 0.925* 0.25 1.475* 0.45* Unit
delta ISA, ISAB |xa|, |xb|
RLOAD RLOAD RLOAD Driver shorted ground Drivers shorted together VPAD, VPADN
1.125*
1.275*
External reference, REF10 REF14
Table LVDS Driver Data Parameter Fall Time, Rise Time, Differential Skew |tpHLA tpLHB| |tpHLB tpLHA| Channel-to-channel Skew |tpDIFFm tpDIFFn|, Propagation Delay Time Symbol TFALL TRISE TSKEW1 Test Conditions ZLOAD CPAD CPAD ZLOAD CPAD CPAD differential pair package point transition signals package differential ZLOAD CPAD CPADN Unit
TSKEW2 TPLH TPHL
0.50 0.55
0.90 1.03
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LVDS (continued)
LVDS Receiver Buffer Requirements
Table LVDS Receiver Data Parameter Receiver Input Voltage Range, Receiver Input Differential Threshold Receiver Input Differential Hysteresis Receiver Differential Input Impedance Symbol |VIDTH| HYST Test Conditions |VGPD| mVdc |VGPD| VIDTHH VIDTHL With built-in termination, center-tapped -100 Unit
Buffer will produce output transition when input open-circuited. Note: V-3.5 -125 slow-fast process.
Table LVDS Receiver Data Symbol TPWD TPLH, TPHL TRISE TFALL Parameter Receiver Output Pulse-width Distortion Propagation Delay Time With Common-mode Variation, Receiver Output Signal Rise Time, Receiver Output Signal Fall Time, Test Conditions |VIDTH| 0.75 0.74 1.65 1.82 Unit
Table LVDS Receiver Power Consumption Symbol PRdc PRac Parameter Receiver Power Receiver Power Test Conditions 34.8 0.026 Unit mW/MHz
Table LVDS Operating Parameters Parameter Transmit Termination Resistor Receiver Termination Resistor Temperature Range Power Supply Power Supply Test Conditions Normal Unit
Note: Under worst-case operating condition, LVDS driver will withstand disabled unpowered receiver unlimited period time without being damaged. Similarly, when outputs short-circuited each other ground, LVDS will suffer permanent damage. LVDS driver supports hot-insertion. Under well-controlled environment, LVDS drive backplane well cable.
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Table Derating Commercial Devices (I/O Supply VDD) (°C) Power Supply Voltage 0.82 0.91 0.98 1.00 1.23 1.34 0.72 0.80 0.85 0.99 1.07 1.15 0.66 0.72 0.77 0.90 0.94 1.01
Timing Characteristics
Description
most accurate timing characteristics reported timing analyzer ORCA Foundry development system. timing report provided development system after layout divides path delays into logic routing delays. timing analyzer also provide logic delays prior layout. While this allows routing budget estimates, there wide variance routing delays associated with different layouts. logic timing parameters noted Electrical Characteristics section this data sheet same those design tools. timing, symbol names generally concatenation operating mode parameter type. setup, hold, propagation delay parameters, defined below, designated symbol name SET, HLD, characters, respectively. values given parameters same those used during production testing speed binning devices. junction temperature supply voltage used characterize devices listed delay tables. Actual delays nominal temperature voltage best-case processes much better than values given. should noted that junction temperature used tables generally junction temperature FPGA depends power dissipated device, package thermal characteristics (JA), ambient temperature, calculated following equation discussed further Package Thermal Characteristics Summary section: TJmax TAmax Note: user must determine this junction temperature delays from ORCA Foundry should derated based following derating tables. Table Table provide approximate power supply junction temperature derating OR3LP26B commercial devices. delay values this data sheet reported ORCA Foundry shown 1.00 tables. method determining maximum junction temperature defined Package Thermal Characteristics section. Taken cumulatively, range parameter values best-case worst-case processing, supply voltage, junction temperature approach three one.
Table Derating Commercial Devices (I/O Supply VDD2) (°C) Power Supply Voltage 2.38 0.86 0.94 0.99 1.00 1.23 1.33 0.71 0.79 0.84 0.99 1.05 1.13 2.63 0.67 0.73 0.77 0.92 0.96 1.03
Note: derating tables shown above typical critical path that contains logic delay routing delay. Since routing delay derates higher rate than logic delay, paths with more than routing delay will derate higher rate than shown table. approximate derating values temperature 0.26% logic delay 0.45% routing delay. approximate derating values voltage 0.13% both logic routing delays
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Timing Characteristics (continued)
Propagation Delay-The time between specified reference points. delays provided worstcase tphh tpll delays noninverting functions, tplh tphl inverting functions, tphz tplz 3-state enable. Setup Time-The interval immediately preceding transition clock latch enable signal, during which data must stable ensure recognized intended value. Hold Time-The interval immediately following transition clock latch enable signal, during which data must held stable ensure recognized intended value. 3-State Enable-The time from when 3-state control signal becomes active output reaches high-impedance state.
Timing
Refer ORCA Series data sheet following: Programmable (PIO) Timing Characteristics
Special Function Timing
Refer ORCA Series data sheet following: Microprocessor Interface (MPI) Timing Characteristics Programmable Clock Manager (PCM) Timing Characteristics Boundary-Scan Timing Characteristics
Clock Timing
Refer ORCA Series data sheet following:
ExpressCLK (ECLK) Fast Clock (FCLK) Timing Characteristics
Timing
Refer ORCA Series data sheet following: Combination Timing Characteristics Sequential Timing Characteristics Ripple Mode Timing Characteristics Synchronous Memory Write Characteristics Synchronous Memory Read Characteristics
General-Purpose Clock Timing Characteristics (Internally Generated Clock) ORT4622 ExpressCLK Output Delay (Pin-to-Pin) ORT4622 Fast Clock (FCLK) Output Delay (Pin-toPin) ORT4622 General System Clock (SCLK) Output Delay (Pin-to-Pin) ORT4622 Input ExpressCLK (ECLK) Fast Capture Setup/Hold Time (Pin-to-Pin) ORT4622 Input Fast Clock Setup/Hold Time (Pin-toPin) ORT4622 Input General System Clock Setup/Hold Time (Pin-to-Pin)
Timing
Refer ORCA Series data sheet following: Output Direct Routing Timing Characteristics
Configuration Timing
Refer ORCA Series data sheet Configuration Timing Characteristics.
SLIC Timing
Refer ORCA Series data sheet following: Supplemental Logic Interconnect Cell (SLIC) Timing Characteristics
Readback Timing
Refer ORCA Series data sheet Readback Timing Characteristics.
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Timing Characteristics (continued)
Table ORT4622 Embedded Core FPGA Interface Clock Operation Frequencies ORT4622 Commercial: VDD2 Description min, VDD2 min) Signal sys_clk toh_clk
sys_clk clock frequency based macro specifications.
Speed 77.76* 77.76
Unit
embedded core/FPGA on-chip interface timing available ORCA Foundry through STAMP timing file included ORT4622 Design Kit.
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Timing Characteristics (continued)
Clock Timing
FPGA_SYSCLK SYS_FP
DATA_TX (DATA FROM FPGA EMBEDDED CORE)
FIRST STS1
5-8605
Figure Transmit Parallel Port Timing (Backplane FPGA) Table Timing Requirements (Transmit Parallel Port Timing) Symbol Parameter Clock Period Clock Time Clock High Time 12.86 6.43 6.43 Unit
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ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
Timing Characteristics (continued)
TPROP SYS_CLK
SYS_FP
DATA_TX (PARALLEL DATA FROM FPGA EMBEDDED CORE) HDOUT (LVDS DATA OUT)
STS1
FIRST STS1
5-8606
Figure Transmit Transport Delay (FPGA Backplane) Table Timing Requirements (Transmit Transport Delay) Symbol TPROP Parameter Number Clocks Delay from Parallel Input LVDS Output Unit SYS_CLK
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Timing Characteristics (continued)
SYS_CLK LINE_FP
DATA_RX (FROM EMBEDDED CORE FPGA) PARITY, SPE, C1J1 PINS
FIRST STS1
5-8607
Figure Receive Parallel Port Timing (Backplane FPGA) Table Timing Requirements (Receive Parallel Port Timing) Symbol Parameter Clock Period Clock Time Clock High Time 12.86 6.43 6.43 Unit
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ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
Timing Characteristics (continued)
SYS_CLK
PROT_SW_A PROT_SW_C
DATA_RX BUS*
THIZ
SYS_CLK
DATA_RX
5-8608
Data refers bits data, parity, SPE, C1J1. Channel refers whether PROT_SW_A PROT_SW_C pins that activated. example, PROT_SW_A activated, timing diagram output refers output
Figure Protection Switch Timing Table Timing Requirements (Protection Switch Timing) Symbol THIZ Parameter Transport Delay from Latching PROT_SW_A/C Actual Data Switch Transport Delay from Latching PROT_SW_A/C Actual Hi-z Propagation Delay from SYS_CLK HI-Z Output Unit Leading edge SYS_CLKs Leading edge SYS_CLKs Leading edge SYS_CLKs
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ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
Timing Characteristics (continued)
SYS_CLK
SYS_FP
DATA_TX (PARALLEL BUS)
bytes GUARD BAND CLK)
1044 bytes
GUARD BAND CLK)
1044 bytes
bytes
TOH_CLK
TOH_ CLK_ENA
SERIAL INPUT
MSbit(7) byte STS1
byte STS1 5-8609
Figure Input Serial Port Timing (FPGA Backplane) Table Timing Requirements (TOH Input Serial Port Timing) Symbol Parameter Clock Period Clock High Time Clock Time 12.86 6.43 6.43 Unit
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ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
Timing Characteristics (continued)
HDIN (INPUT LVDS SERIAL 622M DATA)
bytes
1044 bytes TTRANS_SYS
1044 bytes
bytes
TTRANS_TOH
TOH_CLK
SERIAL OUTPUT
MSbit(7) byte
byte
byte
5-8610
Note: total delay from STS1 arriving LVDS input RX_TOH_FP SYS_CLKs TOH_CLKs. This will vary SYS_CLKs, each FIFO alignment, SYS_CLKs variability clock recovery macro.
Figure Output Serial Port Timing (Backplane FPGA) Table Timing Requirements (TOH Output Serial Port Timing) Symbol Parameter Unit SYS_CLKs TOH_CLKs
TTRANS_SYS Delay from First LVDS Serial Input Transfer TOH_CLK TTRANS_TOH Delay from Transfer TOH_CLK RX_TOH_FP
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Timing Characteristics (continued)
TACCESS_MIN TPULSE CPU_CS_N (CS_N) TRD_WR_N, ADDR_MAX, DB_HOLD CPU_RD_WR_N (RD_WR_N) CPU_ADDR[6:0] (ADDR[6:0]) CPU_DATA[7:0] (DB[7:0]) INTERNAL REGISTER (SYS_CLK DOMAIN) TADDR_MAX TDAT_MAX RD_WR_MAX TWRITE_MAX CPU_INT_N (INT_N)
DATA VALID
VALUE
VALUE
TINT_MAX
5-8611
Note: interface stream selected either from device FPGA interface. timing diagram applies both interfaces, FPGA block.
Figure Write Transaction Table Timing Requirements (CPU Write Transaction) Symbol TPULSE TADDR_MAX TDAT_MAX TRD_WR_MAX TWRITE_MAX TACCESS_MIN Parameter Minimum Pulse Width CS_N Maximum Time from Negative Edge CS_N ADDR Valid Maximum Time from Negative Edge CS_N Data Valid Maximum Time from Negative Edge CS_N Negative Edge RD_WR_N Maximum Time from Negative Edge CS_N Contents Internal Register Latching DB[7:0] Minimum Time Between Write Cycle (falling edge CS_N) Other Transaction (read write falling edge CS_N) Maximum Time from Register Minimum Hold Time that RD_WR_N, ADDR Must Held Valid from Negative Edge CS_N Unit
TINT_MAX TRW_WR_N,
ADDR, DB_HOLD
Lucent Technologies Inc. Lucent Technologies Inc.
ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
Timing Characteristics (continued)
TACCESS_MIN TPULSE CPU_CS_N (CS_N) CPU_RD_WR_N (RD_WR_N) CPU_ADDR[6:0] (ADDR[6:0]) THIZ_MAX CPU_DATA[7:0] (DB[7:0]) DATA VALID
TADDR_MAX TRD_WR_MAX TDATA_MAX
5-8612
Notes: interface stream selected either from device FPGA interface. timing diagram applies both interfaces, FPGA block. time delay between advanced SYS_CLK distributed SYS_CLK used sample CS_N consequence. However, path delay CS_N from where sampled SYS_CLK must minimized. calculated delays assume loading pins.
Figure Read Transaction Table Timing Requirements (CPU Read Transaction) Symbol TPULSE TADDR_MAX TRD_WR_MAX TDATA_MAX THIZ_MAX TACCESS_MIN Parameter Minimum Pulse Width CS_N Maximum Time from Negative Edge CS_N ADDR Valid Maximum Time from Negative Edge CS_N RD_WR_N Falling Maximum Time from Negative Edge CS_N Data Valid Port Maximum Time from Rising Edge CS_N Port Going HI-Z Minimum Time Between Read Cycle (falling edge CS_N) Other Transaction (read write falling edge CS_N) Unit
Lucent Technologies Inc. Lucent Technologies Inc.
ORCA ORT4622 FPSC Four-Channel Mbits/s Backplane Transceiver
Input/Output Buffer Measurement Conditions (on-LVDS Buffer)
OUTPUT UNDER TEST OUTPUT UNDER TEST
Load Used Measure Propagation Delay
Load Used Measure Rising/Falling Edges
5-3234(F)
Note: Switch TPLZ/TPZL; switch TPHZ/TPZH.
Figure Test Loads
ts[i]
out[i]
TEST LOADS (SHOWN ABOVE)
out[i] VDD/2 TPLL TPHH
5-3233.a(F)
Figure Output Buffer Delays
in[i]
in[i] VDD/2 TPLL TPHH<
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