APPLICATION NOTE #108 CT2577 SmaRT Series Users Guide Point
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CIRCUIT TECHNOLOGY
APPLICATION NOTE #108
CT2577 SmaRT Series Users Guide
Point Contact: John Vanchieri Tel: (516) 752-2484
APPLICATION NOTE #108
Released 9/98
Table Contents
Contents
MIL-STD-1553 Interface Signals Hard Wired Interface Signals MIL-STD-1760 Signals Interface Signals Status Word Discrete Inputs Discrete Signals Discrete Signals
Page
Signal Descriptions.3-7
Remote Terminal (RT) Mode.8-21
Sequence Operation Receive Command Message Illegalization MIL-STD-1760 Features 1760 Header Word Signals that Indicate Checksum Failure Block Transfer Logic READ (Receive) Transfer Times Transmit Command MIL-STD-1760 Features Signals that Indicate Checksum Failure Block Transfer Logic Transfer Times WRITE Changing Status Word Bits Device Status Register Data Storage Retrieval Sample Software Code Retriving Loading Data Self Test Basic Operation Detailed Operation Summary Operation
CT2577/79 RT/BT Memory Breakdown RT/BT Device Memory Code Breakdown Description.23-29
Status Word Control Sets Control Area RT/RX BC/TX Mode Area Control Receive Transmit Subaddresses 01-1E (1-30) RT/RX BC/TX Mode Area (31) RT/BC Control Area RT/BC Block Transfer Logic (BTL) Control Self Test Control RT/TX BC/RX Mode Area Transmit Receive Subaddresses 01-1E (1-30) RT/TX BC/RX Mode Area (31) Broadcast RT/RX BC/TX Mode Area Broadcast Receive Transmit Subaddresses 01-1E (1-30) Broadcast RT/RX BC/TX Mode Area (31)
CT2577/79 Part Ordering Information .30-34
CT2577 MIL-STD-1553 1760 Controller Remote Terminal CT2579 McAir Controller Remote Terminal
CT2577/79 Pinouts.35-41
CT2577-01-xx-F84 Quad Flatpack CT2577-11-xx-F84 Quad Flatpack CT2579-01-xx-F84 Quad Flatpack CT2579-11-xx-F84 Quad Flatpack CT2577-10-xx-P119 Grid Array CT2579-10-xx-P119 Grid Array
APPLICATION NOTE #108
Released 9/98
Signal Descriptions
MIL-STD-1553 Interface Signals
Data0(Bus) Connect positive side external databus transformer Ndata0(Bus) Connect negative side external databus transformer Data1(Bus) Connect positive side external databus transformer Ndata1(Bus) Connect negative side external databus transformer
Hard Wired Interface Signals
AddrA-E Remote Terminal address inputs unit. ADDR least significant ADDR most significant bit. Address inputs unit. AddrA LSB, AddrE MSB. Parity Address inputs. AddrP must parity This signal sets unit respond with status word within (dead time) while Remote Terminal mode. Subaddress also enabled valid subaddress data. Normally subaddress reserved mode codes. dead response time, subaddress used data. response time, subaddress used mode codes. Select subsystem data interface. mode only lower bits databus (DATA 0-7) used data transfers. left open circuit device will default mode. Mode Mode Select MULTIBUS subsystem interface. left open circuit device will default mode. Multibus Mode Mode Select Remote Terminal wrap around subaddress this test work correctly theunit must mode. Controller sends data subaddress which remains data buffer memory available sent back very next command Controller. data data buffer memory this mode does transferred main RAM. very next command transmit command subaddress data buffer memory flushed will respond normally next commands. wrap around test enabled, data subaddress must transferred correct sequence. Normal Mode Wrap Around Mode
AddrP MACAIR
NBIT16
*WRAPEN
MIL-STD-1760 Signals
NENCHK Enables Disables internal hardware checksum generation validation both Remote Terminal Controller. When enabled, circuitry will check
APPLICATION NOTE #108
Released 9/98
incoming data correct checksum generate correct checksum word outgoing data transfer. input this ENABLES checksum circuitry. input this Disables checksum circuitry. NVALCHK Latched version STATUS signal. NVALCHK latched falling edge NCMDSTRB (RT) NSTSTRB (BC) will remain stable until next NCMDSTRB NSTSTRB. output this means checksum VALID. output this means checksum VALID. Open drain output will toggle high each incoming data word from 1553 databus provided NENCHK enabled. When last data word received STATUS line sampled protocol circuitry determine checksum message valid. message, STATUS then checksum valid. This STATUS signal wired several different pins customise units response achecksum failure. STATUS wired signals such NILLCMD which would cause message illegalised Service Request Status. MIL-STD-1760, first data word message defined Header word. NHDR signal indicates presence Header word T0-T15 highway received. user also read Header word from RAM. this means Header Word T0-15 When store released from aircraft Remote Terminal address inputs high causing signal STREL high Enables Latched Address Option. Normally, address lines constantly monitored compared incoming Command Word. When enabled, address lines levels internally latched every time unit reset. latched address information then compared incoming Command Word. This latched address function complies with requirements MIL-STD-1760. this means address lines latched this means address lines latched
STATUS
NHDR
STREL
Interface Signals
ADIN0-11 address input unit specifying what location user will accessing registers. These address inputs inverted when Multibus interface selected. Indicates what mode unit Mode Mode Used Device Select. Signal indicate processor addressing this unit. user this signal tied address decoder enable unit read/write operation. Enable unit operations DISABLE unit operations clock system clock.
BCNRT
NCARDEN
C16Mhz
APPLICATION NOTE #108
Released 9/98
DATA0-15
bidirectional data highway access internal registers. When mode only DATA used. Data inputs outputs inverted when Multibus interface selected. After write read cycle begun, this signal indicates that write read operation unit been acknowledged that access been granted. Read data available write data complete. user complete write read cycle. Cycle acknowledged, access granted. acknowledge, wait. Empty flag Command Status FIFO memory which store command words (RT) status words (BC). mode memory will store command words that have accessed main RAM. This includes standard commands receive transmit data from main mode codes with data that require subsystem involvement Synchronize With Data Transmit Vector Word. mode status responses stored this memory. Access this memory gained reading from address output this means FIFO empty words). output this means FIFO empty (has words read). Full flag Command Status FIFO memory. When signal goes memoryis full will store more data. Bidirectional reset pin. Interface this should form open collector pull down driver. unit will reset when level input asserted power bidirectional that unit will drive signal after status response mode code Reset Remote Terminal. Upon reset unit will initialise mode will able respond immediately after rising edge NRES. bidirectional data highway access internal registers. When mode only DATA used. Data inputs outputs inverted when Multibus interface selected. Allows user have access MIL-STD-1553 traffic real time. user utilize this message illegalization read words such Synch w/Data directly T0-15 bus. Utilizing NDATA signal, user read data words T0-15 burst transferring data into RAM. Upper byte: When unit mode this signal used address lines. mode signal used address lines ADIN Mode Data Strobe data transfer Read/Write data Tri-state Data 0-15
NACK
NEMPTY
NFULL NRES
T0-15
Multibus Mode:Read strobe data transfer Read data FROM unit Subsystem Tri-state Data0-15 Mode Read/Write direction flag data strobe Write data FROM Subsystem Device Read data FROM Device unit Subsystem
APPLICATION NOTE #108
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Multibus Mode:Write strobe data transfer Write data FROM Subsystem Device Tri-state Data0-15
Status Word Discrete Inputs
following signals inputs appropriate bits Status word. inputs sampled after NVCR signal. These Status Word inputs should latched NVCR remain stable until next NVCR signal. inputs listed below active low. appropriate bits, user must pull that input "low" ("0") Message Error, illegalizes message. Command will stored Command Status memory transfers from main will take place. data will transmitted following status. Sets Terminal Flag Sets Service Request Sets Subsystem Busy Sets Subsystem Flag Sets Dynamic Control Accept response Mode Code "Dynamic Control Request"
NBUSY NSSFLAG NDBCA
Discrete Signals
BCST Output high indicates command received broadcast. Signal will remain high until next command received.
Broadcast Command received
MCDET Output high indicates command received mode command. Signal will remain high until next command received.
Mode Code Command received NCMDSTRB This signal indicates that completely validated message been received standard subaddress data activity. Mode commands with without data will generate this signal. NCMDSTRB signal long indication that burst will initiate NCMDSTRB transfer words between word data memory internal main RAM. subsystem read writes main that have been acknowledged (NACK "0") before NCMDSTRB begun must completed within subsystem read write requests main initiated after NCMDSTRB begun will held acknowledge) until cycle been completed. length cycle dependant number words into RAM. Access word memory still possible during cycle subsystem. However, transfers between memory main will locked out. NDBC Active indicates that command received Remote Terminal mode code Dynamic Control. Signal will remain until next command received.
APPLICATION NOTE #108
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NSYNC
Signal subsystem indicating receipt Synchronize mode commands mode code associated data word, will available T0-T15 this time. there associated data word, T0-T15 will zero. Early indication that Command Word been received being processed. Command Word received available T0-15 decoding this time. user this signal message illegalization Status bits. Access valid data word real time before being written RAM. Data word available T0-T15 during active signal. Input illegalise command Remote Terminal with clear status response. signal sampled after NVCR except mode code receive commands which case sampled after last data word been received. this input will illegalise message, Command will stored Command Status memory transfers from main will take place. device will respond with clear status unless been specifically set. data will transmitted following status.
NVCR
NDATA NILLCMD
Discrete Signals
NNEWBUS Control sequence normally initiated until current sequence completed, indicated signal EOT. However, Control sequence terminated restarted NNEWBUS active along with write address (000h). This feature would only used switching. Indicates that valid transfer been completed selected. Valid transfer completed Completed Indication that error occurred either information transferred unit from subsystem transfers 1553 data bus. Nature error available reading from register location (012h). Error occurred error This signal goes indicate valid transfer been completed 1553 data received Status word available T0-T15 highway. Status word also stored Command Status memory this time. Once signal goes high data received Controller transfer) will transferred main from word data buffer memory. Note: Data transferred transfers stored Controllers main RAM. used illegalise message just received. Signal tied STATUS illegalisation 1760 checksum failures. will prevent data received being transferred main RAM, Status word will stored Command Status memory.
ERROR
NSTSTRB
NNINHST
APPLICATION NOTE #108
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Remote Terminal (RT) Mode
SEQUENCE OPERATION
following section describes sequence operation various commands that received SmaRT unit Mode.
RECEIVE COMMAND
incoming command word verified protocol checks (such parity count). verified command word placed T0-15 NVCR signal strobed. this time that message illegalized. Each successive data word after command word placed internal buffer FIFO. This done double buffer incoming data complete message verification. Only after message completely validated will data transferred internal RAM. Otherwise, contents FIFO automatically flushed. This ensures that only valid data will ever read subsystem. transfer from FIFO accomplished fast burst. guarantee only valid data greatly simplifies MIL-STD-1553 implementation. Error handling data required subsystem. subsystem allowed most flexibility access without contending with 1553 traffic. 1553, data words received rate µSec word maximum time µSec word transfer. Many other systems buffer incoming data all. That means that periodically being updated with data words into µSeconds. error occurs, corrupt data already memory must sorted subsystem microprocessor. Smart unit buffers data that completely available subsystem until transfer occurs. possibilities memory contention greatly reduced contents guaranteed valid. When entire received data words transferred buffer FIFO, NCMDSTRB goes indicating that completely validated message been received. received Command Word again appears T0-15 this time. NCMDSTRB strobe will initiate cycle transfer data words from buffer FIFO internal RAM. NCMDSTRB pulse µSec long during this time interval, arbitration logic active. subsystem already begun read/write operation before NCMDSTRB, NACK (acknowledge) signal will nSec allowing completion read/write command. read/write operation must completed within remaining µSec. read/write operation starts after NCMDSTRB strobe begun, NACK will occur thus hold subsystem duration cycle internal RAM. During NCMDSTRB, Command Word loaded into Command/Status FIFO stack NEMPTY line goes high. user utilize this signal indication that some activity occurred. Command/Status FIFO stores command words subsystem review. This allows processor only response 1553 unit when something occurred. Constant polling 1553 unit required. reduce
APPLICATION NOTE #108
Released 9/98
processor intervention even further, Command/Status FIFO will only store commands that have associated data with
MESSAGE ILLEGALIZATION
message illegalized applying active signal within nSec rising edge NVCR this time. signal pulled low, will respond with Status word having Message Error set.
T0-15
NVCR
nSec nSec
implement this function place latching PROM T0-T10 data bus. PROM would only have decode bits bits subaddress, bits word count, T/R) have output place high/low level input pin. upper five bits (T11-T15) just Remote Terminal address unit which constant decode these bits necessary. latching signal PROM would NVCR line. will read acted upon nSec after rising edge NVCR. signal would remain latched stable until next rising edge NVCR.
MIL-STD-1760 FEATURES
enable 1760 features checksum validation, NENCHK line held low. This enables integrated on-chip hardware checksum features. hardware automatically checks incoming message correct checksum.
1760 HEADER WORD
signal NHDR will early indicator 1760 header word. This headerword will appear T0-15 when NHDR signal low. NHDR signal will every header word (first data word) even 1760 checksum circuitry enabled not. NHDR just indicator first data word T0-15. T0-15 1760
NHDR nSec
APPLICATION NOTE #108
Released 9/98
SIGNALS THAT INDICATE CHECKSUM FAILURE
1760 applications, STATUS line indicates message failed checksum. STATUS line will toggle down each received data word calculating checksum sampled falling edge NCMDSTRB. STATUS line tied Status Word inputs those bits event checksum fail. STATUS open output line that will selected Status Word Bits Status Word response current message. This great features this product. subsystem does have verify checksum software detect error. SmaRT unit automatically does this hardware unit able flag error Status Word CURRENT Status Word response This minimizes processor overhead reduces response time notifying Controller that error occurred. 1760 applications, NVALCHK signal also indicates valid checksum Receive Command message. NVALCHK latched version STATUS signal updated only Receive Commands. valid falling edge NCMDSTRB Receive Command remains stable until next Receive Command message. Transmit Command message will alter this signal because Transmit Command does require incoming checksum validation.
T0-15 NEMPTY STATUS
VALID
NVALCHK NCMDSTRB µSec
Latched Until Next Receive Command
BLOCK TRANSFER LOGIC
Block Transfer Logic (BTL) enabled both Remote Terminal Controller. consists word memory buffering subsystem main thus guaranteeing data consistency both transmit receive transfers. reads writes identical read write main RAM. address locations same. only difference that circuitry will intercept those read
APPLICATION NOTE #108
Released 9/98
writes store them buffer instead. user accesses same locations they would they were directly accessing main RAM. block transfer logic enabled with signal NENBTL (pin being active applicable subaddress (unless McAir selected) areas ram. block transfer logic also configured writing certain address locations providing NENBTL selected, 402h 403h 404h 405h Disable Read Disable Read Enable Read Enable Read Disable Write Enable Write Disable Write Enable Write
Reset will enable both Write Read. Note: 257X versions with internal that have NENBTL dsiscrete input have enabled internally.
READ (RECEIVE)
Read functions similarly Write that buffers read activity. subsystem read will initially generate that entire portion subaddress stored buffer. subsystem then read data leisure while main free future updates. Since entire portion subaddress data from RAM, data read from buffer guaranteed contiguous. user must read data from device specific sequence starting with first word received location ending with last word received location subaddress. will sense read from location reset sequence ready access. first word received message will read first, this will initiate burst transfer complete message from main memory word buffer memory, during which time subsystem will locked out. Data transferred rate word. system then read data from leisure. last word read will last word received message read from location zero. This will reset block transfer logic. 1553 transfer main becomes active during burst transfer, transfer will complete then locked until 1553 complete. However word buffer memory will accessible subsystem this time read data. 1553 transfer main becomes active before start burst transfer, transfer will belocked until 1553 complete. system will locked during this time (main being accessed 1553 word buffer memory waiting receive message). When 1553 complete burst transfer will take place then unlock subsystem.
APPLICATION NOTE #108
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Once burst transfer commenced will complete, thus ensuring data consistency.
TRANSFER TIMES
cycle transfers words from FIFO internal rate word each µSec. maximum cycle time could possibly occur data word transfer accessed beginning NCMDSTRB Strobe. Maximum subsystem hold-off time would µSec (NCMDSTRB Signal) µSec (0.5 µSec word) total 24.5 µSec.
TRANSMIT COMMAND
incoming command word verified protocol checks (such parity count). verified command word placed T0-15 NVCR signal strobed. this time that message illegalized.
T0-15
NVCR
nSec nSec
message illegalized applying active signal within nSec rising edge NVCR this time. will respond with Status word having Message Error set. Section 1.2.1.1 implementing Message Illegalization. NCMDSTRB goes indicating that completely validated message been received. validated Command Word again appears T0-15 this time. NCMDSTRB strobe will initiate cycle transfer data words from internal buffer FIFO. Buffering outgoing message with FIFO means that subsystem allowed most flexibility access without contending with 1553 traffic. 1553, data words transmitted rate µSec word maximum time µSec word transfer. Many other systems buffer outgoing data all. That means that periodically being accessed data words from µSeconds. SmaRT unit buffers outgoing data that completely available subsystem after transfer from occurs. possibilities memory contention greatly reduced contents outgoing data will affected subsystem operations. NCMDSTRB pulse µSec long during this time interval, arbitration logic active. subsystem already begun read/write operation before NCMDSTRB, NACK (acknowledge) signal will nSec allowing
APPLICATION NOTE #108
Released 9/98
completion read/write command. read/write operation must completed within remaining µSec. read/write operation starts after NCMDSTRB strobe begun, NACK will occur thus hold subsystem duration cycle from internal RAM. During NCMDSTRB, Command Word loaded into Command/Status FIFO stack NEMPTY line goes high. user utilize this signal indication that some activity occurred. Command/Status FIFO stores command words subsystem review. This allows processor only response 1553 unit when something occurred. Constant polling 1553 unit required. reduce processor intervention even further, Command/Status FIFO will only store commands that have associated data with
MIL-STD-1760 FEATURES
1760 features enabled (NENCHK line held low), checksum word automatically generated transmitted last data word. subsystem processor does have calculate load checksum word into RAM. SmaRT unit automatically does this hardware transmits correct checksum data word last word out. This reduces subsystem processor overhead significantly.
SIGNALS THAT INDICATE CHECKSUM FAILURE
1760 applications, STATUS line indicates message failed checksum. STATUS line will stay high Transmit Command word because there associated data words received checksum validation. STATUS sampled falling edge NCMDSTRB. STATUS line tied Status Word inputs those bits event checksum fail. STATUS open output line that will selected Status Word Bits Status Word response current message. This great features this product. subsystem does have verify checksum software detect error. SmaRT unit automatically does this hardware unit able flag error Status Word CURRENT Status Word response This minimizes processor overhead reduces response time notifying Controller that error occurred. 1760 applications, NVALCHK signal does change from it's previous state since Transmit Command Word incoming data words. NVALCHK latched version STATUS signal updated only Receive Commands. valid falling edge NCMDSTRB Receive Command remains stable until next Receive Command message. Transmit Command message will alter this signal because Transmit Command does require incoming checksum validation.
T0-15
NCMDSTRB
NEMPTY
NVALCHK
µSec
PREVIOUS STATE
Released 9/98
APPLICATION NOTE #108
BLOCK TRANSFER LOGIC TRANSFER TIMES
reads writes identical read write main RAM. address locations same. only difference that circuitry will intercept those read writes store them buffer instead. user accesses same locations they would they were directly accessing main RAM. block transfer logic also configured writing certain address locations providing NENBTL selected, 402h 403h 404h 405h Disable Read Disable Read Enable Read Enable Read Disable Write Enable Write Disable Write Enable Write
Reset will enable both Write Read.
WRITE
Write Logic basically stores writes particular subaddress buffer until subsystem completed entire subaddress update. When subsystem finished, will generate burst from main contiguous transfer. This guarantees that entire subaddress updated. Until transfer buffer allows main free updates from 1553 data bus. user must write data device specific sequence starting with first word transmission location ending with last word transmission location subaddress. will sense write location initiate sequence. Data message written word buffer memory speed subsystem. first word transmission written first location last word transmission written last location subaddress. address first word stored register counter within "block transfer logic". last word transmission always written location zero, this will trigger transfer data from word buffer memory main memory. Data transferred rate word. full word transfer will take approximately 1553 quiet entire message will immediately transferred single burst main memory, address being generated counter within block transfer logic. During this transfer subsystem will locked NACK from updates. 1553 transfer main becomes active during burst transfer, transfer will complete then locked updates until 1553 complete. However buffer memory will accessible subsystem this time. 1553 transfer main becomes active before start burst transfer, transfer will locked (after location zero written until 1553 complete. system will locked during this time (main being accessed
APPLICATION NOTE #108
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1553 buffer memory full). memory fully loaded, subsystem continue load memory until full (write indicates full condition). When 1553 complete burst transfer will take place then unlock subsystem. Once burst transfer commenced will complete, thus ensuring data consistency. cycle begins after rising edge NCMDSTRB. requested data words placed internal buffer FIFO. This done double buffer outgoing data contiguous block free internal quickly possible. cycle transfers words from internal rate word each µSec. maximum cycle time would occur data word transfer µSec. Maximum subsystem hold-off time would 8.5µSec µSec total 40.5 µSec.
CHANGING STATUS WORD BITS
There four Status word bits that altered subsystem through simple write operations. These four bits addresses follows: SERVREQ 008h BUSY 004h SSFLAG 002h DBCA 001h Memory further details.
DEVICE STATUS
status device determined reading from location status bits status will available DATA pins 0-7. DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DBCA SSFLAG SSBUSY SERVREQ WRITE ENABLED READ ENABLED OFF-LINE SELF TEST ENABLED ON-LINE SELF TEST ENABLED
Memory further details.
REGISTER
With MCAIR (pin disabled, writing data will content register. data also read from these locations. This register non-resetable. Memory further details.
APPLICATION NOTE #108
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DATA STORAGE RETRIEVAL
storage retrieval data optimized fast processor accesses. data (Transmit Receive) stored with first data word (Word memory location last data word (Word location processor reads Command word extracts bit, subaddress, word count bits pointer proper memory location. word count field used down counter variable that Loop routine executed then branched counter This more efficient some compilers than counter comparing current loop counter with word count field every loop. following section contains sample software pseudo code data handling. Memory further details.
SAMPLE SOFTWARE CODE
following section contains sample pseudo-code programming operation SmaRT unit. code most resembles Microsoft Quick Basic code (IBM compatible) simplicity. RETRIEVING LOADING DATA Routines operation Remote Terminal (RT) Mode Variables NCMDEMPTY EMPTY Command WORDS FIFO) HAVE COMMAND WORDS FIFO This signal derived from NEMPTY CT2577. MODE MODE MODE CMDWORD COMMAND WORD READ FROM FIFO WORDCNT LOWER COMMAND WORD INDICATES MANY DATA WORDS DATA() DATA ARRAY WORDS MAX) MEMPOINT LOWER BITS COMMAND WORD T/R_BIT COMMAND WORD
APPLICATION NOTE #108
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************ INITIALIZATION ROUTINE INIT: DEFINT 400(h) "WRITE THIS ADDRESS CT2577 INTO MODE INPUT MODE, XX(h) "READ BCNRT FROM CT2577 MODE MODE DATA(32) "LOCATIONS 1-32 WORDS ************ DETECT COMMAND ROUTINE DETECT: NCMDEMPTY THEN CMDWORD INPUT(OOh) ;READ FROM LOCATION MEMPOINT CMDWORD 0000011111111111(b) T/R_BIT CMDWORD 0000010000000000(b) WORDCNT CMDWORD 0000000000011111(b) MEMPOINT MEMPOINT "OFFSET POINTER THAT FINAL POSITION LOCATION EXAMPLE, "WORD TRANSFER SHOULD LOADED "LOCATION THAT SUBADDRESS. WORDCNT 00000(b) THEN WORDCNT "ALL ZEROS WORD COUNT FIELD DATA WORDS T/R_BIT 0000000000000000(b) THEN REDIM DATA() ;CLEARS ARRAY DATA() ROUTINE READ RECEIVED DATA FROM 1553 GOTO RECEIVE T/R_BIT 0000010000000000(b) THEN REDIM DATA() ;CLEARS ARRAY DATA()
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DATA(J) XXXX ;LOAD DATA TRANSMIT NEXT GOTO TRANSMIT GOTO ROUTINE LOAD DATA INTO FROM PROCESSOR ************************* TRANSMIT: WORDCNT OUTPUT DATA(I), MEMPOINT WRITES DATA() INTO LOCATION MEMPOINT MEMPOINT MEMPOINT NEXT GOTO ROUTINE READ DATA FROM PROCESSOR RECEIVE: WORDCNT DATA(I) INPUT(MEMPOINT) READS LOCATION MEMPOINT INTO DATA() ARRAY MEMPOINT MEMPOINT NEXT GOTO ROUTINE SCAN MORE MESSAGES END: NCMDEMPTY THEN GOTO DETECT ELSE RETURN SOMETHING ELSE UNTIL ANOTHER 1553 MESSAGE RECEIVED
APPLICATION NOTE #108
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SELF TEST
self test feature internal external loop back test additional verification functionality. This addition Remote Terminal Wraparound circuitry. difference that this test manual under subsystem control. subsystem microprocessor initiates self test subsequent data word pattern. subsystem then reads back wrapped data word determines correct. online self test must done with 1553 data quiet. self test function enabled disabled writing certain address locations. Reset will disable self test. Enable offline self test device status Enable online self test device status Disable self test
When self test enabled device both When self test disabled device will revert back previous state.
BASIC OPERATION
basic operation transmit message "receive data word" receive this message. online self test selected message will transmitted onto 1553 transceivers received transceivers. will respond with Status. offline self test selected transceivers will inhibited Manchester encoder output routed Manchester decoder input. status device obtained reading from offline self test enabled. online self test enabled.
DETAILED OPERATION
Enable self test writing either (offline) (online). Select required 1553 data tested writing
Write data word contents required self test appropriate location broadcast message: 2(bcast) 01-1E(subaddress) 00(1 word) normal receive message: 0(rec) 01-1E(subaddress) 00(1 word). Initiate transfer data word writing address with data word content RTaddr 0(rec) 01-1E(subaddress) 01(1 data word). following automatic sequence initiated: Command word (data word written location processed protocol, transferred Manchester encoder transmitted onto (online self test) Manchester decoder (offline self test).
APPLICATION NOTE #108
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self test data word read from appropriate location, transferred encoder transmitted contiguously following command word. Command word received Manchester decoder, valid with correct address broadcast stored protocol. data word received decoder valid stored word data memory. protocol will validate message successful will write Command word word Command Status memory transfer data word appropriate location. data word received written same location that originally accessed from, contents should altered while self test progress (eg. write 0000). This done immediately after transfer initiated. There approx self test complete.
ensure that contents have been altered advisable read data back from RAM. completion successful self test signal NCMDSTRB will active low, after which data read from compared with data used self test. addition Command word used self test read from Disable self test writing device will revert back original state RT).
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SUMMARY OPERATION
Device either
ADDR (Write) ADDR (Write) ADDR (Write) ADDR (Write) ADDR 01-1E (Write) DATA ADDR 01-1E (Write) DATA ADDR (Write) DATA 01-1E ADDR (Write) DATA RTAD 01-1E ADDR 01-1E (Write) DATA ADDR 01-1E (Write) DATA ADDR 01-1E (Read) DATA ADDR 01-1E (Read) DATA ADDR 01-1E (Read) DATA ADDR 01-1E (Read) DATA ADDR (Read) DATA 01-1E ADDR (Read) DATA RTAD 01-1E ADDR (Write) ADDR (Read) Select offline self test. Select online self test. Select Select Write self test data BCAST location. Write self test data RECEIVE location. Transmit message (Bcast receive word). Transmit message (Receive word). Write self test location. Write self test location. Read from self test location. Read from self test location. Read self test data after NCMDSTRB. Read self test data after NCMDSTRB. Read command from command memory. Read command from command memory. Disable self test. Read device status: Offline self test. Online self test
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CT2577 RT/BC Device Memory Breakdown
following description devices that have internal memory. 'User' Locations Read/Writable
BCST (Binary) (Binary)
Subaddress (Hex) Word Count (Hex) Composite Address 16-bit mode (Hex) Composite Address 8-bit mode (Hex) Lower Byte Upper Byte Address Composite MULTIbus Address 16-bit mode (Hex)
FUNCTION
0000 Command Word (2nd RT-RT Command) (BC) TRIGGERS Operation Received STATUS (FIFO Stack) (BC) Resets Status Bits (RT) Received COMMAND (RT) 0002 RT-RT COMMAND (BC) Memory Address through 00Fh (BC) Sets STATUS Word Flags Described below (RT) Status Bits WRITTEN (RT) Addresses 001-00F plus BURST Control Follows: Don't Care STATUS Word Bits Selected WRITEs through 00Fh BURST Control Selected WRITEs through 405h xxxx xxxx BUSY WRITE ENABLED (TX) READ ENABLED (RX)
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RT/BC Device Memory Code Breakdown Descriptions
STATUS WORD Control Sets
0002 0004 0006 0008 000A 000C 000E 0010 0012 0014 0016 0018 001A 001C 001E FFFE FFFD FFFC FFFB FFFA FFF9 FFF8 FFF7 FFF6 FFF5 FFF4 FFF3 FFF2 FFF1 FFF0 SSFLAG SSFLAG BUSY BUSY BUSY SSFLAG BUSY SSFLAG SERVREQ SERVREQ SERVREQ SSFLAG SERVREQ SSFLAG SERVREQ BUSY SERVREQ BUSY SERVREQ BUSY SSFLAG SERVREQ BUSY SSFLAG
Control Area
0020 FFEF 0040 SELECT FFE7BC SELECT
RT/RX BC/TX Mode Area Control
THROUGH 0022 0024 0026 0028 002A 002C 002E 0030 0020 0032 003E FFEE FFED FFEC FFEB FFEA FFE9 FFE8 FFE7 FFEF FFE6 FFE0 SYNC WORD ERROR Register User SELECTED SHUTDOWN (0000/0001) OVERRIDE SELECTED SHUTDOWN (0000/0001) User User SELECT SELECT User User
Receive Transmit Subaddresses 01-1E (1-30)
0040 0048 007E 0080 00BE 00C0 FFDF FFDB FFC0 FFBF FFA0 FF9F SA1Last Word (Word Word Word
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00FE 0100 013E 0140 017E 0180 01BE 01C0 01FE 0200 023E 0240 027E 0280 02BE 02C0 02FE 0300 033E 0340 037E 0380 03BE 03C0 03FE 0400 043E 0440 047E 0480 04BE 04C0 04FE 0500 053E 0540 057E 0580 05BE 05C0 05FE 0600 063E 0640 067E 0680 06BE 06C0 06FE
FF80 FF7F FF60 FF5F FF40 FF3F FF20 FF1F FF10 FEFF FEE0 FEDF FEC0 FEBF FEA0 FE9F FE80 FE7F FE60 FE5F FE40 FE3F FE20 FE1F FE00 FDFF FDE0 FDDF FDC0 FDBF FDA0 FD9F FD80 FD7F FD60 FD5F FD40 FD3F FD20 FD1F FD00 FCFF FCE0 FCDF FCC0 FCBF FCA0 FC9F FC80
SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27
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0700 073E 0740 077E 0780 07BE
FC7F FC60 FC5F FC40 FC3F FC20
SA28 SA29 SA30
RT/RX BC/TX Mode Area (31)
THROUGH THROUGH 07C0 07E0 07E2 07E4 07E6 07E8 07EA 07EC 07FE FC1F FC0F FC0E FC0D FC0C FC0B FC0A FC09 FC00 User User SYNC WORD User User SELECTED SHUTDOWN (0000/0001) OVERRIDE SELECTED SHUTDOWN (0000/0001) User User
RT/BC Control Area
0800 0802 FBFF FBFE SELECT SELECT
RT/BC Block Transfer Logic (BTL) Control Self Test Control
THROUGH 0804 0806 0808 080A 080C 080E 0810 0812 081E FBFD FBFC FBFB FBFA FBF9 FBF8 FBF7 FBF6 FBF0 OFF- LINE Self Test ON-LINE Self Test DISABLE Self Test User User
RT/TX BC/RX Mode Area
THROUGH 0820 0822 0824 0826 0828 083E FBEF FBDF FBCF FBBF FBAF FBE0 VECTOR WORD User LAST COMMAND WORD User User
APPLICATION NOTE #108
Released 9/98
Transmit Receive Subaddresses 01-1E (1-30)
0840 0848 087E 0880 08BE 08C0 08FE 0900 093E 0940 097E 0980 09BE 09C0 09FE 0A00 0A3E 0A40 0A7E 0A80 0ABE 0AC0 0AFE 0B00 0B3E 0B40 0B7E 0B80 0BBE 0BC0 0BFE 0C00 0C3E 0C40 0C7E 0C80 0CBE 0CC0 0CFE 0D00 0D3E 0040 0D7E 0D80 0DBE 0DC0 FBDF FBDB FBC0 FBBF FBA0 FB9F FB80 FB7F FB60 FB5F FB40 FB3F FB20 FB1F FB00 FAFF FAE0 FADF FAC0 FABF FAA0 FA9F FA80 FA7F FA60 FA5F FA40 FA3F FA20 FA1F FA00 F9FF F9E0 F9DF F9C0 F9BF F9A0 F99F F980 F97F F960 F95F F940 F93F F920 F91F Last Word (Word Word Word SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23
APPLICATION NOTE #108
Released 9/98
0DFE 0E00 0E3E 0E40 0E7E 0E80 0EBE 0EC0 0EFE 0F00 0F3E 0F40 0F7E 0F80 0FBE
F900 F8FF F8E0 F8DF F8C0 F8BF F8A0 F89F F880 F87F F860 F85F F840 F83F F820
SA24 SA25 SA26 SA27 SA28 SA29 SA30
BC/RX Mode Area (31)
THROUGH THROUGH 0FC0 0FDE 0FE0 0FE2 0FE4 0FE6 0FE8 0FFE F81F F810 F80F F80E F80D F80C F80B F800
VECTOR WORD User LAST COMMAND WORD User User
Broadcast RT/RX BC/TX Mode Area
THROUGH THROUGH 1000 1020 1022 1024 1036 1028 102A 102C 103E F7FF F7EF F7EE F7ED F7EC F7EB F7EA F7E9 F7E0 User User SYNC WORD User User SELECTED SHUTDOWN (0000/0001) OVERRIDE SELECTED SHUTDOWN (0000/0001) User User
Broadcast Receive Transmit Subaddresses 01-1E (1-30)
1040 1048 107E 1080 10BE F7DF F7DB F7C0 F7BF F7A0 Last Word (Word Word Word
APPLICATION NOTE #108
Released 9/98
10C0 10FE 1100 113E 1140 117E 1180 11BE 11C0 11FE 1200 123E 1240 127E 1280 12BE 12C0 12FE 1300 133E 1340 137E 1380 13BE 13C0 133E 1400 143E 1440 147E 1480 14BE 14C0 14FE 1500 153E 1540 157E 1580 15BE 15C0 15FE 1600 163E 1640 167E 1680 16BE 16C0
F79F F780 F77F F760 F75F F740 F73F F720 F71F F700 F6FF F6E0 F6DF F6C0 F6BF F6A0 F69F F680 F67F F660 F65F F640 F63F F620 F61F F600 F5FF F5E0 F5DF F5C0 F5BF F5A0 F59F F580 F57F F560 F55F F540 F53F F520 F51F F500 F4FF F4E0 F4DF F4C0 F4BF F4A0 F49F
SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27
APPLICATION NOTE #108
Released 9/98
16FE 1700 173E 1740 177E 1780 17BE
F480 F47F F460 F45F F440 F43F F420
SA28 SA29 SA30
Broadcast RT/RX BC/TX Mode Area (31)
THROUGH THROUGH 17C0 17E0 17E2 17E4 17E6 17E8 17EA 17EC 17FE F41F F40F F40E F40D F40C F40B F40A F409 F400 User User SYNC WORD User User SELECTED SHUTDOWN (0000/0001) OVERRIDE SELECTED SHUTDOWN (0000/0001) User User
APPLICATION NOTE #108
Released 9/98
CT2577 Part Ordering Information
APPLICATION NOTE #108
Released 9/98
CT2577 Mil-Std 1553 1760 Controller/Remote Terminal
CT2577-
Quad Flatpack Full 883C Screened Part (-550C +1250C) Extended Temperature Range (-550C +1250C) Industrial Temperature Range (-400C +850C) Commercial Grade (00C +700C) Function Selection
Memory Enabled (T0-T15 Bus) Memory Enabled (T0-T10 Bus) Stores Pinout Stores Pinout
APPLICATION NOTE #108
Released 9/98
CT2578 Mil-Std 1553 1760 Remote Terminal Only
CT2578-
Quad Flatpack Full 883C Screened Part (-550C +1250C) Extended Temperature Range (-550C +1250C) Industrial Temperature Range (-400C +850C) Commercial Grade (00C +700C) Function Selection
Memory Enabled (T0-T15 Bus) Memory Enabled (T0-T10 Bus) Memory Enabled (DMA) Stores Pinout Stores Pinout
APPLICATION NOTE #108
Released 9/98
CT2579 McAir Remote Controller/Remote Terminal
CT2579-
Quad Flatpack Full 883C Screened Part (-550C +1250C) Extended Temperature Range (-550C +1250C) Industrial Temperature Range (-400C +850C) Commercial Grade (00C +700C) Function Selection
Memory Enabled (T0-T15 Bus) Memory Enabled (T0-T10 Bus) Stores Pinout Stores Pinout
APPLICATION NOTE #108
Released 9/98
CT2580 McAir Remote Terminal Only
CT2580-
Quad Flatpack Full 883C Screened Part (-550C +1250C) Extended Temperature Range (-550C +1250C) Industrial Temperature Range (-400C +850C) Commercial Grade (00C +700C) Function Selection
Memory Enabled (T0-T15 Bus) Memory Enabled (T0-T10 Bus) Stores Pinout Stores Pinout
APPLICATION NOTE #108
Released 9/98
CT2577 Pinouts
APPLICATION NOTE #108
Released 9/98
CT2577-01-xx-F84 Pinouts Quad Flatpack
Description ADIN ADIN ADIN BCNRT NSYNC ADIN Connected Connected ADIN ADIN MCDET NVCR BCST ADIN ADIN ADDR NDBC ADDR ADDR ADDR ADDR NACK ADDR DATA (Bus NDATA (Bus NSTSTRB NCARDEN ERROR VDD1 VSS1 C16MHZ ADIN ADIN ADIN NRES/NRCL ADIN Description NCMDSTRB NEMPTY DATA DATA NSSFLAG NBIT16 Connected DATA Connected DATA DATA DATA WRAPEN DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA (Bus NDATA (Bus NFULL DATA VDD2 VSS2 NILLCMD VME(/MULTI)
APPLICATION NOTE #108
Released 9/98
CT2577-11-xx-F84 Pinouts Quad Flatpack
Description ADIN ADIN ADIN BCNRT NSYNC ADIN NVALCHK (1760) STATUS (1760) ADIN ADIN NENCHK (1760) NVCR BCST ADIN ADIN ADDR NDBC ADDR ADDR ADDR ADDR NACK ADDR DATA (Bus NDATA (Bus NSTSTRB NCARDEN ERROR VDD1 VSS1 C16MHZ ADIN ADIN ADIN NRES/NRCL ADIN Description NCMDSTRB NEMPTY DATA DATA NSSFLAG NBIT16 NHDR (1760) DATA STREL (1760) DATA DATA DATA WRAPEN DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA (Bus NDATA (Bus NFULL DATA VDD2 VSS2 NILLCMD VME(/MULTI)
APPLICATION NOTE #108
Released 9/98
CT2579-01-xx-F84 Pinouts Quad Flatpack
Description ADIN ADIN ADIN BCNRT NSYNC ADIN Connected Connected ADIN ADIN MCDET NVCR BCST ADIN ADIN ADDR NDBC ADDR ADDR ADDR ADDR NACK ADDR DATA (Bus NDATA (Bus NSTSTRB NCARDEN ERROR VDD1 VSS1 C16MHZ ADIN ADIN ADIN NRES/NRCL ADIN Description NCMDSTRB NEMPTY DATA DATA NSSFLAG NBIT16 Connected DATA Connected DATA DATA DATA WRAPEN DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA (Bus NDATA (Bus NFULL DATA VDD2 VSS2 NILLCMD VME(/MULTI)
APPLICATION NOTE #108
Released 9/98
CT2579-11-xx-F84 Pinouts Quad Flatpack
Description ADIN ADIN ADIN BCNRT NSYNC ADIN NVALCHK (1760) STATUS (1760) ADIN ADIN NENCHK (1760) NVCR BCST ADIN ADIN ADDR NDBC ADDR ADDR ADDR ADDR NACK ADDR DATA (Bus NDATA (Bus NSTSTRB NCARDEN ERROR VDD1 VSS1 C16MHZ ADIN ADIN ADIN NRES/NRCL ADIN Description NCMDSTRB NEMPTY DATA DATA NSSFLAG NBIT16 NHDR (1760) DATA STREL (1760) DATA DATA DATA WRAPEN DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA (Bus NDATA (Bus NFULL DATA VDD2 VSS2 NILLCMD VME(/MULTI)
APPLICATION NOTE #108
Released 9/98
CT2577-10-xx-P119 Pinouts Grid Array
Description NENBTL DATA DATA 1(BUS) DATA ADIN NFULL DATA DATA DATA INITWD NILLCMD NDATA 1(BUS) DATA DATA DATA ADIN ADIN Description DATA DATA NSYNC BCNRT WRAPEN DATA MCAIR ADIN DATA DATA NVALCHK ADIN STATUS DATA STREL NHDR ADIN NENCHK MCDET NBUSY NBIT16 WATCHDOG NVCR DATA NSSFLAG BCST ADIN ADDR NNEWBUS SELEN DATA Description ADIN ADDR NACK NDATA (BUS) NINHST ADIN ADIN NCMDSTRB NDBCA NTXINH SELEN NDBC ADDR NSTSTRB INHMC ADIN NRES NTXINH ADDR ADDR ADDR DATA 0(BUS) NCARDEN ERROR C16MHZ NDATA ADIN NEMPTY
APPLICATION NOTE #108
Released 9/98
CT2579-10-xx-P119 Pinouts Grid Array
Description NENBTL DATA DATA 1(BUS) DATA ADIN NFULL DATA DATA DATA INITWD NILLCMD NDATA 1(BUS) DATA DATA DATA ADIN ADIN Description DATA DATA NSYNC BCNRT WRAPEN DATA MCAIR ADIN DATA DATA NVALCHK ADIN STATUS DATA STREL NHDR ADIN NENCHK MCDET NBUSY NBIT16 WATCHDOG NVCR DATA NSSFLAG BCST ADIN ADDR NNEWBUS SELEN DATA Description ADIN ADDR NACK NDATA (BUS) NINHST ADIN ADIN NCMDSTRB NDBCA NTXINH SELEN NDBC ADDR NSTSTRB INHMC ADIN NRES NTXINH ADDR ADDR ADDR DATA 0(BUS) NCARDEN ERROR C16MHZ NDATA ADIN NEMPTY
APPLICATION NOTE #108
Released 9/98
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