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Z80380 USER'S MANUAL
Thank your interest Z380Central Processing Unit (CPU) associated family products. This Technical Manual describes programming operation Z380SuperintegrationCore CPU, which found Z380 Microprocessor Unit (MPU), products built around Z380CPU core.
This Z380 User's Manual consists following Sections: Z380Architectural Overview Chapter introductory section covering features giving overview architecture device. Address Spaces Chapter explains address spaces Z380 handle. Also, this chapter includes brief description on-chip registers. Native/Extended Mode, Word/Long Word Mode Operation, Decoder Directives This chapter provides detailed explanation Z380's unique features, operation modes, Decoder Directives. Addressing Modes Data Types Chapter describes Addressing mode data types which Z380 handle. Instruction Chapter contains overview instruction set; well detailed instruction-by-instruction description alphabetical order. Interrupts Traps Chapter explains interrupts traps features Z380. Reset Chapter describes Reset function. Z380 Benchmark Appnote Z380 Questions Answers
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Appendix Appendix covers Z380's instruction format. Appendix Appendix contains Z380 instructions sorted Alphabetical Order. Appendix Appendix contains Z380 instructions sorted Numerical Order. Appendix Tables Appendix lists Z380 instructions instruction affected Native/Extended mode Word/Long Word mode. Appendix Tables Appendix lists Z380 instructions instruction affected DDIR (Immediate Decoder Directives) mode. Index listing Z380User's Manual words phrases.
This manual assumes reader basic knowledge CPUbased system architectures software development systems, such text editor, invoking assembler/ compiler. Also, knowledge Z80® architecture desirable.
1994, 1995, 1996, 1997 Zilog, Inc. rights reserved. part this document copied reproduced form means without prior written consent Zilog, Inc. information this document subject change without notice. Devices sold Zilog, Inc. covered warranty patent indemnification provisions appearing Zilog, Inc. Terms Conditions Sale only. ZILOG, INC. MAKES WARRANTY, EXPRESS, STATUTORY, IMPLIED DESCRIPTION, REGARDING INFORMATION FORTH HEREIN REGARDING FREEDOM DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT. ZILOG, INC. MAKES WARRANTY MERCHANTABILITY FITNESS PURPOSE. Zilog, Inc. shall responsible errors that appear this document. Zilog, Inc. makes commitment update keep current information contained this document.
Zilog's products authorized critical components life support devices systems unless specific written agreement pertaining such intended executed between customer Zilog prior use. Life support devices systems those which intended surgical implantation into body, which sustains life whose failure perform, when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. Zilog, Inc. East Hacienda Ave. Campbell, 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 370-8056 Internet: http://www.zilog.com
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USER ANUAL
USER's MANUAL
CHAPTER
Z380ARCHITECTURAL OVERVIEW
INTRODUCTION
Z380 incorporates advanced architectural features that allow fast efficient throughput increased memory addressing capabilities while maintaining Z80® Z180® object-code compatibility. Z380 core provides continuing growth path present Z80- Z180®-based designs offers following features:
Full Static CMOS Design with Power Standby Mode Support Operating Frequency Volts Operating Frequency Volts Enhanced Instruction that Maintains Object-Code Compatibility with Z180 Microprocessors 16-Bit (64K) 32-Bit (4G) Linear Address Space 16-Bit Internal Data Clock Cycle Instruction Execution (Minimum) Multiple On-Chip Register Files (Z380 Four Banks) BC/DE/HL/IX/IY Registers Augmented 16-Bit Extended Registers (BCz/DEz/HLz/IXz/IYz), PC/SP/I Registers Augmented Extended Registers (PCz/ SPz/Iz) 32-Bit Addressing Capability. Newly Added Registers with Extended Registers (IXz'/IYz') Enhanced Interrupt Capabilities, Including 16-Bit Vector Undefined Opcode Trap Full Z380 Instruction
Z380 CPU, enhanced version CPU, retains instruction maintain complete binary-code compatiblity with present Z180 codes. basic addressing modes microprocessor have been augmented with Stack Pointer Relative loads stores, 16-bit 24-bit Indexed offsets, increased Indirect register addressing flexibility, with addressing modes allowing access entire 32-bit address space. Significant additions have been made instruction iincorporating16-bit arithmetic logical operations, 16-bit operations, multiply divide, complete register-to-register loads exchanges, plus 32-bit load exchange, 32-bit arithmetic operation address calculation. basic register file microprocessor expanded include alternate register versions registers. There four sets this basic microprocessor register file present Z380 MPU, along with necessary resources manage switching between different register sets. register pairs index registers basic microprocessor register file expanded bits. Z380 expands basic Kbyte Z180 address space full Gbyte (32-bit) address space. This address space linear completely accessible user program. external address space similarly expanded full Gbyte (32-bit) range, 16bit I/O, both simple block move included. byte-wide internal space been added. This space will used access on-chip resources future Superintegration implementation this core. Figure provides detailed description basic register architecture Z380 with size register banks shown four each, however, Z380 architecture allows future expansion sets each.
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Z380USER'S MANUAL
INTRODUCTION (Continued)
Sets Registers IXU' IYU' IXL' IYL'
BCz' DEz' HLz' IXz' IYz'
Figure 1-1. Z380CPU Register Architecture
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ARCHITECTURE
Z380 binary-compatible extension Z180 architecture. High throughput rates achieved high clock rate, high bandwidth, instruction fetch/execute overlap. Communicating external world through 8-bit 16-bit data bus, Z380 full 32-bit machine internally, with 32-bit 32-bit registers. will return Z380 Native mode. This restriction applies because possibility "misplacing" interrupt service routines vector tables during transition from Extended mode back Native mode. 1.2.1.2 Word Long Word Mode addition Native Extended mode, which specific memory space addressing, Z380 operate either Word Long Word mode specific data load exchange operations. Word mode (the Reset configuration), word load exchange operations manipulate 16-bit quantities. example, only loworder words source destination exchanged exchange operation, with high-order words unaffected. Long Word mode, bits source destination exchanged. Z380 implements instructions plus decoder directives allow switching between Word Long Word mode; SETC (Set Control Long Word) RESC (Reset Control Long Word) perform global switch, while DDIR DDIR their variants decoder directives that select particular mode only instruction that they precede. Note that word data arithmetic opposed address manipulation arithmetic), rotate, shift, logical operations always 16-bit quantities. They controlled either Native/Extended Word/Long Word selections. exceptions 16-bit quantities are, course, those multiply divide operations with 32-bit products dividends. word Input/Output operations performed 16-bit values, regardless Word/Long Word operation.
1.2.1 Modes Operation
maintain compatibility with Z80/Z180 while having capability manipulate Gbytes memory address range, Z380 bits Select Register (SR) control modes operation. controls address manipulation mode: Native mode Extended mode; other controls data manipulation mode: Word mode Long Word mode. result, Z380 four modes operation. reset, Z380 Native/Word mode, which compatible Z80/Z180's operation mode. details this subject, refer Chapter "Native/Extended Mode, Word/Long Word Mode Operation, Decoder Directive Instructions." 1.2.1.1 Native Mode Extended Mode Z380 operate either Native Extended mode, controlled Select Register (SR). Native mode (the Reset configuration), address manipulations performed modulo 65536 (216). this mode, Program Counter (PC) only increments across bits, address manipulation instructions (increment, decrement, add, subtract, indexed, stack relative, relative) only operate bits, Stack Pointer (SP) only increments decrements across bits. high-order word left zeros, high-order words register. Thus, Native mode fully compatible with CPU's Kbyte address mode. still possible address memory outside Kbyte address space data storage retrieval Native mode, however, since direct addresses, indirect addresses, high-order word registers loaded with non-zero values. Executed code interrupt service routines must reside lowest Kbytes address space. Extended mode, however, address manipulation instructions operate bits, allowing access entire Gbyte address space Z380 CPU. both Native Extended modes, Z380 drives bits address onto external address bus; only width manipulated addresses distinguishes Native from Extended mode. Z380 implements instruction allow switching from Native Extended mode (SETC XM); however, once Extended mode, only Reset
1.2.2 Address Spaces
Addressing spaces Z380 include register, control register, memory address, on-chip address, external address. register space superset register set, consists registers register file. These registers used data address manipulation, extension register set, with four sets this extended register present Z380 CPU. Access these registers specified instruction, with active register selected bits Select Register (SR) control register space.
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1.2.2 Address Spaces (Continued)
Each register includes primary registers well alternate registers IX', IY'. Also, IX', registers accessible byte registers, each named IXU, IXL, IXU' IXL', IYU, IYL, IYU', IYL'. These byte registers paired with with with with with with form word registers, these word registers extended bits with extension register. This register extension only accessible when using register 32-bit register Long Word mode) when swapping between most-significant least-significant word 32-bit register using SWAP instructions. Whenever instruction refers word register, implicit size controlled Word Long Word mode. Also included registers, well Select Register (SR) determines operation Z380 CPU. contents this register determine operating mode, which register bank will used, interrupt mode effect, Z380 CPU's memory address space linear Gbytes. keep compatibility with memory addressing model, control bits change operation modes-Native Extended, Word Long Word. Z380 architecture also distinguishes between memory addressing space and, therefore, requires specific instructions. Furthermore, addressing space subdivided into on-chip address space external addressing space. External addressing space Z380 bits long, internal addressing space 8-bits long. There separate sets instructions each addressing space. Some Internal registers used control functionality device, such program/read status Trap, Assigned Vector Base address, enabling interrupts, Chip version details this topic, refer Chapter "Address Spaces."
1.2.4. Addressing Modes
Addressing modes used Z380 calculate effective address operand needed execution instruction. Seven addressing modes supported Z380 CPU. these seven, addition addressing modes (Stack Pointer Relative) remaining modes either existing extensions addressing modes.
Register Immediate Indirect Register Direct Address Indexed Program Counter Relative Stack Pointer Relative
addressing modes available 8-bit load, arithmetic, logical instructions; 8-bit shift, rotate, manipulation instructions limited registers Indirect register addressing modes. 16-bit loads addressing registers support addressing modes except Index, while other 16-bit operations limited Register, Immediate, Indirect Register, Index, Direct Address, Relative addressing modes. details this subject, refer Chapter "Addressing Modes Data Types."
1.2.5. Instruction
Z380 instruction expansion instruction set; enhancements include support additional addressing modes instructions well addition instructions. Z380 instruction provides full complement 8-bit, 16-bit, 32-bit operation, including multiplication division. details this subject, refer Chapter "Instruction Set."
1.2.6 Exception Conditions
Z380 supports three types exceptions (conditions that alter normal flow program execution); interrupts, traps, resets. Interrupts asynchronous events typically triggered peripherals requiring attention. Z380 interrupt structure been significantly enhanced increasing number interrupt request lines adding efficient means handling nested interrupts. Z380 five interrupt lines. These are: Nonmaskable Interrupt line (/NMI) Maskable interrupt lines (/INT0, /INT1, /INT2, /INT3). Interrupt requests /INT3-/INT1
1.2.3 Data Types
Many data types supported Z380 architecture. basic data type 8-bit byte, which also basic addressable memory element. architecture also supports operations bits, (Binary Coded Decimal) digits, words bits bits), byte strings word strings. details this topic, refer Section 4.3, "Data Types."
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Z380USER'S MANUAL first three modes compatible with interrupt modes; fourth mode provides more flexibility. Traps synchronous events that trigger special response when undefined instruction executed. used increase system reliability, used "software trap instruction." Hardware resets occur when /RESET line activated override other conditions. /RESET causes certain control registers initialized. details this subject, refer Chapter "Interrupts Traps."
8080 compatible (Mode which interrupting device provides first instruction interrupt routine. Dedicated interrupts (Mode which jumps dedicated address when interrupt occurs. Vectored interrupt mode (Mode which interrupting peripheral device provides vector into table jump address. Enhanced vectored interrupt mode (Mode wherein expects 16-bit vector, instead 8-bit interrupt vectors Mode
BENEFITS ARCHITECTURE
Z380 architecture provides several significant benefits, including increased program throughput achieved higher bandwidth (16-bit wide bus), reduction clocks/basic machine cycle four clocks/cycle CPU), prefetch cue, access larger linear addressing space, enhanced instructions/new addressing mode, data/address manipulation 16/32 bits, faster context switching utilizing multiple register banks. technology improved over time, applications started demand more complicated processing, multitasking, faster processing, etc., with high level language needed develop software. result, Kbytes memory addressing space enough some based applications. order handle more than Kbytes memory, requires Memory Banking scheme, (Memory Management Unit), like Z180 Z280 MPU. These provide overhead access more than Kbytes memory. Z380 architecture allows access full Gbytes (232) memory addressing space well Gbytes addressing area, without using Memory Banking scheme, MMU.
1.3.1 High Throughput
Very high throughput rates achieved with Z380 CPU, basic machine cycle's reduction clocks/cycle from four clocks/cycle CPU, fine tuned four staged pipeline with prefetch cue. This well designed pipeline prefetch both totally transparent user, thus maximizing efficiency pipeline time. Z380 implemented onto Z380 configured with 16-bit wide data bus, which doubles bandwidth. These architectural features result clocks/instructions execution minimum, three clocks/instruction average. high clock rates MHz) achievable with this processor. Make overall performance Z380 more than times that Z80.
1.3.3. Enhanced Instruction with 16-Bit 32-Bit Manipulation Capability
Z380 instruction 100% upward compatible instruction set; that instructions have been preserved binary level. instructions added Z380 include:
Less restricted operand source/destination combinations. More flexible register exchange instructions. Stack Pointer Relative addressing mode.
1.3.2 Linear Memory Address Space
Z380 architecture Gbytes linear memory address space. architecture allows Kbytes memory addressing space. This more than sufficient when first developed. DC-8297-03
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1.3.3. Enhanced Instruction with 16-Bit 32-Bit Manipulation Capability (Continued)
DDIR (Decoder Directive Instructions) enhance addressing capability cover Gbytes memory space, well data manipulation capability. Jump relative/Call relative instructions with 8-bit, 16-bit, 24-bit displacement. Full complements 16-bit arithmetic instructions. 32-bit manipulate instructions address manipulation.
register pairs (including each register's Extended portion). When doing context switching, exceptional condition (trap interrupts) subroutine/procedure calls, save contents registers currently use, along with current status. Traditionally architecture, this done saving contents register into memory, usually using push/pop instructions auxiliary register file. Register contents then restored when process finished. With Z380 CPU's multiple register banks, saving contents working register currently just matter instruction change field Select Register, which allows fast context switching.
These instructions help compact code, well shorten program's overall execution speed. details this subject, refer Chapter "Instruction Set."
1.3.4 Faster Context Switching
Z380 architecture allows multiple sets register banks AF/AF', BC/DE/HL, BC'/DE'/HL', IX/IX', IY/IY'
SUMMARY
Z380 high-performance 16-bit Central Processing Unit Superintegrationcore. Code-compatible with CPU, Z380 architecture been expanded include features such multiple register banks, Gbytes linear memory addressing space, efficient handling nested interrupts. benefits this architecture, including high throughput rates, code density, compiler efficiency, greatly enhance power versatility Z380 CPU. Thus, Z380 provides both growth path existing Z80-based designs powerful processor applications products developed around this core.
1994, 1995, 1996, 1997 Zilog, Inc. rights reserved. part this document copied reproduced form means without prior written consent Zilog, Inc. information this document subject change without notice. Devices sold Zilog, Inc. covered warranty patent indemnification provisions appearing Zilog, Inc. Terms Conditions Sale only. ZILOG, INC. MAKES WARRANTY, EXPRESS, STATUTORY, IMPLIED DESCRIPTION, REGARDING INFORMATION FORTH HEREIN REGARDING FREEDOM DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT. ZILOG, INC. MAKES WARRANTY MERCHANTABILITY FITNESS PURPOSE. Zilog, Inc. shall responsible errors that appear this document. Zilog, Inc. makes commitment update keep current information contained this document.
Zilog's products authorized critical components life support devices systems unless specific written agreement pertaining such intended executed between customer Zilog prior use. Life support devices systems those which intended surgical implantation into body, which sustains life whose failure perform, when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. Zilog, Inc. East Hacienda Ave. Campbell, 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 370-8056 Internet: http://www.zilog.com
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Z380USER'S MANUAL
USER's MANUAL
CHAPTER
ADDRESS SPACES
INTRODUCTION
Z380 supports five address spaces corresponding different types locations that addressed method which logical addresses formed. These five address spaces are:
External Address Space. This consists external ports addresses through which peripheral devices accessed. On-Chip Address Space. This consists internal port addresses through which peripheral devices accessed. Also, this addressing space contains registers control functionality device, giving status information.
Register Space. This consists register addresses register file. Control Register Space. This consists Select Register (SR). Memory Address Space. This consists addresses locations main memory.
REGISTER SPACE
Z380 register file illustrated Figure 2-1. Note that this figure shows configuration register Z380 CPU, number register files vary future Superintegration devices. Z380 contains abundant register resources. given time, program immediate access both primary alternate registers selected register set. Changing register sets simple matter LDCTL instruction program Select Register (SR). register file divided into five groups registers apostrophe indicates register auxiliary registers).
Four sets Index registers (IX, IX', IY') Stack Pointer (SP) Program Counter, Interrupt register, Refresh register (PC,
Register addresses either specified explicitly instruction implied semantics instruction.
Four sets Flag Accumulator registers Four sets Primary Working registers
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REGISTER SPACE (Continued)
Sets Registers IXU' IYU' IXL' IYL'
BCz' DEz' HLz' IXz' IYz'
Figure 2-1. Register File Organization (Z380 MPU)
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2.2.1 Primary Working Registers
working register divided into register files: primary file alternate file (designated prime (`)). Each file contains 8-bit accumulator (A), Flag register (F), 8-bit general-purpose registers with their Extended registers. Only file active given time, although data inactive file still accessed using instructions byte-wide registers, instructions register pairs (either 16-bit 32-bit wide depending status). Exchange instructions allow programmer exchange active file with inactive file. AF', EXX, EXALL instructions changes register files use. Upon reset, primary register file register active. Changing register sets simple matter LDCTL instruction program accumulator destination register 8-bit arithmetic logical operations. general-purpose registers paired (BC, HL), extended bits extension register (with suffix "z"; BCz/DEz/HLz), form three 32-bit general-purpose registers. register serves 16-bit 32-bit accumulator word operations. Access Extended portion registers possible using SWAP instruction word Load instructions Long Word operation mode. Flag register contains eight status flags. Four individually used control program branching, used support decimal arithmetic, reserved. These flags reset various operations. details Flag operations, refer Section 5.2, "Flag Register." registers, IYU, IYU', IYL, IYL' registers. Selection primary auxiliary Index registers made EXXX, EXXY, EXALL instructions, programming Upon reset, primary registers register active. Changing register sets simple matter LDCTL instruction program
2.2.3. Interrupt Register
Interrupt register used interrupt modes /INT0 generate 32-bit indirect address interrupt service routine. register supplies upper bits indirect address interrupting peripheral supplies lower eight bits. Assigned Vectors mode /INT3-/INT1, upper bits vector supplied register; bits 15-9 supplied from Assigned Vector Base register, bits assigned vector unique each /INT3-/INT1.
2.2.4. Program Counter
Program Counter (PC) used sequence through instructions currently executing program generate relative addresses. contains 32-bit address current instruction being fetched from memory. Native mode, effectively only bits long, since upper word [PC31-PC16] forced zero, when carried from (Lower word [PC15-PC0] Upper word [PC31-PC16]) inhibited this mode. Extended mode, allowed increment across bits.
2.2.5. Register 2.2.2. Index Registers
four index registers, IX', IY', extended bits extension register (with suffix "z"; IXz/IYz), form 32-bit index registers. access Extended portion registers SWAP instruction word Load instructions Long Word operation mode. These Index registers hold 32-bit base address that used Index addressing mode. Only register each active given time, although data inactive file still accessed using (either 16-bit 32-bit wide depending status). Index registers also function general-purpose registers with upper lower bytes lower bits being accessed individually. These byte registers called IXU, IXU', IXL, IXL' register used general-purpose 8-bit read/write register. register associated with refresh controller contents changed only user.
2.2.6. Stack Pointer
Stack Pointer (SP) used saving information when interrupt trap occurs supporting subroutine calls returns. Stack Pointer relative addressing allows parameter passing using bits wide, extended register bits wide.
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2.2.6 Stack Pointer (Continued)
Increment/decrement Stack Pointer affected modes operation (Native Extended). Native mode, stack operates modulo 216, Extended mode, operates modulo 232. example, holds 0001FFFEH, does Word size operation. After operation, holds 00010000H Native mode, 00020000H Extended mode. either case, programmed Stack frame. This done Load- to-Stack pointer instructions Long Word mode.
2.3. CONTROL REGISTER SPACE
control register space consists 32-bit Select Register (SR). accessed whole upper three bytes accessed individually YSR, XSR, DSR. addition, these upper three bytes loaded with same byte value. also PUSHed POPed cleared zeros Reset. details this register, refer Chapter 5.3, "Select Register."
MEMORY ADDRESS SPACE
memory address space viewed string Gbytes numbered consecutively ascending order. 8-bit byte basic addressable element Z380 memory address space. However, there other addressable data elements: bits, 2-byte words, byte strings, 4-byte words. size data element being addressed depends instruction being executed well Word/Long Word mode. addressed specifying byte within that byte. Bits numbered from right left, with least significant being illustrated Figure 2-2. address multiple-byte entity same address byte with lowest memory address entity. Multiple-byte entities stored beginning with either even memory addresses. word (either 2byte 4-byte entity) aligned address even; otherwise unaligned. Multiple transactions, which required access multiple-byte entities, minimized alignment maintained. format multiple-byte data types also shown Figure 2-2. Note that when word stored memory, least significant byte precedes more significant byte word, architecture. Also, loweraddressed byte present upper byte external data bus.
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Z380USER'S MANUAL
Bits within byte:
16-bit word address Least Significant Byte Most Significant Byte Address Address
32-bit word address D7-0 (Least Significant Byte) D15-8 D23-16 D31-24 (Most Significant Byte) Address Address Address Address
Memory addresses: Even address (A0=0) Least Significant Byte
address (A0=1) Most Significant Byte
Figure 2-2. Bit/Byte Ordering Conventions
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2.5. EXTERNAL ADDRESS SPACE
External address space Gbytes size External addresses generated instructions except those reserved on-chip address space accesses. take variety forms, shown Table 2.1. external read write always transaction, regardless size type instruction.
Table 2-1. Addressing Options Instruction dst,(C) INA(W) dst,(mn) DDIR INA(W) dst,(lmn) DDIR INA(W) dst,(klmn) Block Input (n),A (C),dst OUTA(W) (mn),dst DDIR OUTA(W) (lmn),dst DDIR OUTA(W) (klmn),dst Block Output A31-A24 00000000 BC31-B24 00000000 00000000 BC31-B24 00000000 BC31-B24 00000000 00000000 BC31-B24 A23-A16 Address A15-A8 A7-A0 BC15-B8 BC15-B8 A7-A0 BC15-B8 BC15-B8 A7-A0 BC7-B0 BC7-B0 BC7-B0 BC7-B0
00000000 BC23-B16 00000000 BC23-B16 00000000 BC23-B16 00000000 BC23-B16
2.6. ON-CHIP ADDRESS SPACE
Z380 on-chip address space control on-chip peripheral functions Superintegrationversion devices. portion interrupt functions also controlled several on-chip registers, which occupy on-chip address space. This on-chip address space accessed only with following reserved on-chip instructions which identical Z180 original instructions access Page addressing area. OUT0 TSTIO R,(n) (n),R OTIM OTIMR OTDM OTDMR Register Name Interrupt Enable Register Assigned Vector Base Register Trap Break Register Chip Version Register Internal Address 0FFH
Chip Version register returns byte data, which indicates version CPU, specific implementation Z380 based Superintegration device. Currently, value assigned Z380 MPU, other values reserved. other three registers, refer Chapter "Interrupts Traps." Also, Z380 registers control chip selects, refresh, waits, clock divide Internal address 10H. these registers, refer Z380 Product specification (DC-3003-01).
When these instructions executed, Z380 outputs register address being accessed pseudo-transaction BUSCLK cycles duration, with address signals A31-A8 zero. pseudo-transactions, control signals their inactive state. following four registers assigned this addressing space part Z380 core:
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1994, 1995, 1996, 1997 Zilog, Inc. rights reserved. part this document copied reproduced form means without prior written consent Zilog, Inc. information this document subject change without notice. Devices sold Zilog, Inc. covered warranty patent indemnification provisions appearing Zilog, Inc. Terms Conditions Sale only. ZILOG, INC. MAKES WARRANTY, EXPRESS, STATUTORY, IMPLIED DESCRIPTION, REGARDING INFORMATION FORTH HEREIN REGARDING FREEDOM DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT. ZILOG, INC. MAKES WARRANTY MERCHANTABILITY FITNESS PURPOSE. Zilog, Inc. shall responsible errors that appear this document. Zilog, Inc. makes commitment update keep current information contained this document.
Z380USER'S MANUAL
Zilog's products authorized critical components life support devices systems unless specific written agreement pertaining such intended executed between customer Zilog prior use. Life support devices systems those which intended surgical implantation into body, which sustains life whose failure perform, when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. Zilog, Inc. East Hacienda Ave. Campbell, 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 370-8056 Internet: http://www.zilog.com
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ZILOG
Z380USER'S MANUAL
USER's MANUAL
CHAPTER
ADDRESS SPACES
INTRODUCTION
Z380 supports five address spaces corresponding different types locations that addressed method which logical addresses formed. These five address spaces are:
External Address Space. This consists external ports addresses through which peripheral devices accessed. On-Chip Address Space. This consists internal port addresses through which peripheral devices accessed. Also, this addressing space contains registers control functionality device, giving status information.
Register Space. This consists register addresses register file. Control Register Space. This consists Select Register (SR). Memory Address Space. This consists addresses locations main memory.
REGISTER SPACE
Z380 register file illustrated Figure 2-1. Note that this figure shows configuration register Z380 CPU, number register files vary future Superintegration devices. Z380 contains abundant register resources. given time, program immediate access both primary alternate registers selected register set. Changing register sets simple matter LDCTL instruction program Select Register (SR). register file divided into five groups registers apostrophe indicates register auxiliary registers).
Four sets Index registers (IX, IX', IY') Stack Pointer (SP) Program Counter, Interrupt register, Refresh register (PC,
Register addresses either specified explicitly instruction implied semantics instruction.
Four sets Flag Accumulator registers Four sets Primary Working registers
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REGISTER SPACE (Continued)
Sets Registers IXU' IYU' IXL' IYL'
BCz' DEz' HLz' IXz' IYz'
Figure 2-1. Register File Organization (Z380 MPU)
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2.2.1 Primary Working Registers
working register divided into register files: primary file alternate file (designated prime (`)). Each file contains 8-bit accumulator (A), Flag register (F), 8-bit general-purpose registers with their Extended registers. Only file active given time, although data inactive file still accessed using instructions byte-wide registers, instructions register pairs (either 16-bit 32-bit wide depending status). Exchange instructions allow programmer exchange active file with inactive file. AF', EXX, EXALL instructions changes register files use. Upon reset, primary register file register active. Changing register sets simple matter LDCTL instruction program accumulator destination register 8-bit arithmetic logical operations. general-purpose registers paired (BC, HL), extended bits extension register (with suffix "z"; BCz/DEz/HLz), form three 32-bit general-purpose registers. register serves 16-bit 32-bit accumulator word operations. Access Extended portion registers possible using SWAP instruction word Load instructions Long Word operation mode. Flag register contains eight status flags. Four individually used control program branching, used support decimal arithmetic, reserved. These flags reset various operations. details Flag operations, refer Section 5.2, "Flag Register." registers, IYU, IYU', IYL, IYL' registers. Selection primary auxiliary Index registers made EXXX, EXXY, EXALL instructions, programming Upon reset, primary registers register active. Changing register sets simple matter LDCTL instruction program
2.2.3. Interrupt Register
Interrupt register used interrupt modes /INT0 generate 32-bit indirect address interrupt service routine. register supplies upper bits indirect address interrupting peripheral supplies lower eight bits. Assigned Vectors mode /INT3-/INT1, upper bits vector supplied register; bits 15-9 supplied from Assigned Vector Base register, bits assigned vector unique each /INT3-/INT1.
2.2.4. Program Counter
Program Counter (PC) used sequence through instructions currently executing program generate relative addresses. contains 32-bit address current instruction being fetched from memory. Native mode, effectively only bits long, since upper word [PC31-PC16] forced zero, when carried from (Lower word [PC15-PC0] Upper word [PC31-PC16]) inhibited this mode. Extended mode, allowed increment across bits.
2.2.5. Register 2.2.2. Index Registers
four index registers, IX', IY', extended bits extension register (with suffix "z"; IXz/IYz), form 32-bit index registers. access Extended portion registers SWAP instruction word Load instructions Long Word operation mode. These Index registers hold 32-bit base address that used Index addressing mode. Only register each active given time, although data inactive file still accessed using (either 16-bit 32-bit wide depending status). Index registers also function general-purpose registers with upper lower bytes lower bits being accessed individually. These byte registers called IXU, IXU', IXL, IXL' register used general-purpose 8-bit read/write register. register associated with refresh controller contents changed only user.
2.2.6. Stack Pointer
Stack Pointer (SP) used saving information when interrupt trap occurs supporting subroutine calls returns. Stack Pointer relative addressing allows parameter passing using bits wide, extended register bits wide.
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2.2.6 Stack Pointer (Continued)
Increment/decrement Stack Pointer affected modes operation (Native Extended). Native mode, stack operates modulo 216, Extended mode, operates modulo 232. example, holds 0001FFFEH, does Word size operation. After operation, holds 00010000H Native mode, 00020000H Extended mode. either case, programmed Stack frame. This done Load- to-Stack pointer instructions Long Word mode.
2.3. CONTROL REGISTER SPACE
control register space consists 32-bit Select Register (SR). accessed whole upper three bytes accessed individually YSR, XSR, DSR. addition, these upper three bytes loaded with same byte value. also PUSHed POPed cleared zeros Reset. details this register, refer Chapter 5.3, "Select Register."
MEMORY ADDRESS SPACE
memory address space viewed string Gbytes numbered consecutively ascending order. 8-bit byte basic addressable element Z380 memory address space. However, there other addressable data elements: bits, 2-byte words, byte strings, 4-byte words. size data element being addressed depends instruction being executed well Word/Long Word mode. addressed specifying byte within that byte. Bits numbered from right left, with least significant being illustrated Figure 2-2. address multiple-byte entity same address byte with lowest memory address entity. Multiple-byte entities stored beginning with either even memory addresses. word (either 2byte 4-byte entity) aligned address even; otherwise unaligned. Multiple transactions, which required access multiple-byte entities, minimized alignment maintained. format multiple-byte data types also shown Figure 2-2. Note that when word stored memory, least significant byte precedes more significant byte word, architecture. Also, loweraddressed byte present upper byte external data bus.
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Bits within byte:
16-bit word address Least Significant Byte Most Significant Byte Address Address
32-bit word address D7-0 (Least Significant Byte) D15-8 D23-16 D31-24 (Most Significant Byte) Address Address Address Address
Memory addresses: Even address (A0=0) Least Significant Byte
address (A0=1) Most Significant Byte
Figure 2-2. Bit/Byte Ordering Conventions
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2.5. EXTERNAL ADDRESS SPACE
External address space Gbytes size External addresses generated instructions except those reserved on-chip address space accesses. take variety forms, shown Table 2.1. external read write always transaction, regardless size type instruction.
Table 2-1. Addressing Options Instruction dst,(C) INA(W) dst,(mn) DDIR INA(W) dst,(lmn) DDIR INA(W) dst,(klmn) Block Input (n),A (C),dst OUTA(W) (mn),dst DDIR OUTA(W) (lmn),dst DDIR OUTA(W) (klmn),dst Block Output A31-A24 00000000 BC31-B24 00000000 00000000 BC31-B24 00000000 BC31-B24 00000000 00000000 BC31-B24 A23-A16 Address A15-A8 A7-A0 BC15-B8 BC15-B8 A7-A0 BC15-B8 BC15-B8 A7-A0 BC7-B0 BC7-B0 BC7-B0 BC7-B0
00000000 BC23-B16 00000000 BC23-B16 00000000 BC23-B16 00000000 BC23-B16
2.6. ON-CHIP ADDRESS SPACE
Z380 on-chip address space control on-chip peripheral functions Superintegrationversion devices. portion interrupt functions also controlled several on-chip registers, which occupy on-chip address space. This on-chip address space accessed only with following reserved on-chip instructions which identical Z180 original instructions access Page addressing area. OUT0 TSTIO R,(n) (n),R OTIM OTIMR OTDM OTDMR Register Name Interrupt Enable Register Assigned Vector Base Register Trap Break Register Chip Version Register Internal Address 0FFH
Chip Version register returns byte data, which indicates version CPU, specific implementation Z380 based Superintegration device. Currently, value assigned Z380 MPU, other values reserved. other three registers, refer Chapter "Interrupts Traps." Also, Z380 registers control chip selects, refresh, waits, clock divide Internal address 10H. these registers, refer Z380 Product specification (DC-3003-01).
When these instructions executed, Z380 outputs register address being accessed pseudo-transaction BUSCLK cycles duration, with address signals A31-A8 zero. pseudo-transactions, control signals their inactive state. following four registers assigned this addressing space part Z380 core:
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1994, 1995, 1996, 1997 Zilog, Inc. rights reserved. part this document copied reproduced form means without prior written consent Zilog, Inc. information this document subject change without notice. Devices sold Zilog, Inc. covered warranty patent indemnification provisions appearing Zilog, Inc. Terms Conditions Sale only. ZILOG, INC. MAKES WARRANTY, EXPRESS, STATUTORY, IMPLIED DESCRIPTION, REGARDING INFORMATION FORTH HEREIN REGARDING FREEDOM DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT. ZILOG, INC. MAKES WARRANTY MERCHANTABILITY FITNESS PURPOSE. Zilog, Inc. shall responsible errors that appear this document. Zilog, Inc. makes commitment update keep current information contained this document.
Z380USER'S MANUAL
Zilog's products authorized critical components life support devices systems unless specific written agreement pertaining such intended executed between customer Zilog prior use. Life support devices systems those which intended surgical implantation into body, which sustains life whose failure perform, when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. Zilog, Inc. East Hacienda Ave. Campbell, 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 370-8056 Internet: http://www.zilog.com
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Z380USER'S MANUAL
USER's MANUAL
CHAPTER
NATIVE EXTENDED MODE, WORD/LONG WORD MODE OPERATIONS DECODER DIRECTIONS
INTRODUCTION
Z380CPU architecture allows access Gbytes (232) memory addressing space, locations I/O. offers 16/32-bit manipulation capability while maintaining object-code compatibility with CPU. order implement these capabilities instruction sets, modes operation address manipulation (Native Extended mode), modes operation data manipulation (Word Long Word mode), special Decoder Directives. Reset, Z380 defaults Native mode Word mode. this condition, behaves exactly same CPU, even though access entire Gbytes memory data access locations space, access newly added registers which includes Extended registers register banks, capability executing Z380 instructions. described below, Z380 switched between Word mode Long Word mode during operation through SETC RESC instructions, Decoder Directives. Native Extended modes exception- defaults Native mode, Extended mode instruction. Only Reset return Native mode. Figure illustrates relationship between these modes operation.
Z380 Native Word Long Word Extended
Native Mode
Figure 3-1. Z380CPU Operation Modes
instructions which work with DDIR instructions, refer Appendix
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DECODER DIRECTIVES
Decoder Directive instruction, rather directive instruction decoder. instruction decoder directed fetch additional byte word immediate data address with instruction, well tagging instruction execution either Word Long Word mode. Since architecture's addressing convention memory "least significant byte first, followed more significant bytes," possible have such instructions direct instruction decoder fetch additional byte(s) address information immediate data extend instruction. eight combinations options supported, shown below. Instructions which support decoder directives assembled instruction decoder decoder directive were present.
decoder directive causes decoder fetch additional byte immediately after existing immediate data direct address, front trailing opcode bytes (with instructions starting with DD-CB FD-CB, example). Likewise, decoder directive causes decoder fetch additional word immediately after existing immediate data direct address, front trailing opcode bytes. Byte ordering within instruction follows usual convention; least significant byte first, followed more significant bytes. More-significant immediate data direct address bytes specified instruction read zeros processor. decoder directive causes instruction decoder instruction execution Word mode. This useful while Long Word (LW) Select Register (SR) set, 16-bit data manipulation required this instruction. decoder directive causes instruction decoder instruction execution Long Word mode. This useful while cleared, 32bit data manipulation required this instruction.
DDIR DDIR IB,W DDIR IW,W DDIR DDIR DDIR IB,LW DDIR IW,LW DDIR
Word mode Immediate byte, Word mode Immediate Word, Word mode Immediate byte Long Word mode Immediate byte, Long Word mode Immediate Word, Long Word mode Immediate Word
NATIVE MODE EXTENDED MODE
Z380 operate either Native Extended mode, manipulate addresses. Native mode (the Reset configuration), Program Counter only increments across bits, stack Push operations manipulate 16-bit quantities (two bytes). Thus, Native mode fully compatible with CPU's Kbyte address space programming model. extended portion Program Counter (PC31PC15) forced program address location next 0000FFFFH 00000000H this mode. This means Native mode, program have reside within first Kbytes memory addressing space. Extended mode, however, increments across bits stack Push operations manipulate 32-bit quantities. Thus, Extended mode allows access entire Gbyte address space. both Native Extended modes, Z380 drives bits address onto external address bus; only increments stack operations distinguish Native from Extended mode. Note that regardless Native Extended mode, 32-bit address always used data access. Thus, data reference, complete Gbytes memory area accessed. example: (HL)
uses 32-bit address value stored HL31-HL0 (HLz source location address. However, Reset, HL31-HL16 portion (HLz) initializes 00H. Unless modified other than 00H, operation this instruction identical with CPU. Modifying extended portion register done either using 32-bit load instruction Long Word mode, with DDIR instructions), using 16-bit load instruction with SWAP instructions.
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Z380USER'S MANUAL Once Extended mode, only Reset return Native mode. Reset, Z380 Native mode. Refer Sections more examples.
WORD LONG WORD MODE OPERATION
Z380 operate either Word Long Word mode. Word mode (the Reset configuration), word operations manipulate 16-bit quantities, compatible with 16-bit operations. Long Word mode, word operations manipulate 32-bit quantities. Note that Native/Extended Word/Long Word selections independent another, Word/Long Word pertains data operand address manipulation only. Z380 implements instructions decoder directives allow switching between these modes; SETC (Set Long Word) RESC (Reset Long Word) perform global switch, while DDIR DDIR decoder directives that select particular mode only instruction that they precede. Examples: Effect Word mode Long Word mode DDIR (HL) Loads BC15-BC0 from location (HL) (HL+1), (BC31-BC16) remains unchanged. DDIR (HL) Loads BC31-BC0 from locations (HL) (HL+3). Loads 00001234H into HL31-HL0. 0000H appended HL31-HL16 portion. Immediate data load with DDIR instructions DDIR IW,LW HL,12345678H Loads 12345678H into HL31-HL0. DDIR IB,LW HL,123456H Loads 00123456H into HL31-HL0. appended Most significant byte HL31-HL24. DDIR HL,1234H
1994, 1995, 1996, 1997 Zilog, Inc. rights reserved. part this document copied reproduced form means without prior written consent Zilog, Inc. information this document subject change without notice. Devices sold Zilog, Inc. covered warranty patent indemnification provisions appearing Zilog, Inc. Terms Conditions Sale only. ZILOG, INC. MAKES WARRANTY, EXPRESS, STATUTORY, IMPLIED DESCRIPTION, REGARDING INFORMATION FORTH HEREIN REGARDING FREEDOM DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT. ZILOG, INC. MAKES WARRANTY MERCHANTABILITY FITNESS PURPOSE. Zilog, Inc. shall responsible errors that appear this document. Zilog, Inc. makes commitment update keep current information contained this document.
Zilog's products authorized critical components life support devices systems unless specific written agreement pertaining such intended executed between customer Zilog prior use. Life support devices systems those which intended surgical implantation into body, which sustains life whose failure perform, when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. Zilog, Inc. East Hacienda Ave. Campbell, 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 370-8056 Internet: http://www.zilog.com
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USER's MANUAL
CHAPTER
ADDRESSING MODES DATA TYPES
INSTRUCTION
instruction consecutive list more bytes memory. Most instructions upon some data; term operand refers data operated upon. Z380CPU instructions, operands reside registers, memory locations, ports (internal external). method used designate location operands instruction called addressing modes. Z380 supports seven addressing modes; Register, Immediate, Indirect Register, Direct Address, Indexed, Program Counter Relative Address, Stack Pointer Relative. wide variety data types accessed using these addressing modes.
ADDRESSING MODE DESCRIPTIONS
following pages contain descriptions addressing modes Z380 CPU. Each description explains operand's location calculated, indicates which address spaces accessed with that particular addressing mode, gives example instruction using that mode, illustrating assembly language format addressing modes. Example mode: Load register Word mode. DDIR ;Next instruction Word mode BC,HL ;Load contents into Before instruction execution After instruction execution 1234 1234 5678 DEF0
9ABC DEF0 9ABC DEF0
4.2.1 Register
When this addressing mode used, instruction processes data taken from 8-bit registers IXU, IXL, IYU, IYL, 16-bit registers special byte registers Storing data register allows shorter instructions faster execution that occur with instructions that access memory. Instruction OPERATION
Load register Long Word mode. DDIR ;Next instruction Long Word mode BC,HL ;Load contents into Before instruction execution After instruction execution 1234 5678
9ABC DEF0 9ABC DEF0
9ABC DEF0
REGISTER
OPERAND
4.2.2 Immediate (IM)
When Immediate addressing mode used, data processed instruction. Immediate addressing mode only mode that does indicate register memory address source operand.
operand value contents register. operand always register address space. register length (byte word) specified instruction opcode. case Long Word register operation, specified either through SETC instruction DDIR decoder directive.
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4.2.2 Immediate (IM) (Continued)
Instruction OPERATION OPERAND operand value instruction 123456H Immediate mode often used initialize registers. Also, this addressing mode affected DDIR Immediate Data Directives expand immediate value bits bits. Example mode: Load immediate value into accumulator A,55H ;Load into accumulator. Load 24-bit register DDIR immediate value into
;next instruction Long Word mode, with additional immediate data ;load HLz, with constant 123456H
This case, Z380 appends byte. 0987 0012 6543 3456
Before instruction execution After instruction execution
Before instruction execution After instruction execution
4.2.3 Indirect Register (IR)
Indirect Register addressing mode, register specified instruction holds address operand. Memory Instruction OPERATION data processed location specified register (depending instruction) memory accesses, register I/O.
REGISTER
Register Address
Port OPERAND
operand value contents location whose address register.
Depending instruction, operand specified mode located either address space (I/O instruction) memory address space (all other instructions). Indirect Register mode save space reduce execution time when consecutive locations referenced location repeatedly accessed. This mode also used simulate more complex addressing modes, since addresses computed before data accessed. address this mode always treated 32-bit mode. After reset, contents extend registers (registers with suffix) initialized 0's; hence, these instructions will executed just Z80/Z180.
Example mode: Load accumulator from contents memory pointed (HL) (HL) ;Load accumulator with data ;addressed contents Before instruction execution After instruction execution Memory location HLz,HL 12345678 12345678
12345678
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Z380USER'S MANUAL Depending instruction, operand specified mode either address space (I/O instruction) memory address space (all other instructions). This mode also used Jump Call instructions specify address next instruction executed. (The address serves immediate value that loaded into program counter.) Also, DDIR Immediate Data Directives used expand direct address bits. Operand width affected status load exchange instructions.
4.2.4 Direct Address (DA)
When Direct Address mode used, data processed location whose memory port address instruction. Instruction OPERATION ADDRESS Memory Port OPERAND
operand value contents location whose address instruction.
Example mode: Load register from memory location 00005E22H Word mode (5E22H) ;Load with data address ;00005E22H 1234 0301 00005E22 00005E23
Before instruction execution After instruction execution Memory location
Load register from memory location 12345E22H Word mode DDIR ;extend direct address word (12345E22H) ;Load with data address ;12345E22H 1234 0301 12345E22 12345E23
Before instruction execution After instruction execution Memory location
Load register from memory location 12345E22H Long Word mode DDIR IW,LW ;extend direct address word, ;and operation Long Word (12345E22H) ;Load with data address ;12345E22H 1234 0705 5678 0301
Before instruction execution After instruction execution Memory location
12345E22 12345E23 12345E24 12345E25
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4.2.5 Indexed
When Indexed addressing mode used, data processed location whose address contents use, offset 8-bit signed displacement instruction. Indexed address computed adding 8-bit two's complement signed displacement specified instruction contents register use, also specified instruction. Indexed addressing allows random access tables other complex data structures where address base table known, particular element index must computed program. offset portion expanded bits, instead eight bits using DDIR Immediate Data Directives (DDIR 16-bit offset, DDIR 24-bit offset). Note that computation effective address affected operation mode (Native Extended). Native mode, address computation done modulo 216, Extended mode, address computation done modulo 232.
Instruction REGISTER OPERATION REGISTER ADDRESS OPERAND DISPLACEMENT Example mode: Load accumulator from location (IX-1) Native mode (IX-1) ;Load into accumulator ;contents memory location ;whose address less than ;the contents ;Assume Native mode 0001FFFF 0001 0001 0000 0000
MEMORY
Before instruction execution After instruction execution Memory location
Address calculation: Native mode, 0FFH encoding instruction sign extended 16-bit value before address calculation, calculation done modulo does take into account index register's extended portion.
0000 FFFF FFFF
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Z380USER'S MANUAL
Before instruction execution After instruction execution Memory location
Address calculation: Extended mode, 0FFH encoding instruction sign extended 32-bit value before address calculation, calculation done modulo takes into account index register's extended portion.
00010000 FFFFFFFF 0000FFFF
4.2.6 Program Counter Relative Mode (RA)
Program Counter Relative Addressing mode used certain program control instructions specify address next instruction executed (specifically, Program Counter value displacement value loaded into Program Counter). Relative addressing allows reference forward backward from current Program Counter value; used program control instructions such Jumps Calls that access constants memory. displacement, 8-bit, 16-bit, 24-bit value used. address loaded into Program Counter computed adding two's complement signed displacement specified instruction current Program Counter. Also, Native mode, Instruction OPERATION ADDRESS DISPLACEMENT MEMORY OPERAND Note that computation effective address affected mode operation (Native Extended). Native mode, address computation done modulo 216, Extend (PC31-PC16) forced will affect this portion. Extended mode, address computation done modulo 232, will affect contents extend there carry borrow operation.
Example mode: Jump relative Native mode, 8-bit displacement ;Jumps location ;(Current value) ;'$' represents current value ;This instruction jumps itself. ;since after execution this instruction, points next instruction.
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4.2.6 Program Counter Relative Mode (RA) (Continued)
Before instruction execution After instruction execution 0000 0000 1000 0FFE 1000 FFFE FFFE
Address calculation: Native mode, encoded 0FEH instruction, sign extended 16-bit value before added Program Counter. Calculation done modulo does affect Extended portion Program Counter.
Jump relative Extended mode, 16-bit displacement SETC $-5000H ;Put Extended mode operation ;Jumps location ;(Current value) 5000H stands current value ;This instruction jumps itself. 1959 1958 0807 B80B
Before instruction execution After instruction execution
Address calculation: Since this 4-byte instruction, value after fetch before jump taking place 19590807 00000004 1959080B
displacement portion, -5000H, sign extended 32-bit value before being added Program Counter. Calculation done modulo affects Extended portion Program Counter. 1959080B FFFFB000 1958B80B
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Z380USER'S MANUAL Note that computation effective address affected operation mode (Native Extended). Native mode, address computation done modulo 216, meaning computation done 16-bit does affect upper half portion calculation (wrap around within 16-bit). Extended mode, address computation done modulo 232. Also, size data transfer affected mode bit. Word mode, transfer done bits, Long Word mode, transfer done bits.
4.2.7 Stack Pointer Relative Mode (SR)
Stack Pointer Relative addressing mode, data processed location whose address contents Stack Pointer, offset 8-bit displacement instruction. Stack Pointer Relative address computed adding 8-bit two's complement signed displacement specified instruction contents also specified instruction. Stack Pointer Relative addressing mode used specify data items found stack, such parameters passed procedures. Offset portion expanded bits using DDIR immediate instructions (DDIR 16-bit offset, DDIR 24-bit offset).
Instruction OPERATION DISPLACEMENT
ADDRESS
MEMORY OPERAND
Example mode: Load from location Native mode, Word mode (SP-4) ;Load into from ;contents memory location ;whose address four less than ;the contents ;Assume Native/Word mode.
Before instruction execution After instruction execution Memory location
1234 5678 EFCD AB89 07FF7EFC 07FF7EFD
07FF 07FF
7F00 7F00
Address calculation: Native mode, Decimal) encoding instruction sign extended 16-bit value before address calculation. Calculation done modulo does take into account Stack Pointer's extended portion.
7F00 FFFC 7EFC
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4.2.7 Stack Pointer Relative Mode (SR) (Continued)
Load from location Extended mode, Long Word mode SETC Extended mode DDIR ;operate next instruction Long Word mode (SP-4) ;Load into from ;contents memory location ;whose address four less than ;the contents 1234 5678 EFCD AB89 07FF7F00 FFFFFFFC 07FF7EFC 07FF 07FF 7F00 7F00
Before instruction execution After instruction execution Memory location
07FF7EFC 07FF7EFD 07FF7EFE 07FF7EFF
Address calculation: Extended mode, Decimal) encoding instruction sign extended 32bit value before address calculation, calculation done modulo 232.
Load from location 10000H) Extended mode, Long Word mode SETC Extended mode, DDIR IW,LW ;operate next instruction Long Word mode ;with word immediate data. (SP+10000) ;Load into from ;contents memory location ;whose address 10000H more than ;the contents 1234 5678 EFCD AB89 07FF7F00 00010000 08007F00 07FF 07FF 7F00 7F00
Before instruction execution After instruction execution Memory location
08007F00 08007F01 08007F02 08007F03
Address calculation: Extended mode, 010000H encoding instruction sign extended 32-bit value before address calculation, calculation done modulo 232.
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DATA TYPES
Z380 operate bits, binary-coded decimal (BCD) digits (four bits), bytes (eight bits), words bits bits), byte strings, word strings. Bits registers set, cleared, tested. basic data type byte, which also basic accessible element register, memory, address space. 8-bit load, arithmetic, logical, shift, rotate instructions operate bytes registers memory. Bytes treated logical, signed numeric, unsigned numeric value. Words operated similar manner word load, arithmetic, logical, shift rotate instructions. Operation 2-byte words also supported. Sixteen-bit load arithmetic instructions operate words registers memory; words treated signed unsigned numeric values. reads writes 8-bit 16-bit operations. Also, Z380 architecture supports operation Long Word mode handle 32-bit address manipulation. that purpose, 16-bit wide registers originally have been expanded bits wide, along with support arithmetic instruction needed 32-bit address manipulation. Bits fully supported addressed number within byte (see Figure 2-2). Bits within byte registers memory locations tested, set, cleared. Operation binary-coded decimal (BCD) digits supported Decimal Adjust Accumulator (DAA) Rotate Digit (RLD RRD) instructions. digits stored byte registers memory locations, byte. instruction used after binary addition subtraction numbers. Rotate Digit instructions used shift digit strings memory. Strings 65536 (64K) bytes Byte data Word data manipulated Z380 CPU's block move, block search, block instructions. block move instructions allow strings bytes/words memory moved from location another. Block search instructions provide scanning strings bytes/words memory locate particular value. Block instructions allow strings bytes words transferred between memory peripheral device. Arrays supported Indexed mode (with 8-bit, 16-bit, 24-bit displacement). Stack supported Indexed Stack Pointer Relative addressing modes, special instructions such Call, Return, Push, Pop.
1994, 1995, 1996, 1997 Zilog, Inc. rights reserved. part this document copied reproduced form means without prior written consent Zilog, Inc. information this document subject change without notice. Devices sold Zilog, Inc. covered warranty patent indemnification provisions appearing Zilog, Inc. Terms Conditions Sale only. ZILOG, INC. MAKES WARRANTY, EXPRESS, STATUTORY, IMPLIED DESCRIPTION, REGARDING INFORMATION FORTH HEREIN REGARDING FREEDOM DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT. ZILOG, INC. MAKES WARRANTY MERCHANTABILITY FITNESS PURPOSE. Zilog, Inc. shall responsible errors that appear this document. Zilog, Inc. makes commitment update keep current information contained this document.
Zilog's products authorized critical components life support devices systems unless specific written agreement pertaining such intended executed between customer Zilog prior use. Life support devices systems those which intended surgical implantation into body, which sustains life whose failure perform, when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. Zilog, Inc. East Hacienda Ave. Campbell, 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 370-8056 Internet: http://www.zilog.com
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USER's MANUAL
CHAPTER
INSTRUCTION
INTRODUCTION
Z380CPU instruction superset Z180 MPU; Z380 opcode compatible with CPU/Z180 MPU. Thus, Z80/Z180 program executed Z380 without modification. instruction divided into groups function:
Program Control Group Input Output Operations External Space Input Output Operations Internal Space Control Group Decoder Directives
8-Bit Load/Exchange Group 16/32-Bit Load, Exchange, SWAP Push/Pop Group Block Transfers, Search Group 8-Bit Arithmetic Logic Operations 16/32-Bit Arithmetic Operations 8-Bit Manipulation, Rotate Shift Group 16-Bit Rotates Shifts
This chapter describes instruction Z380 CPU. Flags condition codes discussed relation instruction set. Then, interpretability instructions trap discussed. last part this chapter detailed description each instruction, listed alphabetical order mnemonic. This section intended reference Z380 programmers. entry each instruction contains complete description instruction, including addressing modes, assembly language mnemonics, instruction opcode formats.
PROCESSOR FLAGS
Flag register contains bits status information that cleared operations (Figure 5-1). Four these bits testable P/V, with conditional jump, call, return instructions. flags testable used binary-coded decimal (BCD) arithmetic. Flag register provides link between sequentially executed instructions, that result executing instruction alter flags, resulting value flags used determine operation subsequent instruction. program control instructions, whose operation depends state flags, Jump, Jump Relative, subroutine Call, Call Relative, subroutine Return instructions; these instructions referred conditional instructions.
Figure 5-1. Flag Register
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Z380USER'S MANUAL During Load Accumulator with register instruction, flag loaded with IEF2 flag. details this topic,.refer Chapter "Interrupts Traps." When byte inputted register from device addressed register, flag adjusted indicate parity data.
5.2.1 Carry Flag
Carry flag cleared depending operation being performed. instructions that generate carry subtract instruction generating borrow, Carry flag Carry flag cleared that does generate carry subtract that generates borrow. This saved carry facilitates software routines extended precision arithmetic. multiply instructions Carry flag signal information about precision result. Also, Decimal Adjust Accumulator (DAA) instruction leaves Carry flag carry occurs when adding quantities. rotate instructions, Carry flag used link between least significant most significant bits register memory location. During shift instructions, Carry flag contains last value shifted register memory location. logical instructions Carry flag cleared. Carry flag also complemented with explicit instructions.
5.2.4 Half-Carry Flag
Half-Carry flag cleared depending carry borrow status between bits 8-bit arithmetic operation between bits 16-bit arithmetic operation. This flag used Decimal Adjust Accumulator instruction correct result addition subtraction operation packed data.
5.2.5 Zero Flag
Zero flag result generated execution certain instruction zero. arithmetic logical operations, Zero flag result zero. result zero, Zero flag cleared block search instructions, Zero flag comparison found between value Accumulator memory location pointed contents register pair When testing register memory location, Zero flag contains complemented state tested (i.e., Zero flag tested viceversa). block instructions, result decrements zero, Zero flag otherwise, cleared Also, byte inputs registers from devices addressed register, Zero flag indicate zero byte input.
5.2.2 Add/Subtract Flag
Add/Subtract flag used arithmetic. Since algorithm correcting operations different addition subtraction, this flag used record when subtract last executed, allowing subsequent Decimal Adjust Accumulator instruction perform correctly. discussion instruction further information.
5.2.3 Parity/Overflow Flag (P/V)
This flag particular state depending operation being performed. signed arithmetic, this flag, when indicates that result operation two's complement numbers exceeded largest number, less than smallest number, that represented using two's complement notation. This overflow condition determined examining sign bits operands result. flag also used with logical operations rotate instructions indicate parity result. bits byte counted. total odd, this flag reset indicates parity total even, this flag indicates even parity During block search block transfer instructions, flag monitors state Byte Count register (BC). When decrementing byte counter results zero value, flag cleared otherwise flag
5.2.6 Sign Flag
Sign flag stores state most significant result. When Z380 performs arithmetic operation signed numbers, binary two's complement notation used represent process numeric information. positive number identified most significant bit. negative number identified most significant bit. When inputting byte from device addressed register register, Sign flag indicates either positive negative data.
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Z380USER'S MANUAL Table lists condition code mnemonic, flag setting represents, binary encoding each condition code.
5.2.7 Condition Codes
Carry, Zero, Sign, Parity/Overflow flags used control operation conditional instructions. operation these instructions function state flags. Special mnemonics called condition codes used specify flag setting tested during execution conditional instruction; condition codes encoded into 3-bit field instruction opcode itself.
Table 5-1. Condition codes Condition Codes Jump, Call, Return Instructions Mnemonic Meaning Flag Setting *Abbreviated Condition Codes Jump Relative Call Relative Instructions Mnemonic Meaning Flag Setting Zero Zero Carry Carry Zero* Zero* Carry* Carry* Overflow Parity Overflow Parity Even Sign Plus Sign Minus Binary Code
Binary Code
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SELECT REGISTER
Select Register (SR) controls register selection operating modes Z380 CPU. reserved bits future expansion; they will always read zeros should written with zeros future compatibility. Access this register done using newly added LDCTL instruction. Also, some instructions like EXX, DI/EI change bit(s). shown Figure 5-2.
Reserved
IYBANK
Reserved
IXBANK
Reserved
MAINBANK
IEF1
Figure 5-2. Select Register
5.3.1. Bank Select (IYBANK)
This 2-bit field selects register used registers. This field independently register selection other Z380 registers. Reset selects Bank IY'.
5.3.5. Main Bank Select (MAINBANK)
This 2-bit field selects register used BC', DE', registers. This field independently register selection other Z380 registers. Reset selects Bank these registers.
5.3.2. Register Select (IY')
This controls reports whether currently active register. selected when this cleared, selected when this set. Reset clears this bit, selecting
5.3.6. BC/DE/HL BC'/DE'/HL' Register Select (ALT)
This controls reports whether BC/DE/HL BC'/DE'/ currently active bank registers. BC/DE/HL selected when this cleared, BC'/DE'/HL' selected when this set. Reset clears this bit, selecting BC/DE/HL.
5.3.3. Bank Select (IXBANK)
This 2-bit field selects register used registers. This field independently register selection other Z380 registers. Reset selects Bank IX'.
5.3.7. Extended Mode (XM)
This controls Extended/Native mode selection Z380 CPU. This SETC instruction. This reset software, only Reset. When this set, Z380 Extended mode. Reset clears this bit, Z380 Native mode.
5.3.4. Register Select (IX')
This controls reports whether currently active register. selected when this cleared, selected when this set. Reset clears this bit, selecting
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5.3.8. Long Word Mode (LW)
This controls Long Word/Word mode selection Z380 CPU. This SETC instruction cleared RESC instruction. When this set, Z380 Long Word mode; when this cleared Z380 Word mode. Reset clears this bit. Note that individual Word load exchange instructions executed either Word Long Word mode using DDIR DDIR decoder directives.
5.3.11. Lock (LCK)
This controls Lock/Unlock status Z380 CPU. This SETC instruction cleared RESC instruction. When this set, requests will accepted, providing exclusive access Z380 CPU. When this cleared, Z380 will grant requests normal fashion. Reset clears this bit.
5.3.12. Register Select (AF') 5.3.9. Interrupt Enable Flag (IEF)
This master Interrupt Enable Z380 CPU. This instruction cleared instruction, acknowledgment interrupt request. When this set, interrupts enabled; when this cleared, interrupts disabled. Reset clears this bit. This controls reports whether currently active pair registers. selected when this cleared, selected when this set. Reset clears this bit, selecting
5.3.10. Interrupt Mode (IM)
This 2-bit field controls interrupt mode /INT0 interrupt request. These bits controlled instructions Reset clears both these bits, selecting Interrupt Mode
INSTRUCTION EXECUTION EXCEPTIONS
Three types exception conditions-interrupts, trap, Reset-can alter normal flow program execution. Interrupts asynchronous events generated device external CPU; peripheral devices interrupts request service from CPU. Trap synchronous event generated internally executing undefined instructions. Reset asynchronous event generated outside circuits. terminates current activities puts into known state. Interrupts Traps discussed detail Chapter Reset discussed detail Chapter This section examines relationship between instructions exception conditions. instruction. contents repetition counter registers that index into block operands such that, after each iteration, when instruction reissued upon returning from interrupt, effect same instruction were interrupted. This assumes, course, that interrupt handler preserves registers.
5.4.2 Instruction Execution Trap
Z380 generates Trap when undefined opcode encountered. action response Trap jump address 00000000H with status bit(s) set. This response similar Z180 MPU's action execution undefined instruction. Trap enabled immediately after reset, maskable. This feature used increase software reliability implement "extended" instructions. undefined opcode fetched from instruction stream, returned vector interrupt acknowledge transaction Interrupt mode Since jumps address 00000000H, necessary have Trap handling routine beginning program processing proceed. Otherwise, behaves just like reset CPU. detailed description, refer Chapter
5.4.1 Instruction Execution Interrupts
When receives interrupt request, enabled interrupts that class, interrupt normally processed current instruction. However, block transfer search instructions designed interruptible minimize length time takes respond interrupt. interrupt request received during block move, block search, block instruction, instruction suspended after current iteration. address instruction itself, rather than address following instruction, saved stack, that same instruction executed again when interrupt handler executes interrupt return
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INSTRUCTION FUNCTIONAL GROUPS
This section presents overview Z380 instruction set, arranged functional groups. (See Section explanation notation used Tables through 511). Exchange instruction available swapping contents accumulator with another register with memory, well between registers. Also, exchange instructions available which swap contents register primary register bank auxiliary register bank. instruction this group does affect flags.
5.5.1 8-Bit Load/Exchange Group
This group instructions (Table 5-2) includes load instructions transferring data between byte registers, transferring data between byte register memory, loading immediate data into byte register memory. supported source/destination combinations, refer Table 5-3.
Table 5-2. 8-Bit Load Group Instructions Instruction Name Exchange with Accumulator Exchange Load Accumulator Load Immediate Load Register (Byte) Format A,(HL) r,r' A,src dst,A dst,n (HL),n R,src R,(HL) dst,R (HL),R Note
r=A, Table Table Table Table Table Table Table Table
Table 5-3. 8-Bit Load Group Allowed Source/Destination Combinations Source Dist. (BC) (DE) (HL) (nn) (IX+d) (IY+d) (nn) (BC) (DE) (HL) (IX+d) (IY+d)
Note: supported combinations.
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5.5.2 16-Bit 32-Bit Load, Exchange, SWAP, PUSH/POP Group
This group load, exchange, PUSH/POP instructions (Table 5-4) allows words data (two bytes equal word) transferred between registers memory. exchange instructions (Table 5-5) allow switching between primary alternate register files, exchanging contents register files, exchanging contents addressing register with word stack. possible combinations word exchange instructions, refer Table 5-5. 16-bit 32-bit loads include transfer between registers memory immediate loads registers memory. Push stack instructions also included this group. None these instructions affect flags, except AF'. Table supported source/destination combination 16-bit 32-bit load instructions. transfer size, 16-bit 32-bit, determined status DDIR Decoder Directives. PUSH/POP instructions used save/restore contents register onto stack. used exchange data between procedures, save current register file context switching, manipulate data stack, such return addresses. Supported sources listed Table 5-7. Swap instructions allows swapping contents Word wide register (BC, with Extended portion. These instructions useful manipulate upper word register Word mode. example, when doing data accesses, other than 00000000H-0000FFFFH address range, this instruction "data frame" addresses. This group instructions affected status (Select Register), Decoder Directives which specifies operation mode Word Long Word.
Table 5-4. 16-Bit 32-Bit Load, Exchange, PUSH/POP Group Instructions Instruction Name Exchange Word/Long Word Registers Exchange Byte/Word Registers with Alternate Bank Exchange Register Pair with Alternate Bank Exchange Index Register with Alternate Bank Exchange Registers with Alternate Bank Load Word/Long Word Registers PUSH Swap Contents D31-D16 D15-D0 Format dst,src RR,RR' EXXX EXXY EXALL dst,src dst,src PUSH SWAP Note Table
Table Table Table Table
Table 5-5. Supported Source Destination Combination 16-Bit 32-Bit Exchange Instructions Destination (SP) Source
Note: supported combinations. exchange instructions which designate register destination covered other combinations. These Exchange Word instructions affected Long Word mode.
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5.5.2 16-Bit 32-Bit Load, Exchange, SWAP PUSH/POP Group (Continued)
Table 5-6. Supported Source Destination Combination 16-Bit 32-Bit Load Instructions. Destination (BC) (DE) (HL) (nn) (IX+d) (IY+d) (SP+d) Source mode, means that instruction used with DDIR Immediate instruction. Also, means instruction uses mnemonic "LDW" instead "LD". (nn) (BC) (DE) (HL) (IX+d) (IY+d) (SP+d)
Note: column with character(s) allowed source/destination combinations. combination with means that instruction affected Long Word
Table 5-7. Supported Operand PUSH/POP Instructions PUSH
Note: These PUSH/POP instructions affected Long Word mode operations.
5.5.3 Block Transfer Search Group
This group instructions (Table 5-8) supports block transfer string search functions. Using these instructions, block 65536 bytes byte, Word, Long Word data moved memory, byte string searched until given value found. operations proceed through data either direction. Furthermore, operations repeated automatically while decrementing length counter until reaches zero, they operate storage unit execution with length counter decremented source destination pointer register properly adjusted. latter form useful implementing more complex operations software adding other instructions within loop containing block instructions.
Various Z380 registers dedicated specific functions these instructions-the register counter, DEz/DE HLz/HL registers memory pointers, accumulator holding byte value being sought. repetitive forms these instructions interruptible; this essential since repetition count high 65536. instruction interrupted after interaction, which case address instruction itself, rather than next one, saved stack. contents operand pointer registers, well repetition counter, such that instruction simply reissued after returning from interrupt without visible difference instruction execution. case Word Long Word block transfer instructions, counter value held register decremented four, depending status. Since exiting from these instructions will done when counter value gets count value stored registers
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Z380USER'S MANUAL
5.5.4 8-bit Arithmetic Logical Group
This group instructions (Table 5-9) perform 8-bit arithmetic logical operations. Add, with Carry, Subtract, Subtract with Carry, AND, Exclusive Compare takes input operand from accumulator other from register, from immediate data instruction itself, from memory. memory addressing modes, follows supported-Indirect Register, Indexed, Direct Address-except multiplies, which returns 16-bit result same register multiplying upper lower bytes register pair (BC, SP). Increment Decrement instructions operate data register memory; memory addressing modes supported. These instructions operate only accumulator-Decimal Adjust, Complement, Negate. final instruction this group, Extend Sign, sets flags according computed result. EXTS instruction extends sign leaves result register. Long Word mode, (HL31-HL16) portion also affected. instruction nondestructive instruction. ANDs register source, changes flags according result operation. Both source destination values will preserved.
Compare Decrement Compare, Decrement Repeat CPDR Compare Increment Compare, Increment Repeat CPIR Load Decrement Load Decrement Repeat LDDI Load Increment Load, Increment Repeat LDIR Load Decrement Word/Long Word LDDW Load, Decrement Repeat Word/Long Word LDDRW Load Increment Word/Long Word LDIW Load, Increment Repeat Word/Long Word LDIRW
Table 5-9. Supported Source/Destination 8-Bit Arithmetic Logic Group Instruction Name With Carry (Byte) (Byte) Compare (Byte) Complement Accumulator Decimal Adjust Accumulator Decrement (Byte) Extend Sign (Byte) Increment (Byte) Multiply (Byte) Negate Accumulator Subtract with Carry (Byte) Subtract (Byte) Nondestructive Test Exclusive Format A,src A,src [A,]src [A,]src EXTS [A,]src A,src [A,]src [A,]src src/ (HL) (IX+d) (IY+x)
Note
Note
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5.5.5 16-Bit Arithmetic Operation
This group instructions (Table 5-10) provide 16-bit arithmetic instructions. Add, with Carry, Subtract, Subtract with Carry, AND, Exclusive Compare takes input operand from addressing register other from 16-bit register, from instruction itself; result returned addressing register. 16-bit Increment Decrement instructions operate data found register memory; Indirect Register Direct Address addressing mode used specify memory operand. remaining 16-bit instructions provide general arithmetic capability using register input operands. word Add, Subtract, Compare, signed unsigned Multiply instructions take input operand from register other from 16-bit register, from instruction itself, from memory using Indexed Direct Address addressing mode. 32-bit result multiply returned (HL31-HL0). unsigned divide instruction takes 16-bit dividend from register 16-bit divisor from register, from instruction, memory using Indexed mode. 16-bit quotient returned register 16-bit reminder returned (HL31-HL16). Extend Sign instruction takes contents register delivers 32-bit result registers. Negate instruction negates contents register. Except Increment, Decrement, Extend Sign, instructions this group flags reflect computed result.
Table 5-10. 16-Bit Arithmetic Operation Instruction Name With Carry (Word) (Word) Format HL,src ADCW [HL],src HL,src IX,src IY,src ADDW [HL,]src SP,nn ANDW [HL,]src CPLW [HL] [HL,]src DEC[W] DIVUW [HL,]src EXTSW [HL] INC[W] MULT [HL,]src MULTUW [HL,]src NEGW [HL,]src HL,src SBCW [HL],src HL,(nn) SUBW [HL,]src SP,nn XORW [HL,]src src/ (nn) (IX+d) (IY+d)
Stack Pointer Word Complement Accumulator Compare (Word) Decrement (Word) Divide Unsigned Extend Sign (Word) Increment (Word) Multiply Word Signed Multiply Word Unsigned Negate Accumulator Word Subtract with Carry (Word) Subtract (Word) Subtract from Stack Pointer Exclusive
Note: that instructions with rightmost column affected Extended mode. These operate across bits Modulo address calculation.
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5.5.6 8-Bit Manipulation, Rotate Shift Group
Instructions this group (Table 5-11) test, set, reset bits within bytes, rotate shift byte data position. Bits manipulated specified field within instruction. Rotate optionally concatenate Carry flag byte manipulated. Both left right shifting supported. Right shifts either shift into (logical shifts), replicate sign bits (arithmetic shifts). these instructions, Reset Bit, flags according calculated result; operand register memory location specified Indirect Register Indexed addressing mode. instructions provided manipulating strings digits; these rotate 4-bit quantities memory specified Indirect Register. low-order four bits accumulator used link between rotation successive bytes.
Table 5-11. Set/Reset/Test, Rotate Shift Group Instruction Name Test Reset Rotate Left Rotate Left Accumulator Rotate Left Circular Rotate Left Circular (Accumulator) Rotate Left Digit Rotate Right Rotate Right Accumulator Rotate Right Circular Rotate Right Circular (Accumulator) Rotate Right Digit Shift Left Arithmetic Shift Right Arithmetic Shift Right Logical Format RLCA RRCA (HL) (IX+d) (IY+d)
5.5.7 16-Bit Manipulation, Rotate Shift Group
Instructions this group (Table 5-12) rotate shift word data position. Rotate optionally concatenate Carry flag word manipulated. Both left right shifting supported. Right shifts either shift into (logical shifts), replicate sign bits (arithmetic shifts). operand register pair memory location specified Indirect Register Indexed addressing mode, shown below.
Table 5-12. 16-Bit Rotate Shift Group. Instruction Name Rotate Left Word Rotate Left Circular Word Rotate Right Word Rotate Right Circular Word Shift Left Arithmetic Word Shift Right Arithmetic Word Shift Right Logical Word Format RLCW RRCW SLAW SRAW SRLW Destination (HL) (HL) (IX+d) (IY+d)
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Z380USER'S MANUAL into procedure address stack this manner allows straightforward implementation nested recursive procedures. Call, Jump, Jump Relative unconditional based setting flag. Call Relative (CALR) instructions work just like ordinary Call instructions, with Relative address. 8-bit, 16bit, 24-bit offset value used, that allows call procedure within range -126 +129 bytes (8-bit offset;CALR [cc,]e), -32765 +32770 bytes (16-bit offset; CALR [cc,]ee), -8388604 +8388611 bytes [cc,] eee) supported. These instructions really useful program relocatable programs. Jump available with Indirect Register mode addition Direct Address mode. useful implementing complex control structures such dispatch tables. When using Direct Address mode Jump Call, operand used immediate value that loaded into specify address next instruction executed. conditional Return instruction companion call instruction; condition specified instruction satisfied, loads from stack pops stack. special instruction, Decrement Jump Non-Zero (DJNZ), implements control part basic Pascal loop which implemented instruction. supports 8-bit, 16-bit, 24-bit displacement. Note that Jump Relative, Call Relative, DJNZ instructions modulo Native mode, Extended mode address calculation. possible that Z380 jump unexpected address.
5.5.8 Program Control Group
This group instructions (Table 5-13) affect Program Counter (PC) thereby control program flow. registers memory altered except Stack Pointer Stack, which play significant role procedures interrupts. exception Decrement Jump Non-Zero [DJNZ], which uses register loop counter.) flags also preserved except instructions specifically designed complement Carry flag. Set/Reset Condition flag instructions used with Conditional Jump, conditional Jump Relative, Conditional Call, Conditional Return instructions control program flow. Jump Jump Relative (JR) instructions provide conditional transfer control location processor flags satisfy condition specified instruction. Jump Relative, with 8-bit offset byte instruction that jumps instructions within range -126 +129 bytes from location this instruction. Most conditional jumps programs made locations only bytes away; Jump Relative, with 8-bit offset, exploits this fact improve code compactness efficiency. Jump Relative, with 16-bit offset [cc,]ee), four byte instruction that jumps instructions within range -32765 +32770 bytes from location this instruction, Jump Relative, with 24-bit offset [cc,] eee), five byte instruction that jumps instructions within range -8388604 +8388611 bytes from location this instruction. using these Jump Relative instructions with 16-bit 24-bit offsets allows write relocatable location independent) programs. Call Restart used calling subroutines; current contents pushed onto stack effective address indicated instruction loaded
Table 5-13. Program Control Group Instructions Instruction Name Call Complement Carry Flag Call Relative Decrement Jump Non-zero Jump Jump Relative Return Restart Carry Flag Format CALL cc,dst CALR cc,dst DJNZ cc,dst cc,dst (PC+d) (HL) (IX) (IY)
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Z380USER'S MANUAL contents appear D15-D7. These instructions affect flags. Also, there instructions available which allow specify 16-bit absolute address (with DDIR decoder directives, 24-bit 32-bit address specified) available. These instructions affect flags. remaining instructions this group form powerful complete complement instructions transferring blocks data between ports memory. operation these instructions very similar that block move instructions described earlier, with exception that operand always port whose address remains unchanged while address other operand memory location) incremented decremented.In Word mode transfer, counter (i.e., register) holds number transfers, rather than number bytes transfer memory-to-memory word block transfer. Both byte word forms these instructions available. automatically repeating forms these instructions interruptible, like memory-to-memory transfer. addresses output address dependant instruction, listed Table 2-1.
5.5.9 External Input/Output Instruction Group
This group instructions (Table 5-14) used transferring byte, word, string bytes words between peripheral devices registers memory. Byte port addresses transfer bytes D7-D0 only. These 8bit peripherals 16-bit data environment must connected data line D7-D0. 8-bit data environment, word instructions external peripherals should used; however, on-chip peripherals which external core assigned word device still accessed word instructions. instructions transferring single byte (IN, OUT) transfer data between 8-bit register memory address specified instruction peripheral port specified contents register. instruction sets flags according input data; however, special instructions restricted using accumulator Direct Address mode affect flags. Another variant tests input port specified contents register sets flags without modifying registers memory. instructions transferring single word (INW, OUTW) transfer data between register pair peripheral port specified contents register. Word I/O, contents appear D7-D0
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5.5.9 External Input/Output Instruction Group (Continued)
Table 5-14. External Group Instructions. Instruction Name Input Input Accumulator Input Word-Wide Register Input Byte from Absolute Address Input Word from Absolute Address Input Decrement (Byte) Input Decrement (Word) Input, Decrement, Repeat (Byte) Input, Decrement, Repeat (Word) Input Increment (Byte) Input Increment (Word) Input, Increment, Repeat (Byte) Input, Increment, Repeat (Word) Output Output Accumulator Output from Word-Wide Register Output Byte from Absolute Address Output Word from Absolute Address Output Decrement (Byte) Output Decrement (Word) Output, Decrement, Repeat (Byte) Output, Decrement, Repeat (Word) Output Increment (Byte) Output Increment (Word) Output, Increment, Repeat (Byte) Output, Increment, Repeat (Word) Format dst,(C) A,(n) dst,(C) INAW A,(nn) INAW HL,(nn) INDW INDR INDRW INIW INIR INIRW (C),src (n),A OUTW (C), OUTAW (nn),A OUTAW (nn),HL OUTD OUTDW OTDR OTDRW OUTI OTIW OTIR OTIRW dst=A, dst=BC,
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5.5.10 Internal Instruction Group
This group (Table 5-15) instructions used access on-chip addressing space Z380 CPU. This group consists instructions transferring byte from/ Internal locations registers memory, blocks bytes from memory same size Internal locations initialization purposes. These instructions originally assigned newly added instructions Z180 access Page addressing space. There Internal locations, them byte-wide. When these instructions executed, Z380 outputs register address being accessed pseudo transaction BUSCLK durations cycle, with address signals A31-A8 pseudo transactions, control signals their inactive state. instructions transferring single byte (IN0, OUT0) transfer data between 8-bit register Internal address specified instruction. instruction sets flags according input data; however, special instructions which have destination instruction with Direct Address (IN0 (n)), affect register, alters flags accordingly. Another variant, TSTIO instruction, does logical instruction operand with internal location specified register changes flags without modifying registers memory. remaining instructions this group form powerful complete complement instructions transferring blocks data from memory Internal locations. operation these instructions very similar that block move instructions described earlier, with exception that operand always Internal location whose address also increments decrements automatically, Also, address other operand memory location) incremented decremented. Since Internal space byte-wide, only byte forms these instructions available. Automatically repeating forms these instructions interruptible, like memory-tomemory transfer.
Table 5-15. Internal Instruction Group Instruction Name Input from Internal Location Input from Internal Location(Nondestructive) Test Output Internal Location Output Internal Decrement Output Internal Increment Output Internal I/O, Decrement Repeat Output Internal I/O, Increment Repeat Format dst,(n) TSTIO OUT0 (n),src OTDM OTIM OTDMR OTIMR dst=A,
src=A,
Currently, Z380 core following registers part core: Register Name Interrupt Enable Register Assigned Vector Base Register Trap Register Chip Version Register Internal address 0FFH
Chip Version register returns byte data, which indicates version CPU, specific implementation Z380 based Superintegration device. Currently, value assigned Z380 MPU, other values reserved. other three registers, refer Chapter "Interrupt Trap."
Also, Z380 registers control chip selects, refresh, waits, clock divide Internal address 10H. these register, refer Z380 Product specification.
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Z380USER'S MANUAL into flag register. example, this instruction useful implement recursive program, which uses alternate bank save register first time, saves registers into memory thereafter. Mode Test instructions reports current mode operation, Native/Extended, Word/Long Word, Locked not. This instruction used switch procedures depending mode operation. Load Accumulator from Register instructions used report current interrupt mask status. Load from/to register instructions used initialize register. Load Control register instructions used read/write Status Register, set/reset control instructions set/reset control bits Operation instruction does nothing, used filler, debugging purposes, timing adjustment.
5.5.11 Control Group
instructions this group (Table 5-16) upon control status registers perform other functions that into other instruction groups. These include instructions used returning from interrupt service routine. Return from Nonmaskable Interrupt (RETN) Return from Interrupt (RETI) used Program Counter from stack manipulate Interrupt Enable Flag (IEF1 IEF2), signal reset peripherals family. Disable Enable Interrupt instructions used set/reset interrupt mask. Without mask parameters, disables/enables maskable interrupt globally. With mask data, enables/disables interrupts selectively. HALT SLEEP instructions stop waits event happen, puts system into power save mode. Bank Test instructions reports which register file, primary alternate bank, time, reflect status
Table 5-16. Control Group Instruction Name Bank Test Disable Interrupt Enable Interrupt HALT Interrupt Mode Select Load Accumulator from Register Load Register from Accumulator Load Register from Register Load Register from Register Load Control Mode Test Operation Return from Interrupt Return from Nonmaskable Interrupt Reset Control Control Sleep Format BTEST [mask] [mask] HALT A,src dst,A LD[W] HL,I LD[W] HL,I LDCTL dst,src MTEST RETI RETN RESC SETC
dst=LCK, dst=LCK,
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Z380USER'S MANUAL Table 5-17. Decoder Directive Instructions DDIR DDIR IB,W DDIR IW,W DDIR DDIR DDIR IB,LW DDIR IW,LW DDIR Word Mode Immediate Byte, Word Mode Immediate Word, Word Mode Immediate Byte Long Word Mode Immediate Byte, Long Word Mode Immediate Word, Long Word Mode Immediate Word
5.5.12 Decoder Directives
Decoder Directives (Table 5-17) special instructions expand instruction handle Z380's Gbytes linear memory addressing space. details this instruction, refer Chapter
NOTATION BINARY ENCODING
rest this chapter consists detailed description Z380 instructions, arranged alphabetical order mnemonic. This section describes notational conventions used instruction descriptions binary encoding register fields within instruction's operation codes (opcodes). description each instruction begins page. instruction mnemonic name printed bold letters each page enable reader easily locate desired description. assembly language syntax then given single generic form that covers variants instruction, along with list applicable addressing modes. This followed description operation performed instruction "pseudo Pascal" fashion, detailed description, listing flags that affected instruction, illustrations opcodes variants instruction. Symbols. following symbols used describe instruction set. 8-bit constant 16-bit constant 8-bit offset. (two's complement) Source instruction Destination instruction Select Register register. Word operation, register pair. 8-bit register Byte operation. Indirect register Indexed register Word operation, IXH, IXL, IYH, Byte operation. Current Stack Pointer Port pointed register Condition Code Optional field Indirect Address Pointer Direct Address Assignment value indicated symbol example, indicates that source data added destination data result stored destination location. symbol indicates that source destination swapping. example, indicates that source data swapped with data destination; after operation, data "src" "dst" location, data "dst "src" location. notation "dst (b)" used refer given location, "dst(m-n)" used refer location destination. example, HL(7) specifies destination. HL(23-16) specifies location register. Flags. register contains following flags followed symbols. Sign Flag Zero Flag Half Carry Flag Parity/Overflow Flag Add/Subtract Flag Carry Flag
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NOTATION BINARY ENCODING (Continued)
Condition Codes. following symbols describe condition codes. Zero* Zero* Carry* Carry* Sign Sign Overflow Overflow Parity Even Parity Positive Minus bottom each instruction, there field encodings, applicable. cases which call "per convention," then following encoding:
form opcode, first, look field value register, which Then find field value register, which 001. Replace field with value from table, replace value with real number. results being:
*Abbreviated Field Encoding. opcode binary format Tables, following convention: example, opcode format instruction (IX+12h), First, find entry (XY+d),R". That entry opcode format
EXECUTION TIME
Table 5-18 details execution time each instruction encoding. execution times instruction execution only. Clock cycles required fetch decode included because most time clocks required these operations occur parallel with execution previous instruction(s). execution time column indicates memory read operation. time required read operation shown Table 5-18 below. execution time column indicates memory write operation. time required write operation shown Table 5-18 below. execution time column indicates read operation. time required read operation shown Table 5-18 below. execution time column indicates write operation. time required write operation shown Table 5-18 below. entries table below assume wait states. number wait states operation must added these numbers.
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Z380USER'S MANUAL
Long B/B/B/B 9-10
Note: Units Clocks. "N/A" applicable that particular transaction.
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WITH CARRY (BYTE)
A,src Operation:
source operand together with Carry flag added accumulator stored accumulator. contents source unaffected. Two's complement addition performed. Flags: result negative; cleared otherwise result zero; cleared otherwise there carry from result; cleared otherwise arithmetic overflow occurs, that both operands cleared otherwise Cleared there carry from most significant result; cleared otherwise
Addressing Mode
Syntax A,RX A,(HL) A,(XY+d)
Instruction Format 10001-r11y11101 1000110w 11001110 10001110 11y11101 10001110-d-
Execute Time
Note
Field Encodings: convention high byte, byte
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WITH CARRY (WORD)
HL,src HL(15-0) src(15-0)
Operation:
HL(15-0)
source operand together with Carry flag added register stored register. contents source unaffected. Two's complement addition performed. Flags: Addressing Mode result negative; cleared otherwise result zero; cleared otherwise there carry from result; cleared otherwise arithmetic overflow occurs, that both operands same sign result opposite sign; cleared otherwise Cleared there carry from most significant result; cleared otherwise Execute Time
Syntax HL,R
Instruction Format 11101101 01rr1010
Note
Field Encodings:
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ADCW WITH CARRY (WORD)
ADCW [HL,]src Operation: HL(15-0)
HL(15-0) src(15-0)
source operand together with Carry flag added register stored register. contents source unaffected. Two's complement addition performed. Flags: Addressing Mode result negative; cleared otherwise result zero; cleared otherwise there carry from result; cleared otherwise arithmetic overflow occurs, that both operands same sign result opposite sign; cleared otherwise Cleared there carry from most significant result; cleared otherwise Execute Time
Syntax ADCW [HL,]R ADCW [HL,]RX ADCW [HL,]nn ADCW [HL,](XY+d)
Instruction Format 11101101 100011rr 11y11101 10001111 11101101 10001110 -n(low)- n(high)11y11101 11001110
Note
Field Encodings:
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(BYTE)
A,src Operation:
source operand added accumulator stored accumulator. contents source unaffected. Two's complement addition performed. Flags: Addressing Mode result negative; cleared otherwise result zero; cleared otherwise there carry from result; cleared otherwise arithmetic overflow occurs, that both operands same sign result opposite sign; cleared otherwise Cleared there carry from most significant result; cleared otherwise Execute Time
Syntax A,RX A,(HL) A,(XY+d)
Instruction Format 10000-r11y11101 1000010w 11000110 10000110 11y11101 10000110
Note
Field Encodings: convention high byte, byte
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(WORD)
dst,src
Operation:
(XM) then begin dst(31-0) dst(31-0) src(31-0) else begin dst(15-0) dst(15-0) src(15-0) source operand added destination stored destination. contents source unaffected. Two's complement addition performed. Note that length operand controlled Extended/Native mode selection, which consistent with manipulation address instruction.
Flags:
Unaffected Unaffected there carry from result; cleared otherwise Unaffected Cleared there carry from most significant result; cleared otherwise Execute Time
Addressing Mode
Syntax HL,R XY,R HL,(nn)
Instruction Format 00rr1001 11y11101 00rr1001 11101101 11000110 -n(low)-
n(high)-
Note
Field Encodings: register itself,
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STACK POINTER (WORD)
SP,src Operation: (XM) then begin SP(31-0) else begin SP(15-0)
SP(31-0) src(31-0)
SP(15-0) src(15-0)
source operand added register stored register. This effect allocating allocating space stack. Two's complement addition performed. Flags: Unaffected Unaffected there carry from result; cleared otherwise Unaffected Cleared there carry from most significant result; cleared otherwise Execute Time
Addressing Mode
Syntax SP,nn
Instruction Format 11101101 10000010 -n(low)- -n(high)
Note
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ADDW (WORD)
ADDW [HL,]src Operation: HL(15-0)
HL(15-0) src(15-0)
source operand added register stored register. contents source unaffected. Two's complement addition performed. Flags: Addressing Mode result negative; cleared otherwise result zero; cleared otherwise there carry from result; cleared otherwise arithmetic overflow occurs, that both operands same sign result opposite sign; cleared otherwise Cleared there carry from most significant result; cleared otherwise Execute Time
Syntax ADDW [HL,]R ADDW [HL,]RX ADDW [HL,]nn ADDW [HL,](XY+d)
Instruction Format 11101101 100001rr 11y11101 10000111 11101101 10000110 -n(low)- n(high)11y11101 11000110
Note
Field Encodings:
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(BYTE)
[A,]src Operation:
logical operation performed between corresponding bits source operand accumulator result stored accumulator. stored wherever corresponding bits operands both otherwise stored. contents source unaffected. Flags: most significant result set; cleared otherwise bits result zero; cleared otherwise parity even; cleared otherwise Cleared Cleared Execute Time
Addressing Mode
Syntax [A,]R [A,]RX [A,]n [A,](HL) [A,](XY+d)
Instruction Format 10100-r11y11101 1010010w 11100110 10100110 11y11101 10100110-d-
Note
Field
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