AthlonMP Processor with 512KB Cache Technology Performance Leader

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AthlonMP Processor with 512KB Cache Technology Performance Leader

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AthlonMP Processor with 512KB Cache
Technology Performance Leadership Microprocessors
Jack Huynh
Place Sunnyvale, 94088
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AthlonMP Processor
2003
Introduction: Continuing Performance Leadership Microprocessors
Founded 1969, shipped more than million processors worldwide. processors power behind desktop notebook PCs, generation servers workstations. Since introduction 1999, award-winning Athlonprocessor been known industry leader, enabling highest system performance levels market. Since launch June 2001, Athlon processor computer systems based Athlon processor have numerous awards worldwide. all, Athlon processor family, systems based such processors, more than awards worldwide, including World's World Class Award overall Product Year 2000 2002. Athlon processor family provided industry-leading processing power pave road levels end-user capability with application areas from productivity compute-intensive workstation applications, including digital content creation computer-aided design. server market, Athlon processor also provided reliability, stability, performance needed mission-critical email, exchange, file, print, networking applications. Engineering technology leadership performance leadership. AMD's engineering technology leadership specific seventh-generation Athlon processor family includes driving innovations such instruction extensions aimed applications (3DNow!Professional technology) processor instruction level, memory platform level, 0.13-micron process with copper interconnect process technology level. With introduction Athlon processor with 512KB cache 0.13micron process technology, continues tradition technology innovation enabling high levels delivered workstation server performance. discussion that follows provides in-depth look Athlon processor with 512KB cache 0.13-micron process technology increases performance scalability QuantiSpeedarchitecture. differentiating features, well real-world application performance benefits Smart technology multiprocessing architecture) QuantiSpeed architecture will also discussed.
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AthlonMP Processor
2003
Manufacturing Technology Leadership with Leading Edge 0.13-Micron Process Technology
Athlon processor, based core previously codenamed "Barton," newest member family seventh-generation Athlon processors designed meet computationally-intensive requirements software data-rich applications running high-performance workstation server systems. Athlon processor with 512KB cache 0.13-micron process technology increases performance scalability provided QuantiSpeed architecture over previous generations delivering higher clock speeds. 0.13-micron process technology provides thermal headroom necessary scale frequency within thermal limits workstation server platforms, thus maximizing overall performance. Athlon processor with 512KB cache 0.13-micron process technology, like Athlon processors, compatible with AMD's established Socket infrastructure. With increased frequency scalability resulting from 0.13-micron technology combined with QuantiSpeed architecture Smart technology, continues deliver compelling solutions compute-intensive applications workstations servers, delivers superb integer, floating point, multimedia performance applications running technology-based platforms.
Smart Technology Smarter Multiprocessing
With Athlon processor, offers Smart technology-a multiprocessing architecture enabling exceptionally fast performance excellent scalability beyond some traditional multiprocessor system architectures. AMD's innovative Smart technology designed optimize execution multithreaded applications empowering workstations servers achieve exceptional levels productivity performance. Smart technology consists following architectural features: Dual point-to-point high-speed system buses Innovative bus-snooping capability Optimized MOESI cache-coherency protocol
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AthlonMP Processor
2003
Smart technology implements dual point-to-point high-speed system buses that allow processors independently without experiencing system bottleneck sharing common system bus. Performance delays caused arbitration ownership transitions eliminated this architecture, allowing each processor perform dedicated channel system resources. split-transaction nature Athlon system bus, combined with independent data command channels, delivers high-speed front-side solution Athlon processors. snooping critical mechanism maintaining system's data coherency. While processor accessing memory, second processor must snoop "monitor" activity determine current memory access affects memory space. then appropriate measures must taken ensure that affected processors masters have most accurate data available. Smart technology implements performance-oriented snooping mechanism. processors leverage independent processor-to-system, system-to-processor, data channels Athlon system create "virtual" snooping channel. processor transfer data while simultaneously receiving snoop information, processor broadcast snoop information while simultaneously receiving data. some non-split-transactioned, shared-bus architectures, snooping activity "focused" only current access occurring shared system bus. Hence, there less opportunity concurrent data transfers that independent current snoop activity. This translates into performance advantage Athlon processor-based system using Smart technology that data more fully utilized transferring data opposed wasting time handling snoop requests. Smart technology also implements MOESI (Modified, Owner, Exclusive, Shared, Invalid) cache-coherency protocol. MOESI protocol offers potential performance advantage over systems implementing MESI (Modified, Exclusive, Shared, Invalid) protocol. additional "Owner" state allows processor cache "owning" data supply data directly second processor requesting access cached block. requesting processor longer wait owning processor write requested data back main memory before data accessible. Instead, owning processor supplies requested data directly requesting processor. This scheme reduces memory traffic, allows faster access cached data. With Smart technology, Athlon processor continues deliver breakthrough performance multiprocessing server workstation markets.
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AthlonMP Processor
2003
QuantiSpeedArchitecture: More Optimally Balanced Microarchitecture Real-World Application Performance
microprocessor component determining effectiveness computer system execute specific tasks shortest amount time. amount time required complete specific software tasks referred realworld application performance. Application performance function elements. Clock speed processor, measured megahertz gigahertz amount work processor accomplish given clock cycle, measured instructions clock cycle (IPC) Real-World Application Performance [work completed clock cycle] [clock speed] Frequency Different approaches taken optimize processor application performance. worked maintain more balanced microarchitecture with shorter pipeline designed higher than competitive processors available market. Although other competitive processors enable deeper pipelines with fewer gates clock drive frequency improvements, deeper pipelines alone translate into less work clock cycle. This reduced work clock cycle reduced only offset improvements other areas, such branch prediction cache rates. Taken extreme, processor performance actually reduced forcing frequency improvements expense improvements.
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AthlonMP Processor
2003
This point illustrated office applications which tend branch-code intensive resulting lower performance deeper pipelines that must flushed with much greater performance penalty. reaffirmed Desktop Performance Optimization Intel Pentium® Processor paper "Integer basic office productivity applications, such Word spreadsheet processing, tend have many branches code, thus reducing overall capabilities. result, associated branch penalties performance these applications does generally scale well with frequency more resistant improvements micro architectural means, such deeper pipelines." Athlon processor with Smart technology QuantiSpeedarchitecture implemented 0.13-micron technology continues exhibit Athlon processor family's balanced combination improving clock frequency without compromising amount work done clock cycle therefore IPC. result processor design that produces high well high operating frequencies, optimum combination deliver very high level workstation server performance real-world application environments. QuantiSpeed architecture consists four differentiating features that enhance application performance Athlon processor: Nine-issue, superscalar, fully pipelined microarchitecture Superscalar, fully pipelined floating-point unit (FPU) Hardware data prefetch Enhanced Translation Look-aside Buffers (TLBs)
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AthlonMP Processor
2003
Predecode Cache Branch Prediction Table
2-way, 64KB Instruction Cache
24-entry TLB/256-entry
Fetch/Decode Control
3-Way Instruction Decoders Instruction Control Unit (72-entry)
Integer Scheduler (18-entry)
Stack Rename Scheduler (36-entry) Register File (88-entry)
Interface Unit
FStore
FADD 3DNow! FMUL 3DNow!
Cache 16-way, 256KB
Load Store Queue Unit
2-way, 64KB Data Cache
40-entry TLB/256-entry
System Interface
Figure AthlonMP Microarchitecture Block Diagram
QuantiSpeedArchitecture: Nine-Issue, Superscalar, Fully Pipelined Microarchitecture with High-Performance Cache Memory Architecture, Three Full Instruction Decoders
heart QuantiSpeed architecture fully pipelined, nine-issue, superscalar processor core. Athlon processor provides wider execution bandwidth nine execution pipes when compared with competitive processors that have execution pipes. nine execution engines comprised three address calculation units, three integer units, three floating-point units.
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AthlonMP Processor
2003
order supply such highly superscalar microarchitecture, Athlon processor implements large, on-chip cache architecture particularly cache closest core. Athlon processor's highperformance, on-chip cache architecture includes dual-ported 128KB (two separate 64K) split-L1 cache with separate snoop ports, integrated full-speed, 16-way set-associative, 512KB cache using 72-bit (64-bit data 8-bit ECC) interface. Athlon processor's large integrated full-speed cache comprised separate 64KB, two-way set-associative data instruction caches, which much larger than Intel Xeon processor's cache (128K µop). featuring larger cache, applications running Athlon processor perform exceptionally fast since more instruction data information local processor. Applications exploit larger caches benefiting from increased support instruction data locality. data cache also eight banks provide maximum parallelism running multiple applications. supports concurrent accesses 64-bit loads stores. instruction cache contains predecode data assist multiple, high-performance instruction decoders. Both instruction data caches dual-ported contain dedicated snoop ports designed eliminate system coherency traffic, common systems with many devices, from interfering with application performance. Athlon processor also includes integrated, full-speed, 16-way set-associative, exclusive 512KB cache. When processor requests data, first searches data cache. processor finds data cache, result what known cache processor retrieves data from latency cache. processor cannot retrieve data from cache, processor attempts retrieve data cache once again attempts obtain cache hit. event cache miss, processor must then request this data from slower system memory. With additional 256KB cache over previous Athlon processors, Athlon processor with 512KB cache increases performance server applications such email, exchange, file, print, networking applications keeping more frequently accessed instructions data close CPU. Depending environment, larger caches greatly benefit server workstation applications that demand large datasets such database messaging applications. Higher set-associativity increases rate reducing data conflicts. This translates into more possible locations which important data reside cache memory instead system memory. With exclusive cache architecture, contents caches duplicated cache. This enables 512KB cache 128KB cache total usable storage space 640KB.
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AthlonMP Processor
2003
Athlon processor cache architecture also supports error correction code (ECC) protection. With these cache architecture features, Athlon processor designed provide reliable, high-performance computing. When executing software, processor begins decoding program's instructions translating them into operations Ops) that microprocessor execute. order continually feed execution engine with data, Athlon processor includes three instruction decoders. Each decoder capable decoding three instructions clock cycle. comparison, Xeon processor designed decode only instruction clock cycle with resource only instruction decoder. Thus, Xeon processor only one-third maximum theoretical decode bandwidth Athlon processor. decode bandwidth Athlon processor enables processor advantageously utilize execution bandwidth capabilities QuantiSpeed architecture, thereby improving IPC.
QuantiSpeedArchitecture: Superscalar, Fully Pipelined Floating-Point Unit (FPU)
Athlon processor offers most powerful, architecturally advanced floating-point units (FPU) delivered microprocessor. Athlon processor's three-issue, superscalar floating-point capability based three pipelined, out-of-order floating-point execution units, each with one-cycle throughput. Using data format single-instruction multiple-data (SIMD) operations based MMXinstruction model, Athlon processor deliver many four 32-bit, single-precision floating-point results clock cycle.
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AthlonMP Processor
2003
Microarchitecture
Three separate execution units Athlon processor's floatingpoint pipeline support floating-point instructions, instructions, 3DNow!Professional technology instructions. three execution units are: Fstore-This floating point load/store pipeline that handles loads, stores, miscellaneous operations. Fadd-This adder pipeline that contains 3DNow! Professional technology, add, ALU/shifter, execution units. Fmul-This multiplier pipeline that contains ALU, multiplier, reciprocal unit, 3DNow! Professional technology instruction multiplier, support FDIV instructions. addition superscalar design, Athlon processor's super pipelined. This technique supports higher clock frequencies enables process complex floating-point instructions more quickly deliver high overall floating-point instruction throughput. comparison, Xeon processor only offers execution units, both Fadd Fmul Fstore. Thus, example, Athlon processor floating-point addition multiplication clock cycle, while Xeon processor only multiplication addition clock cycle. seventh-generation Athlon processor incorporates other features such 36-entry instruction scheduler 88-entry register file independent, superscalar, outof-order, speculative execution floating-point instructions. With three separate execution units, Athlon processor's superscalar boost performance floating point-intensive applications varying from commercial applications such modeling consumer applications such digital video audio editing workstations.
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AthlonMP Processor
2003
3DNow!Professional Technology: Innovation AthlonMP Processor Core
Athlon processor with 3DNow! Professional technology adds instructions enhanced 3DNow! technology supported original Athlon processor family. These instructions, along with SIMD integer additions already included enhanced 3DNow! technology, compatible with Intel's technology. Table provides breakout 3DNow! technology instruction evolution.
Table Processor Support SIMD Instruction Extensions Instruction Architecture
Processor: 3DNow!technology version supported: Description instructions supported:
AMD-K6®-2 Processor 3DNow!technology
AthlonProcessor Enhanced 3DNow! technology
Athlon Processor 3DNow! Professional technology
Original 3DNow! technology extensions
3DNow! technology plus extensions (part SSE) plus five DSP/communications extensions
Enhanced 3DNow! technology plus extensions (completing support)
3DNow! technology largely complementary architectural enhancements. implementing them variety ways, software developers able determine they utilize advanced architectural capabilities enabled SIMD instruction extensions. Examples applications most able benefit from these instruction extensions include speed recognition, video encoding/decoding, graphics generation. Many current software applications that SIMD-optimized different code paths benefit from 3DNow! technology SSE, depending processor architecture which these applications executed. processor architectures preceding Athlon processor only supported 3DNow! enhanced 3DNow! technology, which yielded following three code path scenarios developers:
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AthlonMP Processor
2003
Software optimized exclusively processor architectures with 3DNow! technology their 3DNow! technology-optimized code path processors supporting 3DNow! technology. Software optimized both processor architectures with 3DNow! technology, other industry processor architectures supporting SSE, their 3DNow! technology-optimized code path processors supporting 3DNow! technology. Software optimized exclusively other industry processor architectures supporting non-optimized code path processor architectures. With advent 3DNow! Professional technology, Athlon processor seamlessly allow SIMD-optimized software third scenario above recognize support optimized code path increased performance. recognition support 3DNow! Professional technology performed automatically software applications that industry standard feature flags, provided CPUID instruction automatically recognize support optimized code path. This means that with 3DNow! Professional technology's support both 3DNow! technologies, Athlon processor able take advantage performance gains offered SIMD-optimized software applications. only Athlon processor designed benefit from existing software applications supporting 3DNow! technologies, future, software developers should have ability utilize strength both 3DNow! technology when optimizing code paths processor architectures that support 3DNow! Professional technology. Athlon processor enables this advanced level SIMD optimization allowing 3DNow! instructions executed same code path.
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AthlonMP Processor
2003
QuantiSpeedArchitecture: Hardware Data Prefetch
further enhance processor and, therefore processor performance, Athlon processor also uses hardware data prefetch technology. This hardware data prefetch technology observes memory accesses, looks regular access patterns, speculatively fetches cache line with data into processor's data cache advance actual data access, therefore reducing average latency seen processor accessing memory. past, data prefetch supported through instructions introduced 3DNow! technologies. However, processor take advantage this capability, software applications specifically optimized with 3DNow! instructions. Athlon processor designed automatically optimize performance existing software that previously been optimized using hardware data prefetch instructions supported 3DNow! Professional technology. Benefits Athlon processor's hardware data prefetching observed more high-end, data-intensive server applications that access larger arrays data. Performance also benefits occupying processor instruction execution bandwidth required software prefetching instructions. optimization most effective when coupled with high-bandwidth system memory transfer capability, available processor platforms such those optimized support memory.
QuantiSpeedArchitecture: Exclusive Speculative Translation Look-aside Buffers (TLBs)
Athlon processor features advanced, two-level Translation Lookaside Buffer (TLB) structures both instruction data address translation. Athlon processor's Level (L1) Instruction (I-TLB) holds entries, Data (D-TLB) holds entries, I-TLB D-TLB each hold entries. reduce incidence entry conflicts, structures adopt exclusive architecture design. With exclusive architecture, TLBs contain entries that duplicated TLBs, enabling combination sizes larger total available entry space both instruction data TLBs. reducing number conflicts caused holding more entries within processor, performance increases high-end,
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AthlonMP Processor
2003
data-intensive applications that encounter instruction sequences that longer have wait entries reloaded during execution. structures Athlon processor also have ability enter data misses TLBs speculatively. Athlon processor allows entries written speculatively before first instruction completed, while preserving proper instruction execution ordering that removes serialization effect results improved system performance.
Conclusion: Technology Performance Leadership Microprocessors
With these differentiating features Athlon processor with QuantiSpeed architecture. 0.13-micron process technology-Provides further thermal headroom necessary scale frequency within thermal limits workstation server platforms processors, thus maximizing overall performance 512KB cache-Increases performance server applications such email, exchange, file, print, networking applications keeping more frequently accessed instructions data close CPU. Smart Technology: Dual point-to-point high-speed system buses-Allows processors independently without overhead sharing common system Innovative bus-snooping capability-Offers high-speed communication between processors multiprocessing system Optimized MOESI cache-coherency protocol-Reduces memory traffic allows faster access cached data.
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AthlonMP Processor
2003
QuantiSpeedArchitecture: Nine-issue, superscalar, fully pipelined microarchitecture-Provides wide executing bandwidth improve overall productivity Superscalar, fully pipelined FPU-Increasing performance floating point-intensive applications while offering 3DNow! Professional technology support Hardware data prefetch-Increasing performance high-end software applications using high-bandwidth system capability, especially with memory
enhancements-Increasing performance high-end, dataintensive applications
.AMD continues accelerate technology innovations while meeting computationally intensive requirements software applications including: applications-3D modeling, animation, digital visualization, etc. Multimedia/digital content creation applications-Photo video editing, video encoding decoding, image compression, soft DVD, encoding decoding, etc. High-end applications-Digital publishing, speech recognition, CAM, digital prototyping, etc. Infrastructure applications-Web servers, file application servers, messaging database servers With compelling performance across these number other applications, Athlon processor with 512KB cache implemented 0.13-micron technology featuring Smart technology continues increase performance scalability provided QuantiSpeed architecture delivering high clock speeds excellent processor performance over previous generations. Athlon processor with 512KB cache Smart technology continues tradition Athlon processor family providing compelling levels delivered system performance today's tomorrow's applications.
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AthlonMP Processor
2003
Overview
Founded 1969 based Sunnyvale, California, (NYSE: AMD) global supplier integrated circuits personal networked computer communications markets with manufacturing facilities United States, Europe, Japan, Asia. AMD, Standard Poor's company, produces microprocessors, Flash memory devices, silicon-based solutions communications networking applications.
2003 Advanced Micro Devices, Inc. rights reserved. AMD, Arrow logo, Athlon, combinations thereof, 3DNow!, QuantiSpeed, PowerNow! trademarks AMD-K6 registered trademark Advanced Micro Devices, Inc. Pentium registered trademark trademark Intel Corporation United States and/or other jurisdictions. HyperTransport licensed trademark HyperTransport Technology Consortium. Other product company names used this publication identification purposes only trademarks their respective companies.
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AthlonMP Processor
2003

AthlonMP Processor with 512KB Cache Technology Performance Leader

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