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eZ80L92

PRELIMINARY PS013011-0204

eZ80L92
Product Specification
PRELIMINARY PS013011-0204
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eZ80L92 Product Specification
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PS013011-0204
eZ80L92 Product Specification
Table of Contents
PS013011-0204
Table of Contents
eZ80L92 Product Specification
PS013011-0204
Table of Contents
eZ80L92 Product Specification
PS013011-0204
Table of Contents
eZ80L92 Product Specification
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Table of Contents
eZ80L92 Product Specification
List of Figures
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List of Figures
eZ80L92 Product Specification
Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57.
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List of Figures
eZ80L92 Product Specification
List of Tables
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List of Tables
eZ80L92 Product Specification
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List of Tables
eZ80L92 Product Specification
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List of Tables
eZ80L92 Product Specification
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List of Tables
eZ80L92 Product Specification
Architectural Overview
Features
· · · · · · · · Single-cycle instruction fetch, high-performance, pipelined eZ80® CPU core1 Low power features including SLEEP mode, HALT mode, and selective peripheral power-down control Two UARTs with independent baud rate generators SPI with independent clock rate generator I2C with independent clock rate generator Infrared Data Association (IrDA)-compliant infrared encoder / decoder New DMA-like eZ80® instructions for efficient block data transfer Glueless external peripheral interface with 4 Chip Selects, individual Wait State generators, and an external WAIT input pin-supports Intel-and Motorola-style buses Fixed-priority vectored interrupts (both internal and external) and interrupt controller Real-time clock with on-chip 32 KHz oscillator, selectable 50 / 60Hz input, and separate VDD pin for battery backup Six 16-bit Counter / Timers with prescalers and direct input / output drive Watch-Dog Timer 24 bits of General-Purpose I / O JTAG and ZDI debug interfaces 100-pin LQFP package 3.0-3.6 V supply voltage with 5 V tolerant inputs
1. For simplicity, the term eZ80® CPU is referred to as CPU for the bulk of this document.
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Architectural Overview
eZ80L92 Product Specification
Note: All signals with an overline are active Low. For example, B / W, for which WORD is active Low, and B / W, for which BYTE is active Low. Power connections follow these conventional descriptions:
Connection Power Ground Circuit VCC GND Device VDD VSS
Block Diagram
Figure 1 illustrates a block diagram of the eZ80L92 microprocessor.
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Architectural Overview
eZ80L92 Product Specification
Real-Time Clock and 32 KHz Oscillator SCL SDA I2C Serial Interface
Bus Controller
BUSACK BUSREQ INSTRD IORQ MREQ RD WR
CTS0 / 1 DCD0 / 1 DSR0 / 1 DTR0 / 1 RI0 / 1 RTS0 / 1 RxD0 / 1 TxD0 / 1 Universal Asynchronous Receiver / Transmitter (UART)
ZiLOG Debug Interface (JTAG / ZDI) Interrupt Vector 7:0 Interrupt Controller
JTAG / ZDI Signals (5)
Chip Select and Wait State Generator
WAIT CS0 CS1 CS2 CS3
DATA7:0 ADDR23:0 8-Bit General Purpose I / O Port (GPIO) Crystal Oscillator and System Clock Generator
IrDA Encoder / Decoder
Programmable Reload Timer / Counters (6)
Watch-Dog Timer (WDT)
PB7:0
Figure 1. eZ80L92 Block Diagram
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PC7:0
PD7:0
Architectural Overview
eZ80L92 Product Specification
Pin Description
Figure 2 illustrates the pin layout of the eZ80L92 in the 100-pin LQFP package. Table 1 describes the pins and their functions.
100-Pin LQFP
Figure 2. 100-Pin LQFP Configuration of the eZ80L92
Architectural Overview
eZ80L92 Product Specification
Table 1. 100-Pin LQFP Pin Identification of the eZ80L92 Device Pin # 1 Symbol ADDR0 Function Address Bus Signal Direction Bidirectional Description Configured as an output in normal operation. The address bus selects a location in memory or I / O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select / Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I / O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select / Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I / O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select / Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I / O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select / Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I / O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select / Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I / O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select / Wait State Generator block to generate Chip Selects.
ADDR1
Address Bus
Bidirectional
ADDR2
Address Bus
Bidirectional
ADDR3
Address Bus
Bidirectional
ADDR4
Address Bus
Bidirectional
ADDR5
Address Bus
Bidirectional
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Architectural Overview
eZ80L92 Product Specification
Table 1. 100-Pin LQFP Pin Identification of the eZ80L92 Device (Continued) Pin # 7 8 9 Symbol VDD VSS ADDR6 Function Power Supply Ground Address Bus Bidirectional Signal Direction Description Power Supply. Ground. Configured as an output in normal operation. The address bus selects a location in memory or I / O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select / Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I / O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select / Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I / O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select / Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I / O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select / Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I / O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select / Wait State Generator block to generate Chip Selects.
ADDR7
Address Bus
Bidirectional
ADDR8
Address Bus
Bidirectional
ADDR9
Address Bus
Bidirectional
ADDR10
Address Bus
Bidirectional
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Architectural Overview
eZ80L92 Product Specification
Table 1. 100-Pin LQFP Pin Identification of the eZ80L92 Device (Continued) Pin # 14 Symbol ADDR11 Function Address Bus Signal Direction Bidirectional Description Configured as an output in normal operation. The address bus selects a location in memory or I / O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select / Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I / O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select / Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I / O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select / Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I / O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select / Wait State Generator block to generate Chip Selects. Power Supply. Ground. Bidirectional Configured as an output in normal operation. The address bus selects a location in memory or I / O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select / Wait State Generator block to generate Chip Selects.
ADDR12
Address Bus
Bidirectional
ADDR13
Address Bus
Bidirectional
ADDR14
Address Bus
Bidirectional
VDD VSS ADDR15
Power Supply Ground Address Bus
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Architectural Overview
eZ80L92 Product Specification
Table 1. 100-Pin LQFP Pin Identification of the eZ80L92 Device (Continued) Pin # 21 Symbol ADDR16 Function Address Bus Signal Direction Bidirectional Description Configured as an output in normal operation. The address bus selects a location in memory or I / O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select / Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I / O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select / Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I / O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select / Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I / O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select / Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I / O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select / Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I / O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select / Wait State Generator block to generate Chip Selects.
ADDR17
Address Bus
Bidirectional
ADDR18
Address Bus
Bidirectional
ADDR19
Address Bus
Bidirectional
ADDR20
Address Bus
Bidirectional
ADDR21
Address Bus
Bidirectional
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Architectural Overview
eZ80L92 Product Specification
Table 1. 100-Pin LQFP Pin Identification of the eZ80L92 Device (Continued) Pin # 27 Symbol ADDR22 Function Address Bus Signal Direction Bidirectional Description Configured as an output in normal operation. The address bus selects a location in memory or I / O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select / Wait State Generator block to generate Chip Selects. Configured as an output in normal operation. The address bus selects a location in memory or I / O space to be read or written. Configured as an input during bus acknowledge cycles. Drives the Chip Select / Wait State Generator block to generate Chip Selects. CS0 Low indicates that an access is occurring in the defined CS0 memory or I / O address space. CS1 Low indicates that an access is occurring in the defined CS1 memory or I / O address space. CS2 Low indicates that an access is occurring in the defined CS2 memory or I / O address space. CS3 Low indicates that an access is occurring in the defined CS3 memory or I / O address space. Power Supply. Ground. Bidirectional The data bus transfers data to and from I / O and memory devices. The eZ80L92 drives these lines only during write cycles when the eZ80L92 is the bus master. The data bus transfers data to and from I / O and memory devices. The eZ80L92 drives these lines only during write cycles when the eZ80L92 is the bus master.
ADDR23
Address Bus
Bidirectional
Chip Select 0
Output, Active Low
Chip Select 1
Output, Active Low
Chip Select 2
Output, Active Low
Chip Select 3
Output, Active Low
VDD VSS DATA0
Power Supply Ground Data Bus
DATA1
Data Bus
Bidirectional
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eZ80L92 Product Specification
Table 1. 100-Pin LQFP Pin Identification of the eZ80L92 Device (Continued) Pin # 37 Symbol DATA2 Function Data Bus Signal Direction Bidirectional Description The data bus transfers data to and from I / O and memory devices. The eZ80L92 drives these lines only during write cycles when the eZ80L92 is the bus master. The data bus transfers data to and from I / O and memory devices. The eZ80L92 drives these lines only during write cycles when the eZ80L92 is the bus master. The data bus transfers data to and from I / O and memory devices. The eZ80L92 drives these lines only during write cycles when the eZ80L92 is the bus master. The data bus transfers data to and from I / O and memory devices. The eZ80L92 drives these lines only during write cycles when the eZ80L92 is the bus master. The data bus transfers data to and from I / O and memory devices. The eZ80L92 drives these lines only during write cycles when the eZ80L92 is the bus master. The data bus transfers data to and from I / O and memory devices. The eZ80L92 drives these lines only during write cycles when the eZ80L92 is the bus master. Power Supply. Ground. Bidirectional, Active Low IORQ indicates that the CPU is accessing a location in I / O space. RD and WR indicate the type of access. The eZ80L92 does not drive this line during RESET. It is an input in bus acknowledge cycles. MREQ Low indicates that the CPU is accessing a location in memory. The RD, WR, and INSTRD signals indicate the type of access. The eZ80L92 does not drive this line during RESET. It is an input in bus acknowledge cycles.
DATA3
Data Bus
Bidirectional
DATA4
Data Bus
Bidirectional
DATA5
Data Bus
Bidirectional
DATA6
Data Bus
Bidirectional
DATA7
Data Bus
Bidirectional
VDD VSS IORQ
Power Supply Ground Input / Output Request
Memory Request
Bidirectional, Active Low
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Architectural Overview
eZ80L92 Product Specification
Table 1. 100-Pin LQFP Pin Identification of the eZ80L92 Device (Continued) Pin # 47 Symbol RD Function Read Signal Direction Output, Active Low Description RD Low indicates that the eZ80L92 is reading from the current address location. This pin is tristated during bus acknowledge cycles. WR indicates that the CPU is writing to the current address location. This pin is tristated during bus acknowledge cycles. INSTRD (with MREQ and RD) indicates the eZ80L92 is fetching an instruction from memory. This pin is tristated during bus acknowledge cycles. Driving the WAIT pin Low forces the CPU to wait additional clock cycles for an external peripheral or external memory to complete its Read or Write operation.
Write
Output, Active Low
INSTRD
Instruction Output, Active Low Read Indicator
WAIT Request Input, Active Low
RESET
Reset
Schmitt Trigger Input, This signal is used to initialize the Active Low eZ80L92. This input must be Low for a minimum of 3 system clock cycles, and must be held Low until the clock is stable. This input includes a Schmitt trigger to allow RC rise times.
Nonmaskable Schmitt Trigger Input, The NMI input is a higher priority input than Interrupt Active Low the maskable interrupts. It is always recognized at the end of an instruction, regardless of the state of the interrupt enable control bits. This input includes a Schmitt trigger to allow RC rise times. Bus Request Input, Active Low External devices can request the eZ80L92 to release the memory interface bus for their use, by driving this pin Low. The eZ80L92 responds to a Low on BUSREQ, by tristating the address, data, and control signals, and by driving the BUSACK line Low. During bus acknowledge cycles ADDR23:0, IORQ, and MREQ are inputs. A Low on this pin indicates that the CPU has entered either HALT or SLEEP mode because of execution of either a HALT or SLP instruction.
BUSREQ
BUSACK
Bus Acknowledge
Output, Active Low
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Architectural Overview
eZ80L92 Product Specification
Bidirectional
Real-Time Clock Power Supply
VSS TMS TCK TRIGOUT TDI TDO VDD
Ground JTAG Test Mode Select JTAG Test Clock
JTAG Test Output Trigger Output JTAG Test Data In JTAG Test Data Out Power Supply Bidirectional Output
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Architectural Overview
eZ80L92 Product Specification
Table 1. 100-Pin LQFP Pin Identification of the eZ80L92 Device (Continued) Pin # 68 Symbol PD0 Function GPIO Port D Signal Direction Bidirectional Description This pin can be used for general-purpose I / O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port D pin, when programmed as output, can be selected to be an open-drain or opensource output. Port D is multiplexed with one UART. This pin is used by the UART to transmit asynchronous serial data. This signal is multiplexed with PD0. This pin is used by the IrDA encoder / decoder to transmit serial data. This signal is multiplexed with PD0. This pin can be used for general-purpose I / O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port D pin, when programmed as output, can be selected to be an open-drain or opensource output. Port D is multiplexed with one UART. This pin is used by the UART to receive asynchronous serial data. This signal is multiplexed with PD1. This pin is used by the IrDA encoder / decoder to receive serial data. This signal is multiplexed with PD1. This pin can be used for general-purpose I / O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port D pin, when programmed as output, can be selected to be an open-drain or opensource output. Port D is multiplexed with one UART. Modem control signal from UART. This signal is multiplexed with PD2.
UART Transmit Data
Output
IrDA Transmit Output Data GPIO Port D Bidirectional
Receive Data
Input
IrDA Receive Data GPIO Port D
Input
Bidirectional
Request to Send
Output, Active Low
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Architectural Overview
eZ80L92 Product Specification
Table 1. 100-Pin LQFP Pin Identification of the eZ80L92 Device (Continued) Pin # 71 Symbol PD3 Function GPIO Port D Signal Direction Bidirectional Description This pin can be used for general-purpose I / O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port D pin, when programmed as output, can be selected to be an open-drain or opensource output. Port D is multiplexed with one UART. Modem status signal to the UART. This signal is multiplexed with PD3. This pin can be used for general-purpose I / O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port D pin, when programmed as output, can be selected to be an open-drain or opensource output. Port D is multiplexed with one UART. Modem control signal to the UART. This signal is multiplexed with PD4. This pin can be used for general-purpose I / O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port D pin, when programmed as output, can be selected to be an open-drain or opensource output. Port D is multiplexed with one UART. Modem status signal to the UART. This signal is multiplexed with PD5. This pin can be used for general-purpose I / O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port D pin, when programmed as output, can be selected to be an open-drain or opensource output. Port D is multiplexed with one UART. Modem status signal to the UART. This signal is multiplexed with PD6.
CTS0 72 PD4
Clear to Send Input, Active Low GPIO Port D Bidirectional
DTR0 73 PD5
Data Terminal Output, Active Low Ready GPIO Port D Bidirectional
DSR0 74 PD6
Data Set Ready GPIO Port D
Input, Active Low Bidirectional
Data Carrier Detect
Input, Active Low
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Architectural Overview
eZ80L92 Product Specification
Table 1. 100-Pin LQFP Pin Identification of the eZ80L92 Device (Continued) Pin # 75 Symbol PD7 Function GPIO Port D Signal Direction Bidirectional Description This pin can be used for general-purpose I / O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port D pin, when programmed as output, can be selected to be an open-drain or opensource output. Port D is multiplexed with one UART. Modem status signal to the UART. This signal is multiplexed with PD7. This pin can be used for general-purpose I / O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port C pin, when programmed as output, can be selected to be an open-drain or opensource output. Port C is multiplexed with one UART. This pin is used by the UART to transmit asynchronous serial data. This signal is multiplexed with PC0. This pin can be used for general-purpose I / O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port C pin, when programmed as output, can be selected to be an open-drain or opensource output. Port C is multiplexed with one UART. This pin is used by the UART to receive asynchronous serial data. This signal is multiplexed with PC1.
RI0 76 PC0
Ring Indicator Input, Active Low GPIO Port C Bidirectional
Transmit Data Output
GPIO Port C
Bidirectional
Receive Data
Input
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Architectural Overview
eZ80L92 Product Specification
Table 1. 100-Pin LQFP Pin Identification of the eZ80L92 Device (Continued) Pin # 78 Symbol PC2 Function GPIO Port C Signal Direction Bidirectional Description This pin can be used for general-purpose I / O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port C pin, when programmed as output, can be selected to be an open-drain or opensource output. Port C is multiplexed with one UART. Modem control signal from UART. This signal is multiplexed with PC2. This pin can be used for general-purpose I / O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port C pin, when programmed as output, can be selected to be an open-drain or opensource output. Port C is multiplexed with one UART. Modem status signal to the UART. This signal is multiplexed with PC3. This pin can be used for general-purpose I / O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port C pin, when programmed as output, can be selected to be an open-drain or opensource output. Port C is multiplexed with one UART. Modem control signal to the UART. This signal is multiplexed with PC4. This pin can be used for general-purpose I / O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port C pin, when programmed as output, can be selected to be an open-drain or opensource output. Port C is multiplexed with one UART. Modem status signal to the UART. This signal is multiplexed with PC5.
RTS1 79 PC3
Request to Send GPIO Port C
Output, Active Low Bidirectional
CTS1 80 PC4
Clear to Send Input, Active Low GPIO Port C Bidirectional
DTR1 81 PC5
Data Terminal Output, Active Low Ready GPIO Port C Bidirectional
Data Set Ready
Input, Active Low
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Architectural Overview
eZ80L92 Product Specification
Table 1. 100-Pin LQFP Pin Identification of the eZ80L92 Device (Continued) Pin # 82 Symbol PC6 Function GPIO Port C Signal Direction Bidirectional Description This pin can be used for general-purpose I / O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port C pin, when programmed as output, can be selected to be an open-drain or opensource output. Port C is multiplexed with one UART. Modem status signal to the UART. This signal is multiplexed with PC6. This pin can be used for general-purpose I / O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port C pin, when programmed as output, can be selected to be an open-drain or opensource output. Port C is multiplexed with one UART. Modem status signal to the UART. This signal is multiplexed with PC7. Ground. This pin is the input to the onboard crystal oscillator for the primary system clock. If an external oscillator is used, its clock output should be connected to this pin. When a crystal is used, it should be connected between XIN and XOUT. This pin is the output of the onboard crystal oscillator. When used, a crystal should be connected between XIN and XOUT. Power Supply.
DCD1 83 PC7
Data Carrier Detect GPIO Port C
Input, Active Low Bidirectional
RI1 84 85 VSS XIN
Ring Indicator Input, Active Low Ground System Clock Input Oscillator Input
System Clock Output Oscillator Output Power Supply
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Architectural Overview
eZ80L92 Product Specification
Table 1. 100-Pin LQFP Pin Identification of the eZ80L92 Device (Continued) Pin # 88 Symbol PB0 Function GPIO Port B Signal Direction Bidirectional Description This pin can be used for general-purpose I / O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port B pin, when programmed as output, can be selected to be an open-drain or opensource output. Alternate clock source for Programmable Reload Timers 0 and 2. This signal is multiplexed with PB0. This pin can be used for general-purpose I / O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port B pin, when programmed as output, can be selected to be an open-drain or opensource output. Alternate clock source for Programmable Reload Timers 1 and 3. This signal is multiplexed with PB1. This pin can be used for general-purpose I / O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port B pin, when programmed as output, can be selected to be an open-drain or opensource output. The slave select input line is used to select a slave device in SPI mode. This signal is multiplexed with PB2. This pin can be used for general-purpose I / O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port B pin, when programmed as output, can be selected to be an open-drain or opensource output. SPI serial clock. This signal is multiplexed with PB3.
Timer 0 In
Input
GPIO Port B
Bidirectional
Timer 1 In
Input
GPIO Port B
Bidirectional
Slave Select
Input, Active Low
GPIO Port B
Bidirectional
SPI Serial Clock
Bidirectional
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Architectural Overview
eZ80L92 Product Specification
Table 1. 100-Pin LQFP Pin Identification of the eZ80L92 Device (Continued) Pin # 92 Symbol PB4 Function GPIO Port B Signal Direction Bidirectional Description This pin can be used for general-purpose I / O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port B pin, when programmed as output, can be selected to be an open-drain or opensource output. Programmable Reload Timer 4 timer-out signal. This signal is multiplexed with PB4. This pin can be used for general-purpose I / O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port B pin, when programmed as output, can be selected to be an open-drain or opensource output. Programmable Reload Timer 5 timer-out signal. This signal is multiplexed with PB5. This pin can be used for general-purpose I / O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port B pin, when programmed as output, can be selected to be an open-drain or opensource output. The MISO line is configured as an input when the eZ80L92 is an SPI master device and as an output when eZ80L92 is an SPI slave device. This signal is multiplexed with PB6.
Timer 4 Out GPIO Port B
Output Bidirectional
Timer 5 Out GPIO Port B
Output Bidirectional
Master In Slave Out
Bidirectional
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Architectural Overview
eZ80L92 Product Specification
Table 1. 100-Pin LQFP Pin Identification of the eZ80L92 Device (Continued) Pin # 95 Symbol PB7 Function GPIO Port B Signal Direction Bidirectional Description This pin can be used for general-purpose I / O. It can be individually programmed as input or output and can also be used individually as an interrupt input. Each Port B pin, when programmed as output, can be selected to be an open-drain or opensource output. The MOSI line is configured as an output when the eZ80L92 is an SPI master device and as an input when the eZ80L92 is an SPI slave device. This signal is multiplexed with PB7. Power Supply. Ground. This pin carries the I2C data signal. This pin is used to receive and transmit the I2C clock. This pin is an output driven by the internal system clock.
Master Out Slave In
Bidirectional
VDD VSS SDA SCL PHI
Power Supply Ground I2C Serial Data Bidirectional I2C Serial Clock Bidirectional
System Clock Output
Pin Characteristics
Table 2. Pin Characteristics of the eZ80 Webserver-i Schmitt Trigger Open Input Drain / Source No No No No No No No No No No No No
Symbol ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 VDD
Tristate Pull Output Up / Down Yes Yes Yes Yes Yes Yes No No No No No No
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Architectural Overview
eZ80L92 Product Specification
Table 2. Pin Characteristics of the eZ80 Webserver-i (Continued) Schmitt Trigger Open Input Drain / Source
Symbol VSS ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 VDD VSS ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21 ADDR22 ADDR23 CS0 CS1 CS2 CS3 VDD VSS DATA0
Reset Active Direction Direction Low / High
Tristate Pull Output Up / Down
Yes Yes Yes Yes Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No
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Architectural Overview
eZ80L92 Product Specification
Table 2. Pin Characteristics of the eZ80 Webserver-i (Continued) Schmitt Trigger Open Input Drain / Source No No No No No No No No No No No No No No
Tristate Pull Output Up / Down Yes Yes Yes Yes Yes Yes Yes No No No No No No No
Low Low Low Low Low Low Low Low Low Low Low
No No No No No No Yes Yes No No No
PS013011-0204
Architectural Overview
eZ80L92 Product Specification
Table 2. Pin Characteristics of the eZ80 Webserver-i (Continued) Schmitt Trigger Open Input Drain / Source No N / A
Symbol TCK
Reset Active Direction Direction Low / High I I Rising (In) Falling (Out) High N / A N / A
Tristate Pull Output Up / Down N / A Up
TRIGOUT TDI TDO VDD PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 VSS XIN XOUT VDD PB0 PB1
Yes Yes Yes
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Yes Yes
PS013011-0204
Architectural Overview
eZ80L92 Product Specification
Table 2. Pin Characteristics of the eZ80 Webserver-i (Continued) Schmitt Trigger Open Input Drain / Source No No No No No No OD & OS OD & OS OD & OS OD & OS OD & OS OD & OS
Pin # 90 91 92 93 94 95 96 97 98 99 100
Symbol PB2 PB3 PB4 PB5 PB6 PB7 VDD VSS SDA SCL PHI
Tristate Pull Output Up / Down Yes Yes Yes Yes Yes Yes No No No No No No
Yes Yes Yes
PS013011-0204
Architectural Overview
eZ80L92 Product Specification
Register Map
Table 3. Register Map Address (hex) Mnemonic Reset (hex) CPU Access Page #
Notes: 1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer timeout reset, the Watch-Dog Timer Control register is reset to 20h. 2. When the CPU reads this register, the current sampled value of the port is read. 3. Read-only if RTC is locked Read / Write if RTC is unlocked. 4. After an external pin reset or a WDT reset, the RTC Control register is reset to x0xxxx00b. After an RTC Alarm Sleep-Mode Recovery reset, the RTC Control register is reset to x0xxxx10b.
PS013011-0204
Register Map
eZ80L92 Product Specification
Table 3. Register Map (Continued) Address (hex) Mnemonic Reset (hex) CPU Access Page #
Notes: 1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer timeout reset, the Watch-Dog Timer Control register is reset to 20h. 2. When the CPU reads this register, the current sampled value of the port is read. 3. Read-only if RTC is locked Read / Write if RTC is unlocked. 4. After an external pin reset or a WDT reset, the RTC Control register is reset to x0xxxx00b. After an RTC Alarm Sleep-Mode Recovery reset, the RTC Control register is reset to x0xxxx10b.
PS013011-0204
Register Map
eZ80L92 Product Specification
Table 3. Register Map (Continued) Address (hex) Mnemonic Reset (hex) CPU Access Page #
Name Port B Data Register2 Port B Data Direction Register Port B Alternate Register 1 Port B Alternate Register 2 Port C Data Register Port C Data Direction Register Port C Alternate Register 1 Port C Alternate Register 2 Port D Data Register Port D Data Direction Register Port D Alternate Register 1 Port D Alternate Register 2
Notes: 1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer timeout reset, the Watch-Dog Timer Control register is reset to 20h. 2. When the CPU reads this register, the current sampled value of the port is read. 3. Read-only if RTC is locked Read / Write if RTC is unlocked. 4. After an external pin reset or a WDT reset, the RTC Control register is reset to x0xxxx00b. After an RTC Alarm Sleep-Mode Recovery reset, the RTC Control register is reset to x0xxxx10b.
PS013011-0204
Register Map
eZ80L92 Product Specification
Table 3. Register Map (Continued) Address (hex) Mnemonic Reset (hex) CPU Access Page #
Notes: 1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer timeout reset, the Watch-Dog Timer Control register is reset to 20h. 2. When the CPU reads this register, the current sampled value of the port is read. 3. Read-only if RTC is locked Read / Write if RTC is unlocked. 4. After an external pin reset or a WDT reset, the RTC Control register is reset to x0xxxx00b. After an RTC Alarm Sleep-Mode Recovery reset, the RTC Control register is reset to x0xxxx10b.
PS013011-0204
Register Map
eZ80L92 Product Specification
Table 3. Register Map (Continued) Address (hex) Mnemonic Reset (hex) CPU Access Page #
Notes: 1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer timeout reset, the Watch-Dog Timer Control register is reset to 20h. 2. When the CPU reads this register, the current sampled value of the port is read. 3. Read-only if RTC is locked Read / Write if RTC is unlocked. 4. After an external pin reset or a WDT reset, the RTC Control register is reset to x0xxxx00b. After an RTC Alarm Sleep-Mode Recovery reset, the RTC Control register is reset to x0xxxx10b.
PS013011-0204
Register Map
eZ80L92 Product Specification
Table 3. Register Map (Continued) Address (hex) Mnemonic Reset (hex) CPU Access Page #
Notes: 1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer timeout reset, the Watch-Dog Timer Control register is reset to 20h. 2. When the CPU reads this register, the current sampled value of the port is read. 3. Read-only if RTC is locked Read / Write if RTC is unlocked. 4. After an external pin reset or a WDT reset, the RTC Control register is reset to x0xxxx00b. After an RTC Alarm Sleep-Mode Recovery reset, the RTC Control register is reset to x0xxxx10b.
PS013011-0204
Register Map
eZ80L92 Product Specification
Table 3. Register Map (Continued) Address (hex) Mnemonic Reset (hex) CPU Access Page #
Notes: 1. After an external pin reset, the Watch-Dog Timer Control register is reset to 00h. After a Watch-Dog Timer timeout reset, the Watch-Dog Timer Control register is reset to 20h. 2. When the CPU reads this register, the current sampled value of the port is read. 3. Read-only if RTC is locked Read / Write if RTC is unlocked. 4. After an external pin reset or a WDT reset, the RTC Control register is reset to x0xxxx00b. After an RTC Alarm Sleep-Mode Recovery reset, the RTC Control register is reset to x0xxxx10b.
PS013011-0204
Register Map
eZ80L92 Product Specification
eZ80® CPU Core
The eZ80® CPU is the first 8-bit microprocessor to support 16 MB linear addressing. Each software module or task under a real-time executive or operating system can operate in Z80-compatible (64 KB) mode or full 24-bit (16 MB) address mode. The eZ80® CPU instruction set is a superset of the instruction sets for the Z80 and Z180 CPUs. Z80 and Z180 programs can be executed on an eZ80® CPU with little or no modification.
Features
· · · · · · · · Code-compatible with Z80 and Z180 products 24-bit linear address space Single-cycle instruction fetch Pipelined fetch, decode, and execute Dual Stack Pointers for ADL (24-bit) and Z80 (16-bit) memory modes 24-bit CPU registers and ALU (Arithmetic Logic Unit) Debug support Nonmaskable Interrupt (NMI), plus support for 128 maskable vectored interrupts
New and Improved Instructions
· Four new block transfer instructions provide DMA-like operations for memory to I / O and I / O to memory transfers. These new instructions are: - INDRX (input from I / O, decrement the memory address, leave the I / O address unchanged, and repeat) - INIRX (input from I / O, increment the memory address, leave the I / O address unchanged, and repeat) - OTDRX (output to I / O, decrement the memory address, leave the I / O address unchanged, and repeat) - OTIRX (output to I / O, increment the memory address, leave the I / O address unchanged, and repeat)
PS013011-0204
eZ80® CPU Core
eZ80L92 Product Specification
Four other block transfer instructions are modified to improve performance relative to the eZ80190 device. These modified instructions are: - IND2R (input from I / O, decrement the memory address, decrement the I / O address, and repeat) - INI2R (input from I / O, increment the memory address, increment the I / O address, and repeat) - OTD2R (output to I / O, decrement the memory address, decrement the I / O address, and repeat) - OTI2R (output to I / O, increment the memory address, increment the I / O address, and repeat)
For more information on the eZ80® CPU, its instruction set, and eZ80® programming, please refer to the eZ80 CPU User Manual. For more information on the eZ80190, please refer to the eZ80190 Product Specification.
PS013011-0204
eZ80® CPU Core
eZ80L92 Product Specification
Reset
RESET Operation
The RESET controller within the eZ80L92 provides a consistent system reset (RESET) function for all type of resets that may affect the system. There are 4 events which can cause a RESET: · · · · External RESET pin assertion Watch-Dog Timer (WDT) time-out when configured to generate a RESET Real-Time Clock alarm with the eZ80® CPU in low-power SLEEP mode Execution of a Debug RESET command
During RESET, an internal RESET mode timer holds the system in RESET for 257 system clock (SCLK) cycles. The RESET mode timer begins incrementing on the next rising edge of SCLK following deactivation of all RESET events (RESET pin, Watch-Dog Timer, Real-Time Clock, Debugger) Note: User must determine is 257 SCLK cycles provides sufficient time for the primary crystal oscillator to stabilize. RESET, via the external RESET pin, must always be executed following application of power (VDD ramp). Without RESET following power-up, proper operation of the eZ80L92 cannot be guaranteed.
PS013011-0204
Reset
eZ80L92 Product Specification
Low-Power Modes
Overview
The eZ80L92 provides a range of power-saving features. The highest level of power reduction is provided by SLEEP mode. The next level of power reduction is provided by the HALT instruction. The lowest level of power reduction is provided by the clock peripheral power-down registers.
SLEEP Mode
The eZ80® CPU can be brought out of SLEEP mode by any of the following operations: · · · · RESET via the external RESET pin driven Low RESET via a Real-Time Clock alarm RESET via a Watch-Dog Timer time-out (if running off of the 32 KHz oscillator and configured to generate a RESET upon time-out) RESET via execution of a Debug RESET command
After exiting SLEEP mode, the standard RESET delay occurs to allow the primary crystal oscillator to stabilize. Refer to the Reset section on page 34 for more information.
PS013011-0204
Low-Power Modes
eZ80L92 Product Specification
HALT Mode
The eZ80® CPU can be brought out of HALT mode by any of the following operations: · · · · · Nonmaskable interrupt (NMI) Maskable interrupt RESET via the external RESET pin driven Low Watch-Dog Timer time-out (if configured to generate either an NMI or RESET upon time-out) RESET via execution of a Debug RESET command
To minimize current in HALT mode, the system clock should be disabled for all unused on-chip peripherals via the Clock Peripheral Power-Down Registers.
Clock Peripheral Power-Down Registers
To reduce power, the Clock Peripheral Power-Down Registers allow the system clock to be disabled to unused on-chip peripherals. Upon RESET, all peripherals are enabled. The clock to unused peripherals can be disabled by setting the appropriate bit in the Clock Peripheral Power-Down Registers to 1. When powered down, the peripherals are completely disabled. To reenable, the bit in the Clock Peripheral Power-Down Registers must be cleared to 0. Many peripherals feature separate enable / disable control bits that must be appropriately set for operation. These peripheral specific enable / disable bits do not provide the same level of power reduction as the Clock Peripheral Power-Down Registers. When powered down, the standard peripheral control registers are not accessible for read or write access. See Tables 4 and 5.
PS013011-0204
Low-Power Modes
eZ80L92 Product Specification
Value Description 1 0 1 0 1 0 1 0 1 0 1 0 1 0 System clock to GPIO Port D is powered down. Port D alternate functions do not operate correctly. System clock to GPIO Port D is powered up. System clock to GPIO Port C is powered down. Port C alternate functions do not operate correctly. System clock to GPIO Port C is powered up. System clock to GPIO Port B is powered down. Port B alternate functions do not operate correctly. System clock to GPIO Port B is powered up. Reserved. System clock to SPI is powered down. System clock to SPI is powered up. System clock to I2C is powered down. System clock to I2C is powered up. System clock to UART1 is powered down. System clock to UART1 is powered up. System clock to UART0 and IrDA endec is powered down. System clock to UART0 and IrDA endec is powered up.
PS013011-0204
Low-Power Modes
eZ80L92 Product Specification
Value Description 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 PHI Clock output is disabled (output is high-impedance). PHI Clock output is enabled. Reserved. System clock to PRT5 is powered down. System clock to PRT5 is powered up. System clock to PRT4 is powered down. System clock to PRT4 is powered up. System clock to PRT3 is powered down. System clock to PRT3 is powered up. System clock to PRT2 is powered down. System clock to PRT2 is powered up. System clock to PRT1 is powered down. System clock to PRT1 is powered up. System clock to PRT0 is powered down. System clock to PRT0 is powered up.
PS013011-0204
Low-Power Modes
eZ80L92 Product Specification
General-Purpose Input / Output
GPIO Overview
The eZ80L92 features 24 General-Purpose Input / Output (GPIO) pins. The GPIO pins are assembled as three 8-bit ports- Port B, Port C, and Port D. All port signals can be configured for use as either inputs or outputs. In addition, all of the port pins can be used as vectored interrupt sources for the eZ80® CPU.
GPIO Operation
PS013011-0204
General-Purpose Input / Output
eZ80L92 Product Specification
Output 0 1 High impedance High impedance 0 High impedance High impedance 1 High impedance High impedance
Port B, C, or D-alternate function controls port I / O. Port B, C, or D-alternate function controls port I / O. Interrupt-active Low Interrupt-active High High impedance High impedance
Interrupt-falling edge triggered High impedance Interrupt-rising edge triggered High impedance
GPIO Mode 1. The port pin is configured as a standard digital output pin. The
GPIO Mode 2. The port pin is configured as a standard digital input pin. The output
GPIO Mode 3. The port pin is configured as open-drain I / O. The GPIO pins do not
feature an internal pull-up to the supply voltage. To employ the GPIO pin in OPEN-DRAIN mode, an external pull-up resistor must connect the pin to the supply voltage. Writing a 0 to the Port x Data register outputs a Low at the pin. Writing a 1 to the Port x Data register results in high-impedance output.
GPIO Mode 4. The port pin is configured as open-source I / O. The GPIO pins do
not feature an internal pull-down to the supply ground. To employ the GPIO pin in OPEN-SOURCE mode, an external pull-down resistor must connect the pin to the
PS013011-0204
General-Purpose Input / Output
eZ80L92 Product Specification
supply ground. Writing a 1 to the Port x Data register outputs a High at the pin. Writing a 0 to the Port x Data register results in a high-impedance output.
GPIO Mode 5. Reserved. This pin produces high-impedance output. GPIO Mode 6. This bit enables a dual edge-triggered interrupt mode. Both a rising
and a falling edge on the pin cause an interrupt request to be sent to the eZ80® CPU. Writing a 1 to the Port x Data register bit position resets the corresponding interrupt request. Writing a 0 produces no effect. The programmer must set the Port x Data register before entering the edge-triggered interrupt mode.
GPIO Mode 7. For Ports B, C, and D, the port pin is configured to pass control over
GPIO Mode 8. The port pin is configured for level-sensitive interrupt modes. An
interrupt request is generated when the level at the pin is the same as the level stored in the Port x Data register. The port pin value is sampled by the system clock. The input pin must be held at the selected interrupt level for a minimum of 2 clock periods to initiate an interrupt. The interrupt request remains active as long as this condition is maintained at the external source.
GPIO Mode 9. The port pin is configured for single edge-triggered interrupt mode.
The value in the Port x Data register determines if a positive or negative edge causes an interrupt request. A 0 in the Port x Data register bit sets the selected pin to generate an interrupt request for falling edges. A 1 in the Port x Data register bit sets the selected pin to generate an interrupt request for rising edges. The interrupt request remains active until a 1 is written to the corresponding interrupt request of the Port x Data register bit. Writing a 0 produces no effect on operation. The programmer must set the Port x Data register before entering the edge-triggered interrupt mode. A simplified block diagram of a GPIO port pin is illustrated in Figure 3.
PS013011-0204
General-Purpose Input / Output
eZ80L92 Product Specification
GPIO Register Data (Input) Q D Q D
System Clock VDD Mode 1 Mode 4 Data Bus System Clock GPIO Register Data (Output) Mode 1 Mode 3 GND D Q Port Pin
Figure 3. GPIO Port Pin Block Diagram
GPIO Interrupts
Each port pin can be used as an interrupt source. Interrupts can be either level- or edge-triggered. Level-Triggered Interrupts When the port is configured for level-triggered interrupts, the corresponding port pin is tristated. An interrupt request is generated when the level at the pin is the same as the level stored in the Port x Data register. The port pin value is sampled by the system clock. The input pin must be held at the selected interrupt level for a minimum of 2 consecutive clock cycles to initiate an interrupt. The interrupt request remains active as long as this condition is maintained at the external source. For example, if PD3 is programmed for low-level interrupt and the pin is forced Low for 2 consecutive clock cycles, an interrupt request signal is generated from that port pin and sent to the eZ80® CPU. The interrupt request signal remains active until the external device driving PD3 forces the pin High. Edge-Triggered Interrupts When the port is configured for edge-triggered interrupts, the corresponding port pin is tristated. If the pin receives the correct edge from an external device, the
PS013011-0204
General-Purpose Input / Output
eZ80L92 Product Specification
GPIO Control Registers
The 12 GPIO Control Registers operate in groups of four with a set for each Port (B, C, and D). Each GPIO port features a Port Data register, Port Data Direction register, Port Alternate register 1, and Port Alternate register 2. Port x Data Registers When the port pins are configured for one of the output modes, the data written to the Port x Data registers, detailed in Table 7, are driven on the corresponding pins. In all modes, reading from the Port x Data registers always returns the current sampled value of the corresponding pins. When the port pins are configured as edge-triggered interrupt sources, writing a 1 to the corresponding bit in the Port x Data register clears the interrupt signal that is sent to the eZ80® CPU. When the port pins are configured for edge-selectable interrupts or level-sensitive interrupts, the value written to the Port x Data register bit selects the interrupt edge or interrupt level. See Table 6 for more information.
PS013011-0204
General-Purpose Input / Output
eZ80L92 Product Specification
Port x Data Direction Registers In conjunction with the other GPIO Control Registers, the Port x Data Direction registers, detailed in Table 8, control the operating modes of the GPIO port pins. See Table 6 for more information.
Port x Alternate Register 1 In conjunction with the other GPIO Control Registers, the Port x Alternate Register 1, detailed in Table 9, control the operating modes of the GPIO port pins. See Table 6 for more information.
Port x Alternate Register 2 In conjunction with the other GPIO Control Registers, the Port x Alternate Register 2, detailed in Table 10, control the operating modes of the GPIO port pins. See Table 6 for more information.
PS013011-0204
General-Purpose Input / Output
eZ80L92 Product Specification
Interrupt Controller
The interrupt controller on the eZ80L92 routes the interrupt request signals from the internal peripherals and external devices (via the GPIO pins) to the eZ80® CPU.
Maskable Interrupts
Table 11. Interrupt Vector Sources by Priority Vector 00h 02h 04h 06h 08h 0Ah 0Ch 0Eh 10h 12h 14h 16h 18h Source Unused Unused Unused Unused Unused PRT 0 PRT 1 PRT 2 PRT 3 PRT 4 PRT 5 RTC UART 0 Vector 1Ah 1Ch 1Eh 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h Source UART 1 I2C SPI Unused Unused Unused Unused Unused Unused Unused Unused Port B 0 Port B 1 Vector 34h 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch Source Port B 2 Port B 3 Port B 4 Port B 5 Port B 6 Port B 7 Port C 0 Port C 1 Port C 2 Port C 3 Port C 4 Port C 5 Port C 6 Vector 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h 62h 64h 66h Source Port C 7 Port D 0 Port D 1 Port D 2 Port D 3 Port D 4 Port D 5 Port D 6 Port D 7 Unused Unused Unused Unused
Note: Absolute locations 00h, 08h, 10h, 18h, 20h, 28h, 30h, 38h, and 66h are reserved for hardware reset, NMI, and the RST instruction.
PS013011-0204
Interrupt Controller
eZ80L92 Product Specification