High performance 32-bit/40-bit floating point processor optimized prof

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High performance 32-bit/40-bit floating point processor optimized prof

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SUMMARY
High performance 32-bit/40-bit floating point processor optimized professional audio processing MHz/1800 MFLOPs, with unique audio centric peripherals such Digital Audio Interface that includes high-precision 8-channel asynchronous sample rate converter among others, ADSP-21364 SHARC ideal applications that require industry leading equalization, reverberation other effects processing Single-Instruction Multiple-Data (SIMD) computational architecture 32-bit IEEE floating-point/32-bit fixed-point/40-bit extended precision floating-point computational units, each with multiplier, ALU, shifter, register file On-chip memory-3M Bits on-chip SRAM
SHARC® Processor ADSP-21364
Code compatible with other members SHARC family ADSP-21364 available core instruction rate. complete ordering information, Ordering Guide page
Figure Functional Block Diagram Processor Core
BLOCKS MEMORY
CORE PROCESSOR
TIMER INSTRUCTION CACHE 48-BIT
BLOCK
BLOCK
SRAM MBIT
BLOCK
BLOCK
SRAM MBIT
SRAM MBIT
SRAM MBIT
DAG1 8X4X32
DAG2 8X4X32
PROGRAM SEQUENCER
ADDR
DATA
ADDR
DATA
ADDR
DATA
ADDR
DATA
ADDRESS ADDRESS DATA
DATA
REGISTER
PROCESSING ELEMENT (PEX) PROCESSING ELEMENT (PEY)
REGISTERS (MEMORY MAPPED)
SPORTS TIMERS
SIGNAL ROUTING UNIT
JTAG TEST EMULATION
PROCESSOR PERIPHERALS
"ADSP-21364 MEMORY INTERFACE FEATURES" SECTION DETAILS
SHARC SHARC logo registered trademarks Analog Devices, Inc.
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Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective companies.
Technology Way, P.O. 9106, Norwood, 02062-9106 U.S.A. Tel:781/329-4700 www.analog.com Fax:781/326-8703 2004 Analog Devices, Inc. rights reserved.
ADSP-21364
FEATURES PROCESSOR CORE
(3.33 core instruction rate, ADSP-21364 performs 1800 MFLOPS/600 MMACS Mbits on-chip dual-ported SRAM blocks 0.50M blocks simultaneous access core processor Dual Data Address Generators (DAGs) with modulo bitreverse addressing Zero-overhead looping with single-cycle loop setup, providing efficient program sequencing Single Instruction Multiple Data (SIMD) architecture provides: computational processing elements Concurrent execution Code compatibility with other SHARC family members assembly level Parallelism busses computational units allows: Single cycle executions (with without SIMD) multiply operation, operation, dual memory read write, instruction fetch Transfers between memory core sustained Gbytes/s bandwidth core instruction rate
stream support, each with channels frame Companding selection channel basis mode Input Data Port provides additional input path SHARC core, configurable channels serial data channels serial data single channel 20bit wide parallel data Signal Routing Unit provides configurable flexible connections between components-six serial ports, precision clock generators, input data port with data acquisition port, port, eight channels asynchronous sample rate converters, three timers, interrupts, flag inputs, flag outputs, pins (DAI_Px) Serial Peripheral Interfaces (SPI): primary dedicated pins, secondary pins Master slave serial boot through primary Full-duplex operation Master-Slave mode multi-master support Open drain outputs Programmable baud rates, clock polarities phases Muxed Flag/IRQ lines Muxed Flag/Timer expired line
ADSP-21364 FEATURES
Controller supports: zero-overhead channels transfers between ADSP-21364 internal memory variety peripherals 32-bit transfers core clock speed, parallel with fullspeed processor execution Asynchronous parallel port provides access asynchronous external memory multiplexed address/data lines support 24-bit address external address range with 8-bit data 16-bit address external address range with 16-bit data Mbyte transfer rate word page boundaries External memory access dedicated channel 32-bit word packing options Programmable wait state options: CCLK Digital Audio Interface (DAI) includes serial ports, Precision Clock Generators, Input Data Port, three timers, 8-channel asynchronous sample rate converter, Signal Routing Unit dual data line serial ports that operate Mbits/s each data line each clock, frame sync data lines that configured either receiver transmitter pair Left-justified Sample Pair Support, programmable direction simultaneous receive transmit channels using compatible stereo devices serial port support telecommunications interfaces including channel support newer telephony interfaces such H.100/H.110
DEDICATED AUDIO COMPONENTS
Sample Rate Converter (SRC) Contains Serial Input Port, Deemphasis Filter providing -140db performance, Sample Rate Converter (SRC) Serial Output Port Supports Left Justified, I2S, Right Justified serial formats (input) Pulse Width Modulation provides: outputs configured four groups four outputs Supports center-aligned edge-aligned waveforms generate complementary signals outputs paired mode independent signals non-paired mode wide variety software hardware multiplier/divider ratios Dual voltage: I/O, core Available 136-ball Package
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GENERAL DESCRIPTION
ADSP-21364 SHARC member SIMD SHARC family DSPs that feature Analog Devices' Super Harvard Architecture. ADSP-21364 source code compatible with ADSP-2126x, ADSP-2116x, DSPs well with first generation ADSP-2106x SHARC processors SISD (Single-Instruction, Single-Data) mode. ADSP-21364 32bit/40-bit floating point processor optimized professional audio applications with large on-chip SRAM, multiple internal buses eliminate bottlenecks, innovative Digital Audio Interface (DAI). shown functional block diagram page ADSP-21364 uses computational units deliver significant performance increase over previous SHARC processors range algorithms. Fabricated state-of-the-art, high speed, CMOS process, ADSP-21364 achieves instruction cycle time 3.33 MHz. With SIMD computational hardware, ADSP-21364 perform 1800 MFLOPS running MHz. Table shows performance benchmarks ADSP-21364. Table ADSP-21364 Benchmarks MHz)
Benchmark Algorithm 1024 Point Complex (Radix with reversal) Filter (per tap)1 Filter (per biquad)1 Matrix Multiply (pipelined) [3x3] [3x1] [4x4] [4x1] Divide Inverse Square Root
ADSP-21364
Three Programmable Interval Timers with Generation, Capture/Pulse width Measurement, External Event Counter Capabilities On-Chip SRAM Bits) 16-bit Parallel port that supports interfaces off-chip memory peripherals JTAG test access port block diagram ADSP-21364 page illustrates following architectural features: controller full duplex serial ports SPI-compatible interface Digital Audio Interface that includes precision clock generators (PCG), input data port (IDP), eight channels asynchronous sample rate converters, serial ports, eight serial interfaces, 20-bit parallel input port, interrupts, flag outputs, flag inputs, three timers, flexible signal routing unit (SRU) Figure page shows sample configuration SPORT using precision clock generators interface with with much lower jitter clock than serial port would generate itself. Many other configurations possible.
Speed MHz) 1.67 6.60 26.60 11.66 18.15
ADSP-21364 FAMILY CORE ARCHITECTURE
ADSP-21364 code compatible assembly level with ADSP-2126x, ADSP-21160 ADSP-21161, with first generation ADSP-2106x SHARC DSPs. ADSP-21364 shares architectural features with ADSP-2126x ADSP-2116x SIMD SHARC family DSPs, detailed following sections.
Assumes files multichannel SIMD mode
SIMD Computational Engine
ADSP-21364 contains computational processing elements that operate Single-Instruction Multiple-Data (SIMD) engine. processing elements referred each contains ALU, multiplier, shifter register file. always active, enabled setting PEYEN mode MODE1 register. When this mode enabled, same instruction executed both processing elements, each processing element operates different data. This architecture efficient executing math intensive algorithms. Entering SIMD mode also effect data transferred between memory processing elements. When SIMD mode, twice data bandwidth required sustain computational operation processing elements. Because this requirement, entering SIMD mode also doubles bandwidth between memory processing elements. When using DAGs transfer data SIMD mode, data values transferred with each access memory register file.
ADSP-21364 continues SHARC's industry leading standards integration DSPs, combining high performance 32-bit core with integrated, on-chip system features. These features include Mbits on-chip SRAM memory, processor that supports channels, serial ports, interface, external parallel bus, Digital Audio Interface (DAI). block diagram ADSP-21364 page illustrates following architectural features: processing elements, each which comprises ALU, Multiplier, Shifter Data Register File Data Address Generators (DAG1, DAG2) Program sequencer with instruction cache buses capable supporting four 32-bit data transfers between memory core every core processor cycle
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ADSP-21364
ADSP-21364
CLKOUT CLOCK CLKIN XTAL CLK_CFG1-0 BOOTCFG1-0 FLAG3-1 FLAG0 (OPTIONAL) SDAT AD15-0
LATCH
ADDR DATA
PARALLEL PORT DEVI
CONTROL
DATA
ADDRESS
DAI_P1 DAI_P2 DAI_P3 DAI_P18 DAI_P19 DAI_P20 SCLK0 SFS0 SD0A SD0B SPORT1 SPORT2 SPORT SPORT4 SPORT5
(OPTIONAL) SDAT
RESET
PCGA
JTAG
Figure ADSP-21364 System Sample Configuration
Independent, Parallel Computation Units
Within each processing element computational units. computational units consist arithmetic/logic unit (ALU), multiplier shifter. These units perform operations single cycle. three units within each processing element arranged parallel, maximizing computational throughput. Single multi-function instructions execute parallel multiplier operations. SIMD mode, parallel multiplier operations occur both processing elements. These computation units support IEEE 32-bit singleprecision floating-point, 40-bit extended precision floatingpoint, 32-bit fixed-point data formats.
Single-Cycle Fetch Instruction Four Operands
ADSP-21364 features enhanced Harvard architecture which data memory (DM) transfers data program memory (PM) transfers both instructions data (see Figure page With ADSP-21364's separate program data memory buses on-chip instruction cache, processor simultaneously fetch four operands (two over each data bus) instruction (from cache), single cycle.
Instruction Cache
ADSP-21364 includes on-chip instruction cache that enables three-bus operation fetching instruction four data values. cache selective-only instructions whose fetches conflict with data accesses cached. This cache allows full-speed execution core, looped operations such digital filter multiply-accumulates butterfly processing.
Data Register File
general purpose data register file contained each processing element. register files transfer data between computation units data buses, store intermediate results. These 10-port, 32-register primary, secondary) register files, combined with ADSP-2136x enhanced Harvard architecture, allow unconstrained data flow between computation units internal memory. registers referred R0-R15 S0-S15.
Data Address Generators With Zero-Overhead Hardware Circular Buffer Support
ADSP-21364's data address generators (DAGs) used indirect addressing implementing circular data buffers hardware. Circular buffers allow efficient programming delay lines other data structures required digital
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signal processing, commonly used digital filters Fourier transforms. DAGs ADSP-21364 contain sufficient registers allow creation circular buffers primary register sets, secondary). DAGs automatically handle address pointer wrap-around, reduce overhead, increase performance, simplify implementation. Circular buffers start memory location.
PROCESSOR BUSSES SYSTEM MEMORY DATA (32) ADDRESS (18) FLAGS/IRQ/TIMEXP CONTROLLER
ADSP-21364
Flexible Instruction
48-bit instruction word accommodates variety parallel operations, concise programming. example, ADSP-21364 conditionally execute multiply, add, subtract both processing elements while branching, fetching four 32-bit values from memory-all single instruction.
CONTROL, STATUS, DATA BUFFERS
OL/G
PARALLEL (16) PORT REGISTERS (MEMORY MAPPED) PORT
ADSP-21364 MEMORY INTERFACE FEATURES
ADSP-21364 adds following architectural features SIMD SHARC family core:
SIGNAL ROUTING UNIT
SERIAL PORTS INPUT DATA PORTS
On-Chip Memory
ADSP-21364 contains three megabits internal SRAM. Each block configured different combinations code data storage (see Figure page Each memory block supports single-cycle, independent accesses core processor processor. ADSP-21364 memory architecture, combination with separate on-chip buses, allow data transfers from core from processor, single cycle. ADSP-21364's, SRAM configured maximum words 32-bit data, 192K words 16-bit data, words 48-bit instructions 40-bit data), combinations different word sizes three megabits. memory accessed 16-bit, 32-bit, 48-bit, 64-bit words. 16-bit floating-point storage format supported that effectively doubles amount data that stored on-chip. Conversion between 32-bit floating-point 16-bit floating-point formats performed single instruction. While each memory block store combinations code data, accesses
CHANNELS) PRECISI CLOCK GENERATORS TIMERS
DIGITAL AUDIO INTERFACE PROCESSOR
Figure ADSP-21364 Processor Peripherals Block Diagram
most efficient when block stores data using transfers, other block stores instructions data using transfers. Using buses, with dedicated each memory block assures single-cycle execution with data transfers. this case, instruction must available cache.
Figure ADSP-21364 Memory
Controller
ADSP-21364's on-chip controller allows data transfers without processor intervention. controller operates independently invisibly processor core, allowing operations occur while core simultaneously executing program instructions. transfers occur between ADSP-21364's internal memory serial ports, SPI-compatible (Serial Peripheral Interface) ports, (Input Data Port), parallel data acquisition port parallel port. Twenty-three channels available
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ADSP-21364 interface, twelve serial ports, eight Input Data Port, processor's parallel port. Programs downloaded ADSP-21364 using transfers. Other features include interrupt generation upon completion transfers, chaining automatic linked transfers.
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ADSP-21364
Digital Audio Interface (DAI)
Digital Audio Interface (DAI) provides ability connect various peripherals SHARCs pins (DAI_P[20:1]). Programs make these connections using Signal Routing Unit (SRU, shown Figure matrix routing unit group multiplexers) that enables peripherals provided interconnected under software control. This allows easy associated peripherals much wider variety applications using larger algorithms than possible with nonconfigurable signal paths. also includes serial ports, precision clock generator (PCG), eight channels asynchronous sample rate converters, input data port (IDP), port, flag outputs flag inputs, three timers. provides additional input path ADSP-21364 core, configurable either eight channels serial data seven channels plus single 20-bit wide synchronous parallel data acquisition port. Each data channel channel that independent from ADSP-21364's serial ports. complete information using DAI, ADSP2136x SHARC Peripherals Reference.
Each serial ports supports Left-justified Sample Pair protocols (I2S industry standard interface commonly used audio codecs, ADCs DACs such Analog Devices AD183x family), with data pins, allowing four Left-justified Sample Pair channels (using stereo devices) serial port, with maximum channels. serial ports permit little-endian big-endian transmission formats word lengths selectable from bits bits. Left-justified Sample Pair modes, dataword lengths selectable between bits bits. Serial ports offer selectable synchronization transmit modes well optional µ-law A-law companding selection channel basis. Serial port clocks frame syncs internally externally generated.
Parallel Port
Parallel Port provides interfaces SRAM peripheral devices. multiplexed address data pins (AD15-0) access 8-bit devices with bits address, 16-bit devices with bits address. either mode, 16bit, maximum data transfer rate Mbytes/sec. transfers used move data from internal memory. Access core also facilitated through parallel port register read/write functions. (Address Latch Enable) pins control pins parallel port.
Serial Ports
ADSP-21364 features synchronous serial ports that provide inexpensive interface wide variety digital mixed-signal peripheral devices such Analog devices AD183x family audio codecs, ADCs, DACs. serial ports made data lines, clock frame sync. data lines programmed either transmit receive each data line dedicated channel. Serial ports enabled programmable simultaneous receive transmit pins that support transmit receive channels audio data when SPORTS enabled, full duplex streams channels frame. serial ports operate maximum data rate Mbits/s. Serial port data automatically transferred from on-chip memory dedicated channels. Each serial ports work conjunction with another serial port provide support. SPORT provides transmit signals while other SPORT provides receive signals. frame sync clock shared. Serial ports operate four modes: Standard serial mode Multichannel (TDM) mode mode Left-justified sample pair mode Left-justified Sample Pair Mode mode which each Frame Sync cycle samples data transmitted/received sample high segment frame sync, other segment frame sync. user control over various attributes this mode.
Serial Peripheral (Compatible) Interface
ADSP-21364 SHARC processor contains Serial Peripheral Interface ports (SPI). industry standard synchronous serial link, enabling ADSP-21364 compatible port communicate with other compatible devices. consists data pins, device select pin, clock pin. full-duplex synchronous serial interface, supporting both master slave modes. port operate multi-master environment interfacing with four other compatible devices, either acting master slave device. ADSP-21364 compatible peripheral implementation also features programmable baud rate clock phase polarities. ADSP-21364 compatible port uses open drain drivers support multi-master configuration avoid data contention. sample rate converter (SRC) contains four blocks same core that used AD1896 Stereo Asynchronous Sample Rate Converter providing 128dB SNR. block used perform synchronous asynchronous sample rate conversion across independent stereo channels, without using internal processor resources. four blocks also configured operate together convert multi-channel audio data without phase mismatches. Finally, used clean audio data from jittery clock sources such S/PDIF receiver.
Pulse Width Modulation
module flexible, programmable, waveform generator that programmed generate required switching patterns various applications related motor control, electronic valve control audio power control.
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generator generate either center-aligned edgealigned waveforms. addition, generate complementary signals outputs paired mode independent signals non-paired mode (applicable single group four waveforms). entire module four groups four outputs each. Therefore this module generates outputs total. Each group produces pairs signals four outputs. generator capable operating distinct modes while generating center-aligned waveforms: single update mode double update mode. single update mode duty cycle values programmable only once period. This results patterns that symmetrical around mid-point period. double update mode, second updating registers implemented midpoint period. this mode, possible produce asymmetrical patterns that produce lower harmonic distortion three-phase inverters.
ADSP-21364
Power Supplies
ADSP-21364 separate power supply connections internal (VDDINT), external (VDDEXT), analog (AVDD/AVSS) power supplies. internal analog supplies must meet 1.2V requirement. external supply must meet 3.3V requirement. external supply pins must connected same power supply. Note that analog supply (AVDD) powers ADSP-21364's clock generator PLL. produce stable clock, should provide external circuit filter power input AVDD pin. Place filter close possible pin. example circuit, Figure prevent noise coupling, wide trace analog ground (AVSS) signal install decoupling capacitor close possible pin. Note that AVSS AVDD pins specified Figure inputs analog ground plane board.
VDDINT 0.01 AVDD
Timers
ADSP-21364 total four timers: core timer able generate periodic interrupts three general purpose timers that that generate periodic interrupts independently operate three modes: Pulse Waveform Generation mode Pulse Width Count /Capture mode External Event Watchdog mode core timer configured FLAG3 Timer Expired signal, each general purpose timer bidirectional four registers that implement mode operation: 6-bit configuration register, 32-bit count register, 32-bit period register, 32-bit pulse width register. single control status register enables disables three general purpose timers independently.
AVSS
Figure Analog Power (AVDD) Filter Circuit
Target Board JTAG Emulator Connector
Analog Devices Tools product line JTAG emulators uses IEEE 1149.1 JTAG test access port ADSP-21364 processor monitor control target board processor during emulation. Analog Devices Tools product line JTAG emulators provides emulation full processor speed, allowing inspection modification memory, registers, processor stacks. processor's JTAG interface ensures that emulator will affect target system loading timing. complete information Analog Devices' SHARC Tools product line JTAG emulator operation, appropriate "Emulator Hardware User's Guide".
Program Booting
internal memory ADSP-21364 boots system power-up from 8-bit EPROM parallel port, master, slave internal boot. Booting determined Boot Configuration (BOOTCFG1-0) pins. Selection boot source controlled either master slave device.
DEVELOPMENT TOOLS
ADSP-21364 supported with complete CROSSCOREsoftware hardware development tools, including Analog Devices emulators VisualDSP++development environment. same emulator hardware that supports other SHARC processors also fully emulates ADSP-21364. VisualDSP++ project management environment lets programmers develop debug application. This environment includes easy assembler (which based algebraic syntax), archiver (librarian/library builder), linker, loader, cycle-accurate instruction-level simulator, C/C++ compiler, C/C++ runtime library that includes mathematical functions. point these tools C/C++ code efficiency. compiler been developed efficient
Phased Locked Loop
ADSP-21364 uses on-chip Phase-Locked Loop (PLL) generate internal clock core. power CLKCFG1-0 pins used select ratios 32:1, 16:1, 6:1. After booting, numerous other ratios selected software control. ratios made software configurable numerator values from software configurable divisor values
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ADSP-21364
translation C/C++ code assembly. SHARC architectural features that improve efficiency compiled C/C++ code. VisualDSP++ debugger number important features. Data visualization enhanced plotting package that offers significant level flexibility. This graphical representation user data enables programmer quickly determine performance algorithm. algorithms grow complexity, this capability have increasing significance designer's development schedule, increasing productivity. Statistical profiling enables programmer intrusively poll processor running program. This feature, unique VisualDSP++, enables software developer passively gather important code execution metrics without interrupting real-time characteristics program. Essentially, developer identify bottlenecks software quickly efficiently. using profiler, programmer focus those areas program that impact performance take corrective action. Debugging both C/C++ assembly programs with VisualDSP++ debugger, programmers can: View mixed C/C++ assembly code (interleaved source object information) Insert breakpoints conditional breakpoints registers, memory, stacks Trace instruction execution Perform linear statistical profiling program execution Fill, dump, graphically plot contents memory Perform source level debugging Create custom debugger windows VisualDSP++ IDDE lets programmers define manage software development. dialog boxes property pages programmers configure manage SHARC development tools, including color syntax highlighting VisualDSP++ editor. This capability permits programmers Control development tools process inputs generate outputs Maintain one-to-one correspondence with tool's command line switches VisualDSP++ Kernel (VDK) incorporates scheduling resource management tailored specifically address memory timing constraints programming. These capabilities enable engineers develop code more effectively, eliminating need start from very beginning, when developing application code. features include Threads, Critical Unscheduled regions, Semaphores, Events, Device flags. also supports Priority-based, Preemptive, Cooperative, Time-Sliced scheduling approaches. addition, designed scalable. application does specific feature, support code that feature excluded from target system.
Because library, developer decide whether not. integrated into VisualDSP++ development environment, also used standard command line tools. When used, development environment assists developer with many error-prone tasks assists managing system resources, automating generation various based objects, visualizing system state, when debugging application that uses VDK. VisualDSP++ Component Software Engineering (VCSE) Analog Devices technology creating, using, reusing software components (independent modules substantial functionality) quickly reliably assemble software applications. Download components from drop them into application. Publish component archives from within VisualDSP++. VCSE supports component implementation C/C++ assembly language. Expert Linker visually manipulate placement code data embedded system. View memory utilization color-coded graphical form, easily move code data different areas external memory with drag mouse, examine time stack heap usage. Expert Linker fully compatible with existing Linker Definition File (LDF), allowing developer move between graphical textual environments. addition software hardware development tools available from Analog Devices, third parties provide wide range tools supporting SHARC processor family. Hardware tools include SHARC processor plug-in cards. Third party software tools include libraries, real-time operating systems, block diagram design tools.
DESIGNING EMULATOR-COMPATIBLE BOARD (TARGET)
Analog Devices family emulators tools that every developer needs test debug hardware software systems. Analog Devices supplied IEEE 1149.1 JTAG Test Access Port (TAP) each JTAG DSP. Nonintrusive incircuit emulation assured processor's JTAG interface-the emulator does affect target system loading timing. emulator uses access internal features DSP, allowing developer load code, breakpoints, observe variables, observe memory, examine registers. must halted send data commands, once operation been completed emulator, system running full speed with impact system timing. these emulators, target board must include header that connects DSP's JTAG port emulator. details target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, emulator logic, EE-68: Analog Devices JTAG Emulation Technical Reference Analog Devices website (www.analog.com)- site search "EE-68." This document updated regularly keep pace with improvements emulator support.
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ADDITIONAL INFORMATION
This data sheet provides general overview ADSP-21364 architecture functionality. detailed information ADSP-2136x Family core architecture instruction set, refer ADSP-2136x Hardware Reference ADSP-21160 SHARC Instruction Reference.
ADSP-21364
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ADSP-21364
FUNCTION DESCRIPTIONS
ADSP-21364 definitions listed below. Inputs identified synchronous must meet timing requirements with respect CLKIN with respect TMS, TDI). Inputs identified asynchronous asserted asynchronously CLKIN TRST). pull unused inputs
VDDEXT GND, except following: DAI_Px, SPICLK, MISO, MOSI, EMU, TMS,TRST, AD15-0 (NOTE: These pins have pull-up resistors.) following symbols appear Type column Table Asynchronous, Ground, Input, Output, Power Supply, Synchronous, (A/D) Active Drive, (O/D) Open Drain, Three-State.
Table Descriptions
AD15-0 Type I/O/T State During After Reset Three-state with pull-up enabled Function
FLAG3-0
I/O/A
Parallel Port Address/Data. ADSP-21364 parallel port corresponding unit output addresses data peripherals these multiplexed pins. multiplex state determined pin. parallel port operate either 8-bit 16-bit mode. Each 22.5 internal pull-up resistor. Address Data Modes page details operation: 8-bit mode: automatically asserted whenever change occurs upper external address bits, A23-8; used conjunction with external latch retain values A23-8. 16-bit mode: automatically asserted whenever change occurs address bits, A15-0; used conjunction with external latch retain values A15-0. these pins flags (FLAGS15-0) PWMs (PWM15-0): (=1) SYSCTL register disable parallel port, (=1) bits 22-25 SYSCTL register enable FLAGS groups four (bit FLAGS30, FLAGS7-4 etc.) (=1) bits 26-29 SYSCTL register enable PWMs groups four (bit PWM0-3, PWM4-7, on). When used input, Channel0 these pins parallel input data. Output only, driven Parallel Port Read Enable. asserted whenever reads 8-bit 16high1 data from external memory device. When AD15-0 flags, this remains deasserted. Output only, driven Parallel Port Write Enable. asserted whenever writes 8-bit high1 16-bit data external memory device. When AD15-0 flags, this remains deasserted. Output only, driven Parallel Port Address Latch enable. asserted whenever drives low1 address parallel port address pins. reset, active high. However, reconfigured using software active low. When AD15-0 flags, this remains deasserted. Three-state Flag Pins. Each flag configured control bits either input output. input, tested condition. output, used signal external peripherals. These pins used interface slave select output during mastering. These pins also multiplexed with IRQx TIMEXP signals. master boot mode, FLAG0 slave select that must connected EPROM. FLAG0 configured slave select during master boot. When (=1) SYSCTL register, FLAG0 configured IRQ0. When (=1) SYSCTL register, FLAG1 configured IRQ1. When (=1) SYSCTL register, FLAG2 configured IRQ2. When (=1) SYSCTL register, FLAG3 configured TIMEXP which indicates that system timer expired.
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Table Descriptions (Continued)
DAI_P20-1 Type I/O/T State During After Reset Three-state with programmable pullup Function
ADSP-21364
SPICLK
Three-state with pull-up enabled
SPIDS
Input only
MOSI
(O/D)
Three-state with pull-up enabled
MISO
(O/D)
Three-state with pull-up enabled
BOOTCFG1-0
Input only
Digital Audio Interface Pins. These pins provide physical interface SRU. configuration registers define combination on-chip peripheral inputs outputs connected pin's output enable. configuration registers these peripherals then determines exact behavior pin. input output signal present routed these pins. provides connection from Serial ports, Input data port, precision clock generators timers, sample rate converters DAI_P20-1 pins These pins have internal 22.5 pull-up resistors which enabled reset. These pull-ups disabled DAI_PIN_PULLUP register. Serial Peripheral Interface Clock Signal. Driven master, this signal controls rate which data transferred. master transmit data variety baud rates. SPICLK cycles once each transmitted. SPICLK gated clock that active during data transfers, only length transferred word. Slave devices ignore serial clock slave select input driven inactive (HIGH). SPICLK used shift shift data driven MISO MOSI lines. data always shifted clock edge sampled opposite edge clock. Clock polarity clock phase relative data programmable into SPICTL control register define transfer format. SPICLK 22.5 internal pull-up resistor. Serial Peripheral Interface Slave Device Select. active signal used select slave device. This input signal behaves like chip select, provided master device slave devices. multi-master mode DSPs SPIDS signal driven slave device signal master) that error occurred, some other device also trying master device. asserted when device master mode, considered multi-master error. single-master, multiple-slave configuration where flag pins used, this must tied pulled high VDDEXT master device. ADSP-21364 ADSP-21364 interaction, master ADSP-21364's flag pins used drive SPIDS signal ADSP-21364 slave device. Master Slave ADSP-21364 configured master, MOSI becomes data transmit (output) pin, transmitting output data. ADSP-21364 configured slave, MOSI becomes data receive (input) pin, receiving input data. ADSP-21364 interconnection, data shifted from MOSI output master shifted into MOSI input(s) slave(s). MOSI 22.5 internal pull-up resistor. Master Slave Out. ADSP-21364 configured master, MISO becomes data receive (input) pin, receiving input data. ADSP-21364 configured slave, MISO becomes data transmit (output) pin, transmitting output data. ADSP-21364 interconnection, data shifted from MISO output slave shifted into MISO input master. MISO 22.5 internal pull-up resistor. MISO configured setting SPICTL register. Note: Only slave allowed transmit data given time. enable broadcast transmission multiple SPI-slaves, DSP's MISO disabled setting (=1) (DMISO) SPICTL register. Boot Configuration Select. This used select boot mode DSP. BOOTCFG pins must valid before reset asserted. Table description boot modes.
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ADSP-21364
Table Descriptions (Continued)
CLKIN Type State During After Reset Input only Function
XTAL CLKCFG1-0
Output only2 Input only
RSTOUT/CLKOUT
Output only
RESET
Input only
TRST
Input only3 Three-state with pull-up enabled Three-state with pull-up enabled Three-state4 Three-state with pull-up enabled Three-state with pull-up enabled
(O/D)
VDDINT VDDEXT AVDD
AVSS
Local Clock Used conjunction with XTAL. CLKIN ADSP-21364 clock input. configures ADSP-21364 either internal clock generator external clock source. Connecting necessary components CLKIN XTAL enables internal clock generator. Connecting external clock CLKIN while leaving XTAL unconnected configures ADSP-21364 external clock source such external clock oscillator. core clocked either output this clock input depending CLKCFG1-0 settings. CLKIN halted, changed, operated below specified frequency. Crystal Oscillator Terminal. Used conjunction with CLKIN drive external crystal. Core/CLKIN Ratio Control. These pins start clock frequency. Table description clock configuration modes. Note that operating frequency changed programming multiplier divider PMCTL register time after core comes reset. Local Clock Out/ Reset Out. Drives core reset signal external device. CLKOUT also configured reset pin.The functionality switched between output clock reset setting PMCTREG register. default reset out. Processor Reset. Resets ADSP-21364 known state. Upon deassertion, there 4096 CLKIN cycle latency lock. After this time, core begins program execution from hardware reset vector address. RESET input must asserted (low) power-up. Test Clock (JTAG). Provides clock JTAG boundary scan. must asserted (pulsed low) after power-up held proper operation ADSP-21364. Test Mode Select (JTAG). Used control test state machine. 22.5 internal pull-up resistor. Test Data Input (JTAG). Provides serial data boundary scan logic. 22.5 internal pull-up resistor. Test Data Output (JTAG). Serial scan output boundary scan path. Test Reset (JTAG). Resets test state machine. TRST must asserted (pulsed low) after power-up held proper operation ADSP-21364. TRST 22.5 internal pull-up resistor. Emulation Status. Must connected ADSP-21364 Analog Devices Tools product line JTAG emulators target board connector only. 22.5 internal pullup resistor. Core Power Supply. Nominally +1.2 supplies DSP's core processor pins package, pins LQFP package). Power Supply. Nominally +3.3 pins package, pins LQFP package). Analog Power Supply. Nominally +1.2 supplies DSP's internal (clock generator). This same specifications VDDINT, except that added filtering circuitry required. more information, Power Supplies page Analog Power Supply Return. Power Supply Return. pins package, pins LQFP package).
continuously driven won't three-stated. Output only three-state driver with output path always enabled. Input only three-state driver with both output path. Three-state three-state driver.
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ADDRESS DATA PINS FLAGS
these pins flags (FLAGS15-0) (=1) SYSCTL register disable parallel port. Table AD[15:0] Flag Mapping
AD10 AD11 AD12 AD13 AD14 AD15 Flag FLAG8 FLAG9 FLAG10 FLAG11 FLAG12 FLAG13 FLAG14 FLAG15 FLAG0 FLAG1 FLAG2 FLAG3 FLAG4 FLAG5 FLAG6 FLAG7
ADSP-21364
deasserted. 16-bit data transfers, latches address bits A15-A0 when asserted, followed data bits D15-D0 when deasserted. Table Address/ Data Mode Selection
Data Mode 8-bit 8-bit 16-bit 16-bit Asserted Deasserted Asserted Deasserted AD7-0 Function A15-8 D7-0 A7-0 D7-0 AD15-8 Function A23-16 A7-0 A15-8 D15-8
BOOT MODES
Table Boot Mode Selection
BOOTCFG1-0 Booting Mode Slave Boot Master Boot Parallel Port boot EPROM
CORE INSTRUCTION RATE CLKIN RATIO MODES
Table Core Instruction Rate/ CLKIN Ratio Selection
CLKCFG1-0 Core CLKIN Ratio 32:1 16:1
ADDRESS DATA MODES
following table shows functionality pins 8-bit 16-bit transfers parallel port. 8-bit data transfers, latches address bits A23-A8 when asserted, followed address bits A7-A0 data bits D7-D0 when
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ADSP-21364
ADSP-21364 SPECIFICATIONS
Timing measured signals when they cross level described Figure page delays nanoseconds) measured between point that first signal reaches point that second signal reaches
RECOMMENDED OPERATING CONDITIONS
Grade Parameter1 VDDINT AVDD VDDEXT CLOAD TAMB
Internal (Core) Supply Voltage Analog (PLL) Supply Voltage External (I/O) Supply Voltage High Level Input Voltage2, VDDEXT Level Input Voltage2 VDDEXT Load Capacitance Output Pins Ambient Operating Temperature3 1.14 1.14 3.13 -0.5
1.26 1.26 3.47 VDDEXT+0.5
Unit
Specifications subject change without notice. Applies input bidirectional pins: AD15-0, FLAG3-0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOTCFGx, CLKIN, CLKCFGx, RESET, TCK, TMS, TDI, TRST. Thermal Characteristics page information thermal specifications.
ELECTRICAL CHARACTERISTICS
Parameter1 IILPU IOZH IOZL IOZLPU IDD-INTYP AIDD
High Level Output Voltage Level Output Voltage2 High Level Input Current4,5 Level Input Current4 Level Input Current Pull-Up5 Three-State Leakage Current Three-State Leakage Current6 Three-State Leakage Current Pull-Up17 Supply Current (Internal)8,9 Supply Current (Analog)10 Input Capacitance11,
Test Conditions VDDEXT min, -1.0 VDDEXT min, VDDEXT max, VDDEXT VDDEXT max, VDDEXT max, VDDEXT= max, VDDEXT VDDEXT max, VDDEXT max, tCCLK VDDINT AVDD fIN=1 MHz, TCASE=25°C, VIN=1.2V
Unit
Specifications subject change without notice. Applies output bidirectional pins: AD15-0, ALE, FLAG3-0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, CLKOUT, XTAL. Output Drive Currents page typical drive current capabilities. Applies input pins: SPIDS, BOOTCFGx, CLKCFGx, TCK, RESET, CLKIN. Applies input pins with 22.5 internal pull-ups: TRST, TMS, TDI. Applies three-statable pins: FLAG3-0. Applies three-statable pins with 22.5 pull-ups: AD15-0, DAI_Px, SPICLK, EMU, MISO, MOSI. Typical internal current data reflects nominal operating conditions. Engineering-to-Engineering Note (No. TBD) further information. Characterized, tested. Applies signal pins. Guaranteed, tested.
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ABSOLUTE MAXIMUM RATINGS
Internal (Core) Supply Voltage (VDDINT)1 Analog (PLL) Supply Voltage (AVDD)1 External (I/O) Supply Voltage (VDDEXT)1 Input Voltage Output Voltage Swing Load Capacitance1 Storage Temperature Range1
ADSP-21364
+1.5 -0.3 +1.5 -0.3 +4.6 -0.5 VDDEXT1 -0.5 VDDEXT1 -65°C +150°C
Stresses greater than those listed above cause permanent damage device. These stress ratings only, functional operation device these other conditions greater than those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
SENSITIVITY
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000V readily accumulate human body test equipment discharge without detection. Although ADSP-21364 features proprietary protection circuitry, permanent damage occur devices subjected high-energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
TIMING SPECIFICATIONS
ADSP-21364's internal clock multiple CLKIN) provides clock signal timing internal memory, processor core, serial ports, parallel port required read/write strobes asynchronous access mode). During reset, program ratio between DSP's internal clock frequency external (CLKIN) clock frequency with CLKCFG1-0 pins. determine switching frequencies serial ports, divide down internal clock, using programmable divider control each port (DIVx serial ports).
ADSP-21364's internal clock switches higher frequencies than system input clock (CLKIN). generate internal clock, uses internal phase-locked loop (PLL). This PLL-based clocking minimizes skew between system clock (CLKIN) signal DSP's internal clock (the clock source parallel port logic pads). Note definitions various clock periods that function CLKIN appropriate ratio control (Table
Table ADSP-21364 CLKOUT CCLK Clock Generation Operation
Timing Requirements CLKIN CCLK Timing Requirements tCCLK tPCLK tSCLK tSPICLK
Description Input Clock Core Clock Description1 CLKIN Clock Period (Processor) Core Clock Period (Peripheral) Clock Period tCCLK Serial Port Clock Period (tPCLK) Clock Period (tPCLK) SPIR
Calculation 1/tCK 1/tCCLK
where: serial port-to-core clock ratio (wide range, determined SPORT CLKDIV) SPIR SPI-to-Core Clock Ratio (wide range, determined SPIBAUD register) DAI_Px Serial Port Clock SPICLK Clock
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ADSP-21364
Figure shows Core CLKIN ratios 6:1, 16:1 32:1 with external oscillator crystal.
CLKOUT CLKIN XTAL XTAL PLLILCLK 3:1, 8:1, 16:1 CCLK (CORE CLOCK)
CLK-CFG [1:0]
Figure Core Clock System Clock Relationship CLKIN
exact timing information given. attempt derive parameters from addition subtraction others. While addition subtraction would yield meaningful results individual device, values given this data sheet reflect statistical variations worst cases. Consequently, meaningful parameters derive longer times. Figure page under Test Conditions voltage reference levels. Switching Characteristics specify processor changes signals. Circuitry external processor must designed compatibility with these signal characteristics. Switching characteristics describe what processor will given circumstance. switching characteristics ensure that timing requirement device connected processor (such memory) satisfied. Timing Requirements apply signals that controlled circuitry external processor, such data input read operation. Timing requirements guarantee that processor operates correctly with other devices. ADSP-21364's internal clock multiple CLKIN) provides clock signal timing internal memory, processor core, serial ports, parallel port required read/write strobes asynchronous access mode). During reset, program ratio between DSP's internal clock frequency external (CLKIN) clock frequency with CLKCFG1-0 pins. determine switching frequencies serial ports, divide down internal clock, using programmable divider control each port (DIVx serial ports). ADSP-21364's internal clock switches higher frequencies than system input clock (CLKIN). generate internal clock, uses internal phase-locked loop (PLL). This PLL-based clocking minimizes skew between system clock (CLKIN) signal DSP's internal clock (the clock source parallel port logic pads). Note following definitions various clock periods that function CLKIN appropriate ratio control.
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Power Sequencing
timing requirements startup given Table Table Power Sequencing Timing Requirements (DSP Startup)
Name Timing Requirements tRSTVDD tIVDDEVDD tCLKVDD tCLKRST tPLLRST tWRST Parameter RESET before VDDINT/VDDEXT VDDINT before VDDEXT CLKIN valid after VDDINT/VDDEXT valid1 CLKIN valid before RESET deasserted control setup before RESET deasserted Subsequent RESET pulse width4 4tCK
ADSP-21364
Unit
Switching Characteristic tCORERST core reset deasserted after RESET deasserted
4096tCK tCCLK
Valid VDDINT/VDDEXT assumes that supplies fully ramped their volt rails. Voltage ramp rates vary from microseconds hundreds milliseconds depending design power supply subsystem. Assumes stable CLKIN signal, after meeting worst-case startup timing crystal oscillators. Refer your crystal oscillator manufacturer's datasheet startup time. Assume maximum oscillator startup time using XTAL internal oscillator circuit conjunction with external crystal. Based CLKIN cycles Applies after power-up sequence complete. Subsequent resets require minimum CLKIN cycles RESET held order properly initialize propagate default states pins. 4096 cycle count depends tSRST specification Table setup time met, additional CLKIN cycle added core reset time, resulting 4097 cycles maximum.
RESET
tRSTVDD
VDDINT
tIVDDEVDD
VDDEXT
tCLKVDD
CLKIN
tCLKRST
CLK_CFG1-0
tPLLRST
RSTOUT
tCORERST
Figure Power Sequencing
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ADSP-21364
Clock Input
Table Clock Input
Parameter Timing Requirements CLKIN Period tCKL CLKIN Width tCKH CLKIN Width High tCKRF CLKIN Rise/Fall (0.4V-2.0V) tCCLK CCLK Period3
19.81 3.31
Unit TBD2 TBD2 TBD2
Applies only CLKCFG1-0 default values control bits PMCTL. Applies only CLKCFG1-0 default values control bits PMCTL. changes control bits PMCTL register must meet core clock timing specification tCCLK.
CLKIN tCKH tCKL
Figure Clock Input
Clock Signals
ADSP-21364 external clock crystal. CLKIN description. programmer configure ADSP-21364 internal clock generator connecting necessary components CLKIN XTAL. Figure shows component connections used crystal operating fundamental mode.
CLKIN
XTAL
NOTE: SPECIFIC CRYSTAL SPECIFIED CONTACT CRYSTAL MANUFACTURER DETAILS. CRYSTAL SELECTION MUST COMPLY WITH CLKCFG1-0
Figure Operation (Fundamental Mode Crystal)
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Reset
Table Reset
Parameter Timing Requirements tWRST RESET Pulse Width Low1 tSRST RESET Setup Before CLKIN
ADSP-21364
4tCK
Unit
Applies after power-up sequence complete. power-up, processor's internal phase-locked loop requires more than while RESET low, assuming stable CLKIN (not including start-up time external clock oscillator).
CLKIN tWRST RESET tSRST
Figure Reset
Interrupts
following timing specification applies FLAG0, FLAG1, FLAG2 pins when they configured IRQ0, IRQ1, IRQ2 interrupts. Table Interrupts
Parameter Timing Requirement tIPW IRQx Pulse Width tPCLK Unit
FLAG2-0 (IRQ2-0) tIPW
Figure Interrupts
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ADSP-21364
Core Timer
following timing specification applies FLAG3 when configured core timer (CTIMER). Table Core Timer
Parameter Switching Characteristic tWCTIM CTIMER Pulse width tPCLK
Unit
FLAG3 (CTIMER)
tWCTIM
Figure Core Timer
Timer PWM_OUT Cycle Timing
following timing specification applies Timer[2:0] PWM_OUT (pulse width modulation) mode. Timer signals routed DAI_P[20:1] pins through SRU. Therefore, timing specifications provided below valid DAI_P[20:1] pins. Table Timer[2:0] PWM_OUT Timing
Parameter Switching Characteristic tPWMO Timer[2:0] Pulse width Output tPCLK 2(231 tPCLK Unit
tPWMO DAI_P[20:1] (TIMER[2:0])
Figure Timer[2:0] PWM_OUT Timing
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Timer WDTH_CAP Timing
following timing specification applies Timer[2:0] WDTH_CAP (pulse width count capture) mode. Timer signals routed DAI_P[20:1] pins through SRU. Therefore, timing specifications provided below valid DAI_P[20:1] pins. Table Timer[2:0] Width Capture Timing
Parameter Timing Requirement tPWI Timer[2:0] Pulse width tPCLK 2(231- tPCLK
ADSP-21364
Unit
tPWI DAI_P[20:1] (TIMER[2:0])
Figure Timer[2:0] Width Capture Timing
Direct Routing
direct connections only (for example DAI_PB01_I DAI_PB02_O). Table Routing
Parameter Timing Requirement tDPIO Delay Input Valid Output Valid Unit
DAI_Pn
DAI_Pm
tDPIO
Figure Direct Routing
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ADSP-21364
Precision Clock Generator (Direct Routing)
This timing only valid when configured such that Precision Clock Generator (PCG) takes inputs directly from pins (via buffers) sends outputs directly pins. other cases, where PCG's Table Precision Clock Generator (Direct Routing)
Parameter Timing Requirements tPCGIW Input Clock Period tSTRIG Trigger Setup Before Falling Edge Input Clock Trigger Hold After Falling Edge Input Clock tHTRIG Switching Characteristics Output Clock Frame Sync Active Edge Delay After tDPCGIO Input Clock tDTRIG Output Clock Frame Sync Delay After Trigger Output Clock Period tPCGOW
inputs outputs directly routed to/from pins (via buffers) there timing data available. Timing Parameters Switching Characteristics apply external pins (DAI_P07 DAI_P20).
Unit
tPCGOW
tPCGOW
tSTRIG
DAI_Pn PCG_TRIGx_I tHTRIG DAI_Pm PCG_EXTx_I (CLKIN) DAI_Py PCG_CLKx_O tDPCGIO tPCGIW
tPCGOW DAI_Pz PCG_FSx_O tDTRIG
Figure Precision Clock Generator (Direct Routing)
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Flags
timing specifications provided below apply FLAG[3:0] DAI_P[20:1] pins, parallel port serial peripheral interface (SPI). Table "Pin Descriptions," page more information flag use. Table Flags
Parameter Timing Requirement tFIPW FLAG[3:0] Pulse Width Switching Characteristic tFOPW FLAG[3:0] Pulse Width tPCLK
ADSP-21364
Unit
tPCLK
DAI_P[20:1] (FLAG3-0IN) (AD[15:0]
tFIPW
DAI_P[20:1] (FLAG3-0OUT) (AD[15:0]
tFOPW
Figure Flags
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ADSP-21364
Memory Read-Parallel Port
these specifications asynchronous interfacing memories (and memory-mapped peripherals) when ADSP-21364 accessing external memory space. Table 8-Bit Memory Read Cycle
Parameter Timing Requirements Address/data [7:0] Setup Before High tDRS tDRH Address/data [7:0] Hold After High tDAD Address [15:8] Data Valid Switching Characteristics tALEW Pulse Width tADAS Address/data [15:0] Setup Before Deasserted1 tADAH Address/data [15:0] Hold After Deasserted1 tALEHZ deasserted1 Address/Data[7:0] High Pulse Width tADRH Address/data [15:8] Hold After High (Data Cycle Duration) tPCLK tPCLK hold cycle specified, else
Unit
tPCLK
tPCLK tPCLK tPCLK tPCLK
tPCLK
reset, active high cycle. However, configured software active
tALEW
tALEHZ tADAS tADAH tADRH
AD[15:8]
VALID ADDRESS
VALID ADDRESS tDRS tDRH
AD[7:0]
VALID ADDRESS
tDAD
VALID DATA
Figure Read Cycle 8-bit Memory Timing
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Table 16-bit Memory Read Cycle
Parameter Timing Requirements tDRS tDRH Address/data [15:0] Setup Before High Address/data [15:0] Hold After High
ADSP-21364
Unit
Switching Characteristics tALEW Pulse Width Address/data [15:0] Setup Before Deasserted1 tADAS tADAH Address/data [15:0] Hold After Deasserted1 tALEHZ deasserted1 Address/Data[15:0] High Pulse Width (Data Cycle Duration) tPCLK tPCLK hold cycle specified, else
tPCLK tPCLK tPCLK tPCLK
reset, active high cycle. However, configured software active low.
tALEW
tADAS AD[15:0] VALID ADDRESS
tADAH
tDRS
tDRH
VALID DATA tALEHZ
Figure Read Cycle 16-bit Memory Timing
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ADSP-21364
Memory Write-Parallel Port
these specifications asynchronous interfacing memories (and memory-mapped peripherals) when ADSP-21364 accessing external memory space. Table 8-bit Memory Write Cycle
Parameter Switching Characteristics: Pulse Width tALEW tADAS Address/data [15:0] Setup Before deasserted1 tALERW Deasserted Read/Write Asserted tADAH Address/data [15:0] Hold After Deasserted Pulse Width tADWL Address/data [15:8] Address/data [15:8] Hold After High tADWH tALEHZ Deasserted1 Address/Data[15:0] High tDWS Address/data [7:0] Setup Before High tDWH Address/data [7:0] Hold After High tDAWH Address/data High (Data Cycle Duration) tPCLK tPCLK hold cycle specified, else
tPCLK tPCLK tCCLK tPCLK tPCLK tPCLK
Unit
reset, active high cycle. However, configured software active
tALEW tDAWH
tALEHZ tADAS tADAH
tADWL
tADWH
AD[15:8]
VALID ADDRESS
VALID ADDRESS tDWS tDWH
AD[7:0]
VALID ADDRESS
VALID DATA
Figure Write Cycle 8-bit Memory Timing
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Table 16-bit Memory Write Cycle
Parameter Switching Characteristics tALEW Pulse Width tADAS Address/data [15:0] Setup Before Deasserted1 tADAH Address/data [15:0] Hold After Deasserted1 Pulse Width deasserted1 Address/Data[15:0] High tALEHZ tDWS Address/data [15:0] Setup Before High tDWH Address/data [15:0] Hold After High (Data Cycle Duration) tPCLK tPCLK hold cycle specified, else
ADSP-21364
tPCLK tPCLK tPCLK tPCLK
Unit
reset, active high cycle. However, configured software active low.
tALEW
tALEHZ tADAS tADAH tDWS tDWH
AD[15:0]
VALID ADDRESS
VALID DATA
Figure Write Cycle 16-bit Memory Timing
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ADSP-21364
Serial Ports
determine whether communication possible between devices clock speed following specifications must confirmed: frame sync delay frame sync setup hold, data delay data setup hold, SCLK width. Table Serial Ports-External Clock
Parameter Timing Requirements tSFSE Setup Before SCLK (Externally Generated either Transmit Receive Mode)1 tHFSE Hold After SCLK (Externally Generated either Transmit Receive Mode)1 tSDRE Receive Data Setup Before Receive SCLK1 tHDRE Receive Data Hold After SCLK1 tSCLKW SCLK Width tSCLK SCLK Period Switching Characteristics tDFSE Delay After SCLK (Internally Generated either Transmit Receive Mode) tHOFSE Hold After SCLK (Internally Generated either Transmit Receive Mode)1 tDDTE Transmit Data Delay After Transmit SCLK1 tHDTE Transmit Data Hold After Transmit SCLK1
Serial port signals (SCLK, DxA,/DxB) routed DAI_P[20:1] pins using SRU. Therefore, timing specifications provided below valid DAI_P[20:1] pins.
Unit
Referenced sample edge. Referenced drive edge.
Table Serial Ports-Internal Clock
Parameter Timing Requirements tSFSI Setup Before SCLK (Externally Generated either Transmit Receive Mode)1 tHFSI Hold After SCLK (Externally Generated either Transmit Receive Mode)1 tSDRI Receive Data Setup Before SCLK1 tHDRI Receive Data Hold After SCLK1 Switching Characteristics tDFSI Delay After SCLK (Internally Generated Transmit Mode)2 tHOFSI Hold After SCLK (Internally Generated Transmit Mode)1 tDFSI Delay After SCLK (Internally Generated Receive Mode) tHOFSI Hold After SCLK (Internally Generated Receive Mode) tDDTI Transmit Data Delay After SCLK1 tHDTI Transmit Data Hold After SCLK1 tSCLKIW Transmit Receive SCLK Width
Unit
-2.5
-1.5 -1.5 0.5tSCLK-2 0.5tSCLK+2
Referenced sample edge. Referenced drive edge.
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Table Serial Ports-Enable Three-State
Parameter Switching Characteristics tDDTEN Data Enable from External Transmit SCLK1 Data Disable from External Transmit SCLK1 tDDTTE tDDTIN Data Enable from Internal Transmit SCLK1
ADSP-21364
Unit
Referenced drive edge.
Table Serial Ports-External Late Frame Sync
Parameter Switching Characteristics tDDTLFSE Data Delay from Late External Transmit External Receive with tDDTENFS Data Enable
Unit
tDDTLFSE tDDTENFS parameters apply Left-justified Sample Pair well serial mode,
EXTERNAL RECEIVE WITH DIA_P[20:0] (SCLK) DRIVE SAMPLE tHFSE/I tSFSE/I DIA_P[20:0] (FS) tDDTENFS DIA_P[20:0] (DXA/DXB) tDDTLFSE tHDTE/I tDDTE/I DRIVE
LATE EXTERNAL TRANSMIT DRIVE SAMPLE tHFSE/I DRIVE
DIA_P[20:0] (SCLK)
tSFSE/I DIA_P[20:0] (FS)
tDDTENFS DIA_P[20:0] (DXA/DXB) tDDTLFSE tHDTE/I
tDDTE/I
NOTE SERIAL PORT SIGNALS (SCLK, DXA,/DXB) ROUTED DAI_P[20:1] PINS USING SRU. TIMING SPECIFICATIONS PROVIDED HERE VALID DAI_P[20:1] PINS.
Figure External Late Frame Sync1
This figure reflects changes made support Left-justified Sample Pair mode.
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ADSP-21364
DATA RECEIVE- INTERNAL CLOCK DRIVE EDGE tSCLKIW DAI_P[20:1] (SCLK) tDFSI tHOFSI DAI_P[20:1] (FS) tSDRI DAI_P[20:1] (DXA/DXB) tHDRI DAI_P[20:1] (DXA/DXB) tSFSI tHFSI DAI_P[20:1] (FS) DAI_P[20:1] (SCLK) SAMPLE EDGE
DATA RECEIVE- EXTERNAL CLOCK DRIVE EDGE tSCLKW SAMPLE EDGE
tDFSE tHOFSE tSFSE
tHFSE
tSDRE
tHDRE
NOTE: EITHER RISING EDGE FALLING EDGE SCLK (EXTERNAL), SCLK (INTERNAL) USED ACTIVE SAMPLING EDGE.
DATA TRANSMIT INTERNAL CLOCK DRIVE EDGE tSCLKIW DAI_P[20:1] (SCLK) tDFSI tHOFSI DAI_P[20:1] (FS) tHDTI DAI_P[20:1] (DXA/DXB) tDDTI DAI_P[20:1] (DXA/DXB) tSFSI tHFSI DAI_P[20:1] (FS) DAI_P[20:1] (SCLK) SAMPLE EDGE
DATA TRANSMIT EXTERNAL CLOCK DRIVE EDGE tSCLKW SAMPLE EDGE
tDFSE tHOFSE tSFSE tHFSE
tHDTE
tDDTE
NOTE: EITHER RISING EDGE FALLING EDGE SCLK (EXTERNAL), SCLK (INTERNAL) USED ACTIVE SAMPLING EDGE.
DRIVE EDGE DAI_P[20:1] SCLK (EXT) SCLK tDDTEN tDDTTE
DRIVE EDGE
DAI_P[20:1] XA/DXB DRIVE EDGE DAI_P[20:1] SCLK (INT) SCLK tDDTIN tDDTTI DRIVE EDGE
DAI_P[20:1] XA/DXB
Figure Serial Ports
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Input Data Port
timing requirements given Table 26.IDP Signals (SCLK, SDATA) routed DAI_P[20:1] pins using SRU. Therefore, timing specifications provided below valid DAI_P[20:1] pins. Table
Parameter Timing Requirements tSIFS Setup Before SCLK Rising Edge1 tSIHFS Hold After SCLK Rising Edge1 SData Setup Before SCLK Rising Edge1 tSISD tSIHD SData Hold After SCLK Rising Edge1 tIDPCLKW Clock Width tIDPCLK Clock Period
ADSP-21364
Unit
DATA, SCLK, come from pins. SCLK also come SPORTs. PCG's input either CLKIN pins.
SAMPLE EDGE tSISCLKW DAI_P[20:1] (SCLK) tSIHFS
tSISFS DAI_P[20:1] (FS) tSISD DAI_P[20:1] (SDATA)
tSIHD
Figure Master Timing
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ADSP-21364
Parallel Data Acquisition Port (PDAP)
timing requirements PDAP provided Table PDAP parallel mode operation channel IDP. details operation IDP, chapter ADSP-2136x Peripherals Manual. Note that Table Parallel Data Acquisition Port (PDAP)
Parameter Timing Requirements tSPCLKEN PDAP_CLKEN Setup Before PDAP_CLK Sample Edge1 tHPCLKEN PDAP_CLKEN Hold After PDAP_CLK Sample Edge1 PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge1 tPDSD tPDHD PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge1 tPDCLKW Clock Width tPDCLK Clock Period tPDHLDD Delay PDAP strobe after last PDAP_CLK capture edge word tPDSTRB PDAP Strobe Pulse Width
most significant bits external PDAP data provided through either parallel port AD[15:0] DAI_P[20:5] pins. remaining bits only sourced through DAI_P[4:1]. timing below valid DAI_P[20:1] pins AD[15:0] pins.
tPCLK tPCLK
Unit
Source pins DATA ADDR[7:0], DATA[7:0], pins. Source pins SCLK are: pins, CLKIN through PCG, pins through PCG.
SAMPLE EDGE tPDCLKW DAI_P[20:1] (PDAP_CLK) tSPHLD DAI_P[20:1] (PDAP_CLKEN) tPDSD DATA tPDHD tHPHLD
DAI_P[20:1] (PDAP_STROBE)
tPDSTRB tPDHLDD
Figure PDAP Timing
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Sample Rate Converter
ADSP-21364
S/PDIF Compatible Transiever
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ADSP-21364
Interface-Master
Table Interface Protocol Master Switching Timing Specifications
Parameter Timing Requirements tSSPIDM Data Input Valid SPICLK edge (Data Input Set-up Time) tHSPIDM SPICLK Last Sampling Edge Data Input Valid Switching Characteristics tSPICLKM Serial Clock Cycle tSPICHM Serial Clock High Period tSPICLM Serial Clock Period tDDSPIDM SPICLK Edge Data Valid (data delay time) tHDSPIDM SPICLK Edge Data Valid (data hold time) FLAG3-0IN (SPI Device Select) First SPICLK Edge tSDSCIM tHDSM Last SPICLK edge FLAG3-0IN high tSPITDM Sequential Transfer Delay
Unit
tPCLK tPCLK tPCLK tPCLK tPCLK tPCLK
FLAG3-0 (OUTPUT)
tSDSCIM
SPICLK (OUTPUT)
tSPICHM
tSPICLM
tSPICLKM
tHDSM
tSPICLM
SPICLK (OUTPUT)
tSPICHM
tDDSPIDM
MOSI (OUTPUT)
HDSPIDM
tSSPIDM
CPHASE=1 MISO (INPUT) VALID
tHSSPIDM
VALID
tHSPIDM
tDDSPIDM
MOSI (OUTPUT) CPHASE=0 MISO (INPUT)
tHDSPIDM
VALID
tHSPIDM
VALID
Figure Master Timing
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Interface-Slave
Table Interface Protocol -Slave Switching Timing Specifications
Parameter Timing Requirements tSPICLKS tSPICHS tSPICLS tSDSCO Serial Clock Cycle Serial Clock High Period Serial Clock Period SPIDS Assertion First SPICLK edge CPHASE CPHASE Last SPICLK Edge SPIDS Asserted CPHASE Data Input Valid SPICLK Edge (Data Input Set-up Time) SPICLK Last Sampling Edge Data Input Valid SPIDS Deassertion Pulse Width (CPHASE=0) tPCLK tPCLK tPCLK tPCLK tPCLK tPCLK tPCLK
ADSP-21364
Unit
tHDS tSSPIDS tHSPIDS tSDPPW
Switching Characteristics tDSOE SPIDS Assertion Data Active tDSDHI SPIDS Deassertion Data High Impedance tDDSPIDS SPICLK Edge Data Valid (Data Delay Time) SPICLK Edge Data Valid (Data Hold Time) tHDSPIDS tDSOV SPIDS Assertion Data Valid (CPHASE=0)
tPCLK
tPCLK
SPIDS (INPUT)
SPICLK (INPUT)
tSPICLS
tSPICL tHDS tSDPPW
tSDSCO
SPICLK (INPUT)
tSPICLS
tSPICHS
tDSOE
tDDSPIDS tDDSPIDS
tDSDHI
MISO (OUTPUT) CPHASE=1 MOSI (INPUT)
tHSPIDS tSSPIDS
VALID
tSSPIDS
VALID
tDSOV
MISO (OUTPUT) CPHASE=0 MOSI (INPUT)
tDDSPIDS
tHDLSBS
tDSDHI
tSSPIDS
VALID VALID
tHSPIDS
Figure Slave Timing
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ADSP-21364
JTAG Test Access Port Emulation
Table JTAG Test Access Port Emulation
Parameter Timing Requirements tTCK Period tSTAP TDI, Setup Before High tHTAP TDI, Hold After High tSSYS System Inputs Setup Before Low1 tHSYS System Inputs Hold After Low1 tTRSTW TRST Pulse Width Switching Characteristics tDTDO Delay From System Outputs Delay After Low2 tDSYS
4tCK
Unit
System Inputs AD15-0, SPIDS, CLKCFG1-0, RESET, BOOTCFG1-0, MISO, MOSI, SPICLK, DAI_Px, FLAG3-0. System Outputs MISO, MOSI, SPICLK, DAI_Px, AD15-0, FLAG3-0, CLKOUT, EMU, ALE.
tTCK tSTAP tDTDO tSSYS SYSTEM INPUTS tDSYS SYSTEM OUTPUTS tHSYS tHTAP
Figure IEEE 11499.1 JTAG Test Access Port
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OUTPUT DRIVE CURRENTS
Figure shows typical characteristics output drivers ADSP-21364. curves represent current drive capability output drivers function output voltage.
ADSP-21364
CAPACITIVE LOADING
Output delays holds based standard capacitive loads: pins (see Figure 30). Figure shows graphically output delays holds vary with load capacitance. graphs Figure Figure Figure linear outside ranges shown Typical Output Delay Load Capacitance Typical Output Rise Time (20%-80%, V=Min) Load Capacitance.
LOAD (VDDEXT) CURRENT
3.47V, 3.3V, 3.13V,
16.0 14.0
RISE FALL TIMES (.694V 2.77V, 80%)
-100 -120 SOURCE (VDDEXT) VOLTAGE 3.47V, 3.3V, 3.13V,
12.0 10.0
Figure ADSP-21364 Typical Drive
TEST CONDITIONS
signal specifications (timing parameters) appear Table page through Table page These include output disable time, output enable time, capacitive loading. timing specifications SHARC apply voltage reference levels Figure
LOAD CAPACITANCE
Figure Typical Output Rise/Fall Time (20%-80%, VDDEXT Max)
16.0
1.5V
14.0
RISE FALL TIMES (0.694v 2.77v, 80%)
OUTPUT 30pF
12.0 10.0
Figure Equivalent Device Loading Measurements (Includes Fixtures)
INPUT 1.5V OUTPUT
LOAD CAPACITANCE
1.5V
Figure Typical Output Fall Time (20%-80%, VDDEXT Min)
Figure Voltage Reference Levels Measurements
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ADSP-21364
Where:
Ambient Temperature
OUTPUT DELAY HOLD
Values provided package comparison design considerations when external heatsink required. Values provided package comparison design considerations. Table Thermal Characteristics Ball BGA1
Parameter
NOMINAL
LOAD CAPACITANCE
Figure Typical Output Delay Hold Load Capacitance Ambient Temperature)
Condition Airflow Airflow Airflow Airflow Airflow Airflow
Typical
Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W
thermal characteristics values provided this table modeled values.
ENVIRONMENTAL CONDITIONS
ADSP-21364 available 136-Ball Grid Array (BGA) package.
THERMAL CHARACTERISTICS
ADSP-21364 processor rated performance over commercial temperature range, TAMB 70°C. Table airflow measurements comply with JEDEC standards JESD51-2 JESD51-6 junction-to-board measurement complies with JESD51-8. junction-to-case measurement complies with MIL- STD-883. measurements 2S2P JEDEC test board. determine Junction Temperature device while application PCB, use: CASE Where: Junction temperature TCASE= Case temperature (0C) measured center package Junction-to-Top package) characterization parameter Typical value from tables below Power dissipation Note #TBD Values provided package comparison design considerations. used order approximation equation:
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136-BALL CONFIGURATIONS
Table 136-Ball Assignments
Name CLKCFG0 XTAL CLKOUT MOSI MISO SPIDS VDDINT VDDINT FLAG3 Pin# Name CLKCFG1 VDDEXT CLKIN TRST AVSS AVDD VDDEXT SPICLK RESET VDDINT FLAG1 FLAG0 FLAG2 DAI_P20 (SFS45) Pin# Name BOOTCFG1 BOOTCFG0 VDDINT Pin# Name VDDINT VDDINT
ADSP-21364
Pin#
VDDINT VDDEXT DAI_P19 (SCLK45)
VDDEXT DAI_P18 (SD5B) DAI_P17 (SD5A)
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ADSP-21364
Table 136-Ball Assignments (Continued)
Name VDDINT DAI_P16 (SD4B) AD15 VDDINT VDDEXT VDDINT DAI_P2 (SD0B) VDDEXT DAI_P4 (SFS0) VDDINT VDDINT DAI_P10 (SD2B) Pin# Name VDDINT DAI_P15 (SD4A) AD14 AD13 AD12 AD11 AD10 DAI_P1 (SD0A) DAI_P3 (SCLK0) DAI_P5 (SD1A) DAI_P6 (SD1B) DAI_P7 (SCLK1) DAI_P8 (SFS1) DAI_P9 (SD2A) DAI_P11 (SD3A) Pin# Name DAI_P14 (SFS23)
Pin# Name DAI_P12 (SD3B) DAI_P13 (SCLK23) Pin#
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ADSP-21364
VDDINT VDDEXT GND* AVSS AVDD SIGNALS
*USE CENTER BLOCK GROUND PINS PROVIDE THERMAL PATHWAYS YOUR PRINTED CIRCUIT BOARD'S GROUND PLANE.
Figure 136-Ball Assignments (Bottom View, Summary)
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January 2004
ADSP-21364
PACKAGE DIMENSIONS
ADSP-21364 available 136-ball package. dimensions millimeters (mm).
12.00
BALL CORNER
0.80
10.40
BALL CORNER
View
12.00
10.40
DETAIL 1.70
0.80
DETAIL 1.31 1.21 1.10 0.25 0.50 0.46 0.40 BALL DIAMETER 0.12 SEATING PLANE
DIMENSIONS MILIMETERS (MM). ACTUAL POSITION BALL GRID WITHIN 0.150 IDEAL POSITION RELATIVE PACKAGE EDGES. ACTUAL POSITION EACH BALL WITHIN 0.08 IDEAL POSITION RELATIVE BALL GRID. COMPLIANT JEDEC REGISTERED OUTLINE MO-205-AE WITH EXCEPTION DIMENSION
Figure 136-ball
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ORDERING GUIDE
Part Number1,2,3 ADSP-21364SKBCZENG ADSP-21364SKBC-ENG
ADSP-21364
Ambient Temperature Instruction Rate Range
On-Chip SRAM
Operating Voltage INT/3.3 INT/3.3
Packages 136-Lead free) 136-Lead
indicates commercial grade temperature (0°C +70°C). indicates Ball Grid Array package. indicates Lead Free package. more information about lead free package offerings, please visit www.analog.com.
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ADSP-21364
2004 Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective companies.
PR04624-0-1/04(PrA)
Page January 2004
www.analog.com
Rev.

High performance 32-bit/40-bit floating point processor optimized prof

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